Attachment #86445 for bug #132056

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 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/*
 * TOTEST
 *	- speed setting
 *	- suspend/resume
 */

#include <linux/config.h>
#include <linux/crc32.h>
#include <linux/kernel.h>

#include "sky2.h"

#define DRV_NAME		"sky2"
#define DRV_VERSION		"1.3-rc1"
#define PFX			DRV_NAME " "

/*

 * a receive requires one (or two if using 64 bit dma).
 */

#define is_ec_a1(hw) \
	unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
		 (hw)->chip_rev == CHIP_REV_YU_EC_A1)

#define RX_LE_SIZE	    	512
#define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
#define RX_MAX_PENDING		(RX_LE_SIZE/2 - 2)

#define TX_RING_SIZE		512
#define TX_DEF_PENDING		(TX_RING_SIZE - 1)
#define TX_MIN_PENDING		64
#define MAX_SKB_TX_LE		(4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)

#define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
#define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))

#define NAPI_WEIGHT		64
#define PHY_RETRIES		1000

#define RING_NEXT(x,s)	(((x)+1) & ((s)-1))

static const u32 default_msg =
    NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
    | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
    | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;

static int debug = -1;		/* defaults above */
module_param(debug, int, 0);

module_param(copybreak, int, 0);
MODULE_PARM_DESC(copybreak, "Receive copy threshold");

static int disable_msi = 0;
module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

static int idle_timeout = 100;
module_param(idle_timeout, int, 0);
MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");

static const struct pci_device_id sky2_id_table[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },

	pr_debug("sky2_set_power_state %d\n", state);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
	vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
		(power_control & PCI_PM_CAP_PME_D3cold);

	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);

	power_control |= PCI_PM_CTRL_PME_STATUS;
	power_control &= ~(PCI_PM_CTRL_STATE_MASK);

			sky2_write8(hw, B2_Y2_CLK_GATE, 0);

		/* Turn off phy power saving */
		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

		/* looks like this XL is back asswards .. */

			if (hw->ports > 1)
				reg1 |= PCI_Y2_PHY2_COMA;
		}

		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
			sky2_pci_write32(hw, PCI_DEV_REG3, 0);
			reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
			reg1 &= P_ASPM_CONTROL_MSK;
			sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
			sky2_pci_write32(hw, PCI_DEV_REG5, 0);
		}

		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

		break;

	case PCI_D3hot:
	case PCI_D3cold:
		/* Turn on phy power saving */
		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
		else
			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);

		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			sky2_write8(hw, B2_Y2_CLK_GATE, 0);

		ret = -1;
	}

	sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	return ret;
}

	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
	u16 ctrl, ct1000, adv, pg, ledctrl, ledover;

	if (sky2->autoneg == AUTONEG_ENABLE &&
	    (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |

			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

			if (sky2->autoneg == AUTONEG_ENABLE &&
			    (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
				ctrl &= ~PHY_M_PC_DSC_MSK;
				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
			}

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			      PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
			      PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */

		/* set Polarity Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,

		/* restore page register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
		break;
	case CHIP_ID_YUKON_EC_U:
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

		/* select page 3 to access LED control register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			      PHY_M_LEDC_INIT_CTRL(8) |	/* 10 Mbps */
			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
			      PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */

		/* set Blink Rate in LED Timer Control Register */
		gm_phy_write(hw, port, PHY_MARV_INT_MASK,
			     ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
		/* restore page register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
		break;

	default:
		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
	}

	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
		/* apply fixes in PHY AFE */
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);

		/* increase differential signal amplitude in 10BASE-T */
		gm_phy_write(hw, port, 0x18, 0xaa99);
		gm_phy_write(hw, port, 0x17, 0x2011);
	}

		/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
		gm_phy_write(hw, port, 0x18, 0xa204);
		gm_phy_write(hw, port, 0x17, 0x2002);

		/* set page register to 0 */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	} else {
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
			/* turn on 100 Mbps LED (LED_LINK100) */
			ledover |= PHY_M_LED_MO_100(MO_LED_ON);
		}

		if (ledover)
			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

	}
	/* Enable phy interrupt on auto-negotiation complete (or link up) */
	if (sky2->autoneg == AUTONEG_ENABLE)
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);

/* Force a renegotiation */
static void sky2_phy_reinit(struct sky2_port *sky2)
{
	spin_lock_bh(&sky2->phy_lock);
	sky2_phy_init(sky2->hw, sky2->port);
	spin_unlock_bh(&sky2->phy_lock);
}

static void sky2_mac_init(struct sky2_hw *hw, unsigned port)


		switch (sky2->speed) {
		case SPEED_1000:
			reg &= ~GM_GPCR_SPEED_100;
			reg |= GM_GPCR_SPEED_1000;
			break;
		case SPEED_100:
			reg &= ~GM_GPCR_SPEED_1000;
			reg |= GM_GPCR_SPEED_100;
			break;
		case SPEED_10:
			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
			break;
		}

		if (sky2->duplex == DUPLEX_FULL)
			reg |= GM_GPCR_DUP_FULL;

		/* turn off pause in 10/100mbps half duplex */
		else if (sky2->speed != SPEED_1000 &&
			 hw->chip_id != CHIP_ID_YUKON_EC_U)
			sky2->tx_pause = sky2->rx_pause = 0;
	} else
		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;



	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));

	spin_lock_bh(&sky2->phy_lock);
	sky2_phy_init(hw, port);
	spin_unlock_bh(&sky2->phy_lock);

	/* MIB clear */
	reg = gma_read16(hw, port, GM_PHY_ADDR);
	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

	for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
		gma_read16(hw, port, i);
	gma_write16(hw, port, GM_PHY_ADDR, reg);

	/* transmit control */


	/* Configure Rx MAC FIFO */
	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
		     GMF_OPER_ON | GMF_RX_F_FL_ON);

	/* Flush Rx MAC FIFO on any flow control or error */
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);


}

/* Assign Ram Buffer allocation.
 * start and end are in units of 4k bytes
 * ram registers are in units of 64bit words
 */
static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
{
	u32 start, end;

	start = startk * 4096/8;
	end = (endk * 4096/8) - 1;
	end = start + len - 1;

	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
	sky2_write32(hw, RB_ADDR(q, RB_START), start);

	sky2_write32(hw, RB_ADDR(q, RB_RP), start);

	if (q == Q_R1 || q == Q_R2) {
		u32 space = (endk - startk) * 4096/8;
		u32 tp = space - space/4;

		/* On receive queue's set the thresholds
		 * give receiver priority when > 3/4 full
		 * send pause when down to 2K
		 */
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);

		tp = space - 2048/8;
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
	} else {
		/* Enable store & forward on Tx queue's because
		 * Tx FIFO is only 1K on Yukon

{
	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

	sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
	return le;
}

/* Update chip's next pointer */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
 */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
				u16 idx, u16 *last, u16 size)
{
	wmb();
	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
	mmiowb();
		if (hwget == 0) {
			/* Start prefetching again */
			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
			goto setnew;
		}

		if (hwget == size - 1) {
			/* set watermark to one list element */
			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);

			/* set put index to first list element */
			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
		} else		/* have hardware go to end of list */
			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
				     size - 1);
	} else {
setnew:
		sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
	}
	*last = idx;
}


static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
{
	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
	sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
	return le;
}

/* Return high part of DMA address (could be 32 or 64 bit) */
static inline u32 high32(dma_addr_t a)
{
	return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
}

/* Build description to hardware about buffer */
static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
{
	struct sky2_rx_le *le;
	u32 hi = high32(map);

	le = sky2_next_rx(sky2);
	le->addr = cpu_to_le32((u32) map);
	le->length = cpu_to_le16(len);
	le->ctrl = sky2->rx_csum ? CALSUM : 0;
	le->opcode = OP_PACKET | HW_OWNER;
}


	if (!netif_running(dev))
		return -ENODEV;	/* Phy still in reset */

	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = PHY_ADDR_MARV;


	case SIOCGMIIREG: {
		u16 val = 0;

		spin_lock_bh(&sky2->phy_lock);
		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
		spin_unlock_bh(&sky2->phy_lock);

		data->val_out = val;
		break;

		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

		spin_lock_bh(&sky2->phy_lock);
		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
				   data->val_in);
		spin_unlock_bh(&sky2->phy_lock);
		break;
	}
	return err;

	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

	spin_lock_bh(&sky2->tx_lock);

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
	sky2->vlgrp = grp;

	spin_unlock_bh(&sky2->tx_lock);
}

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

	spin_lock_bh(&sky2->tx_lock);

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
	if (sky2->vlgrp)
		sky2->vlgrp->vlan_devices[vid] = NULL;

	spin_unlock_bh(&sky2->tx_lock);
}
#endif


	skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
	if (likely(skb)) {
		unsigned long p	= (unsigned long) skb->data;
		skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
			((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
	}

	return skb;


	sky2->rx_put = sky2->rx_next = 0;
	sky2_qset(hw, rxq);

	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
		/* MAC Rx RAM Read is controlled by hardware */
		sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
	}

	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

	rx_set_checksum(sky2);

		sky2_rx_add(sky2, re->mapaddr);
	}

 	/* Truncate oversize frames */
 	sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
 	sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

	/* Tell chip about available buffers */
	sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
	sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
	return 0;
nomem:
	sky2_rx_clean(sky2);

	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u32 ramsize, rxspace, imask;
	int err = -ENOMEM;

	if (netif_msg_ifup(sky2))


	sky2_mac_init(hw, port);

	/* Determine available ram buffer space (in 4K blocks).
	 * Note: not sure about the FE setting below yet
	 */
	if (hw->chip_id == CHIP_ID_YUKON_FE)
		ramsize = 4;
	else
		ramsize = sky2_read8(hw, B2_E_0);

	/* Give transmitter one third (rounded up) */
	rxspace = ramsize - (ramsize + 2) / 3;

	/* 2/3 for Rx */
	rxspace = (2 * ramsize) / 3;
	sky2_ramset(hw, rxqaddr[port], 0, rxspace);
	sky2_ramset(hw, txqaddr[port], rxspace, ramsize);

	/* Make sure SyncQ is disabled */
	sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
		    RB_RST_SET);

	sky2_qset(hw, txqaddr[port]);
	if (hw->chip_id == CHIP_ID_YUKON_EC_U)
		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

	/* Set almost empty threshold */
	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);

	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
			   TX_RING_SIZE - 1);

		goto err_out;

	/* Enable interrupts from phy/mac for port */
	imask = sky2_read32(hw, B0_IMSK);
	imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
	sky2_write32(hw, B0_IMSK, imask);

	return 0;

err_out:

/* Modular subtraction in ring */
static inline int tx_dist(unsigned tail, unsigned head)
{
	return (head - tail) & (TX_RING_SIZE - 1);
}

/* Number of list elements available for next tx */

}

/* Estimate of number of transmit list elements required */
static unsigned tx_le_req(const struct sk_buff *skb)
{
	unsigned count;


	struct sky2_tx_le *le = NULL;
	struct tx_ring_info *re;
	unsigned i, len;
	int avail;
	dma_addr_t mapping;
	u32 addr64;
	u16 mss;
	u8 ctrl;

	/* No BH disabling for tx_lock here.  We are running in BH disabled
	 * context and TX reclaim runs via poll inside of a software
	 * interrupt, and no related locks in IRQ processing.
	 */
	if (!spin_trylock(&sky2->tx_lock))
		return NETDEV_TX_LOCKED;


		 */
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);
			if (net_ratelimit())
				printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
				       dev->name);
		}
		spin_unlock(&sky2->tx_lock);


		/* just drop the packet if non-linear expansion fails */
		if (skb_header_cloned(skb) &&
		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
			dev_kfree_skb(skb);
			goto out_unlock;
		}



		mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
				       frag->size, PCI_DMA_TODEVICE);
		addr64 = high32(mapping);
		if (addr64 != sky2->tx_addr64) {
			le = get_tx_le(sky2);
			le->tx.addr = cpu_to_le32(addr64);

		le->opcode = OP_BUFFER | HW_OWNER;

		fre = sky2->tx_ring
		    + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
		pci_unmap_addr_set(fre, mapaddr, mapping);
	}

	re->idx = sky2->tx_prod;
	le->ctrl |= EOP;

	avail = tx_avail(sky2);
	if (mss != 0 || avail < TX_MIN_PENDING) {
 		le->ctrl |= FRC_STAT;
		if (avail <= MAX_SKB_TX_LE)
			netif_stop_queue(dev);
	}

	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
		netif_stop_queue(dev);

out_unlock:
	mmiowb();
	spin_unlock(&sky2->tx_lock);

	dev->trans_start = jiffies;

		struct tx_ring_info *re = sky2->tx_ring + put;
		struct sk_buff *skb = re->skb;

		nxt = re->idx;
		BUG_ON(nxt >= TX_RING_SIZE);
		prefetch(sky2->tx_ring + nxt);



		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
			struct tx_ring_info *fre;
			fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
			pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
				       skb_shinfo(skb)->frags[i].size,
				       PCI_DMA_TODEVICE);
		}

		dev_kfree_skb(skb);
	}

	spin_lock(&sky2->tx_lock);
	sky2->tx_cons = put;
	if (tx_avail(sky2) > MAX_SKB_TX_LE)
		netif_wake_queue(dev);
	spin_unlock(&sky2->tx_lock);
}

/* Cleanup all untransmitted buffers, assume transmitter not running */
static void sky2_tx_clean(struct sky2_port *sky2)
{
	spin_lock_bh(&sky2->tx_lock);
	sky2_tx_complete(sky2, sky2->tx_prod);
	spin_unlock_bh(&sky2->tx_lock);
}

/* Network shutdown */

	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 ctrl;
	u32 imask;

	/* Never really got started! */
	if (!sky2->tx_le)

	/* Stop more packets from being queued */
	netif_stop_queue(dev);

	/* Disable port IRQ */
	local_irq_disable();
	hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
	local_irq_enable();

	flush_scheduled_work();

	sky2_phy_reset(hw, port);

	/* Stop transmitter */

	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

	/* Disable port IRQ */
	imask = sky2_read32(hw, B0_IMSK);
	imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
	sky2_write32(hw, B0_IMSK, imask);

	/* turn off LED's */
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);


	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

	reg = gma_read16(hw, port, GM_GP_CTRL);
	if (sky2->autoneg == AUTONEG_DISABLE) {
		reg |= GM_GPCR_AU_ALL_DIS;

		/* Is write/read necessary?  Copied from sky2_mac_init */
		gma_write16(hw, port, GM_GP_CTRL, reg);
		gma_read16(hw, port, GM_GP_CTRL);

		switch (sky2->speed) {
		case SPEED_1000:
			reg &= ~GM_GPCR_SPEED_100;
			reg |= GM_GPCR_SPEED_1000;
			break;
		case SPEED_100:
			reg &= ~GM_GPCR_SPEED_1000;
			reg |= GM_GPCR_SPEED_100;
			break;
		case SPEED_10:
			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
			break;
		}
	} else
		reg &= ~GM_GPCR_AU_ALL_DIS;

	if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
		reg |= GM_GPCR_DUP_FULL;


	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

	if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		u16 led = PHY_M_LEDC_LOS_CTRL(1);	/* link active */

		switch(sky2->speed) {
		case SPEED_10:
			led |= PHY_M_LEDC_INIT_CTRL(7);
			break;

		case SPEED_100:
			led |= PHY_M_LEDC_STA1_CTRL(7);
			break;

		case SPEED_1000:
			led |= PHY_M_LEDC_STA0_CTRL(7);
			break;
		}

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
			     PHY_M_LEDC_INIT_CTRL(sky2->speed ==
						  SPEED_10 ? 7 : 0) |
			     PHY_M_LEDC_STA1_CTRL(sky2->speed ==
						  SPEED_100 ? 7 : 0) |
			     PHY_M_LEDC_STA0_CTRL(sky2->speed ==
						  SPEED_1000 ? 7 : 0));
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	}


	sky2->speed = sky2_phy_speed(hw, aux);

	/* Pause bits are offset (9..8) */
	if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
		aux >>= 6;

	sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;

	return 0;
}

/* Interrupt from PHY */
static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
 * because accessing phy registers requires spin wait which might
 * cause excess interrupt latency.
 */
static void sky2_phy_task(void *arg)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
	u16 istatus, phystat;

	spin_lock(&sky2->phy_lock);
	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

	if (!netif_running(dev))
		goto out;

	if (netif_msg_intr(sky2))
		printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",

			sky2_link_down(sky2);
	}
out:
	spin_unlock(&sky2->phy_lock);

	local_irq_disable();
	hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
	local_irq_enable();
}


/* Transmit timeout is only called if we are running, carries is up
 * and tx queue is full (stopped).
 */
static void sky2_tx_timeout(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned txq = txqaddr[sky2->port];
	u16 report, done;

	if (netif_msg_timer(sky2))
		printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

	report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
	done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));

	printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
	       dev->name,
	       sky2->tx_cons, sky2->tx_prod, report, done);

	if (report != done) {
		printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");

		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	} else if (report != sky2->tx_cons) {
		printk(KERN_INFO PFX "status report lost?\n");

		spin_lock_bh(&sky2->tx_lock);
		sky2_tx_complete(sky2, report);
		spin_unlock_bh(&sky2->tx_lock);
	} else {
		printk(KERN_INFO PFX "hardware hung? flushing\n");

		sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
		sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

		sky2_tx_clean(sky2);

		sky2_qset(hw, txq);
		sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
	}
}


/* Want receive buffer size to be multiple of 64 bits
 * and incl room for vlan and truncation
 */
static inline unsigned sky2_buf_size(int mtu)
{
	return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
}

static int sky2_change_mtu(struct net_device *dev, int new_mtu)

	struct sky2_hw *hw = sky2->hw;
	int err;
	u16 ctl, mode;
	u32 imask;

	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
		return -EINVAL;

		return 0;
	}

	imask = sky2_read32(hw, B0_IMSK);
	sky2_write32(hw, B0_IMSK, 0);

	dev->trans_start = jiffies;	/* prevent tx timeout */
	netif_stop_queue(dev);
	netif_poll_disable(hw->dev[0]);

	synchronize_irq(hw->pdev->irq);

	ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
	gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
	sky2_rx_stop(sky2);

	sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);

	err = sky2_rx_start(sky2);
	sky2_write32(hw, B0_IMSK, imask);

	if (err)
		dev_close(dev);

	if (!(status & GMR_FS_RX_OK))
		goto resubmit;

	if (length > sky2->netdev->mtu + ETH_HLEN)
		goto oversize;

	if (length < copybreak) {

	sky2_rx_add(sky2, re->mapaddr);

	/* Tell receiver about new buffers. */
	sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
		     &sky2->rx_last_put, RX_LE_SIZE);

	return skb;


error:
	++sky2->net_stats.rx_errors;

	if (netif_msg_rx_err(sky2) && net_ratelimit())
		printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
		       sky2->netdev->name, status, length);


	goto resubmit;
}

/* Transmit complete */
static inline void sky2_tx_done(struct net_device *dev, u16 last)
 */
#define TX_NO_STATUS	0xffff

static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	if (netif_running(dev)) {
		spin_lock(&sky2->tx_lock);
		sky2_tx_complete(sky2, last);
		spin_unlock(&sky2->tx_lock);
	}
}

/* Process status response ring */
static int sky2_status_intr(struct sky2_hw *hw, int to_do)
 * one poll routine.
 */
static int sky2_poll(struct net_device *dev0, int *budget)
{
	int work_done = 0;
	u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
	unsigned int work_done = 0;
	u16 hwidx;
	u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };

	hwidx = sky2_read16(hw, STAT_PUT_IDX);
	BUG_ON(hwidx >= STATUS_RING_SIZE);
	rmb();

	while (hw->st_idx != hwidx) {
		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
		struct net_device *dev;
		struct sky2_port *sky2;
		struct sk_buff *skb;
		u32 status;
		u16 length;
		u8 op;

		hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
		hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
		prefetch(hw->st_le + hw->st_idx);

		BUG_ON(le->link >= 2);
		dev = hw->dev[le->link];
		if (dev == NULL || !netif_running(dev))
			continue;

		sky2 = netdev_priv(dev);
		length = le->length;
		status = le->status;
		op = le->opcode & ~HW_OWNER;
		le->opcode = 0;

		switch (le->opcode & ~HW_OWNER) {
		case OP_RXSTAT:
			skb = sky2_receive(sky2, length, status);
			if (!skb)


		case OP_TXINDEXLE:
			/* TX index reports status for both ports */
			BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
			sky2_tx_done(hw->dev[0], status & 0xfff);
			if (hw->dev[1])
				sky2_tx_done(hw->dev[1],
				     ((status >> 24) & 0xff)
					     | (u16)(length & 0xf) << 8);
			break;

		default:
			if (net_ratelimit())
				printk(KERN_WARNING PFX
				       "unknown status opcode 0x%x\n", le->opcode);
			goto exit_loop;
		}
	}

exit_loop:
	return work_done;
	mmiowb();

	sky2_tx_check(hw, 0, tx_done[0]);
	sky2_tx_check(hw, 1, tx_done[1]);

	if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
		/* need to restart TX timer */
		if (is_ec_a1(hw)) {
			sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
			sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
		}

		netif_rx_complete(dev0);
		hw->intr_mask |= Y2_IS_STAT_BMU;
		sky2_write32(hw, B0_IMSK, hw->intr_mask);
		mmiowb();
		return 0;
	} else {
		*budget -= work_done;
		dev0->quota -= work_done;
		return 1;
	}
}

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
{
	struct net_device *dev = hw->dev[port];

	if (net_ratelimit())
		printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
		       dev->name, status);

	if (status & Y2_IS_PAR_RD1) {
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: ram data read parity error\n",
			       dev->name);
		/* Clear IRQ */
		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
	}

	if (status & Y2_IS_PAR_WR1) {
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: ram data write parity error\n",
			       dev->name);

		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
	}

	if (status & Y2_IS_PAR_MAC1) {
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
	}

	if (status & Y2_IS_PAR_RX1) {
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
		sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
	}

	if (status & Y2_IS_TCP_TXA1) {
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: TCP segmentation error\n",
			       dev->name);
		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
	}
}

	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
		u16 pci_err;

		pci_err = sky2_pci_read16(hw, PCI_STATUS);
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
			       pci_name(hw->pdev), pci_err);

		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
		sky2_pci_write16(hw, PCI_STATUS,
				      pci_err | PCI_STATUS_ERROR_BITS);
		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	}

		/* PCI-Express uncorrectable Error occurred */
		u32 pex_err;

		pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);

		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
			       pci_name(hw->pdev), pex_err);

		/* clear the interrupt */
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
		sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
				       0xffffffffUL);
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);


	}
}

/* This should never happen it is a fatal situation */
static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
				  const char *rxtx, u32 mask)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
	u32 imask;

	printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
	       dev ? dev->name : "<not registered>", rxtx);

	imask = sky2_read32(hw, B0_IMSK);
	imask &= ~mask;
	sky2_write32(hw, B0_IMSK, imask);

	if (dev) {
		spin_lock(&sky2->phy_lock);
		sky2_link_down(sky2);
		spin_unlock(&sky2->phy_lock);
	}
}

/* If idle then force a fake soft NAPI poll once a second
 * to work around cases where sharing an edge triggered interrupt.
 */
static void sky2_idle(unsigned long arg)
{
	struct sky2_hw *hw = (struct sky2_hw *) arg;
	struct net_device *dev = hw->dev[0];
	u32 status;

	if (__netif_rx_schedule_prep(dev))
		__netif_rx_schedule(dev);

	mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
}


static int sky2_poll(struct net_device *dev0, int *budget)
{
	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
	int work_limit = min(dev0->quota, *budget);
	int work_done = 0;
	u32 status = sky2_read32(hw, B0_Y2_SP_EISR);

	if (status & Y2_IS_HW_ERR)
		sky2_hw_intr(hw);

	/* Do NAPI for Rx and Tx status */
	if (status & Y2_IS_STAT_BMU) {
		hw->intr_mask &= ~Y2_IS_STAT_BMU;
		sky2_write32(hw, B0_IMSK, hw->intr_mask);

		if (likely(__netif_rx_schedule_prep(dev0))) {
			prefetch(&hw->st_le[hw->st_idx]);
			__netif_rx_schedule(dev0);
		}
	}

	if (status & Y2_IS_IRQ_PHY1)
		sky2_phy_intr(hw, 0);


	if (status & Y2_IS_IRQ_MAC2)
		sky2_mac_intr(hw, 1);

	if (status & Y2_IS_CHK_RX1)
		sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);

	if (status & Y2_IS_CHK_RX2)
		sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);

	if (status & Y2_IS_CHK_TXA1)
		sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);

	if (status & Y2_IS_CHK_TXA2)
		sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);

	if (status & Y2_IS_STAT_BMU)
		sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);

	work_done = sky2_status_intr(hw, work_limit);
	*budget -= work_done;
	dev0->quota -= work_done;

	if (work_done >= work_limit)
		return 1;

	netif_rx_complete(dev0);

	status = sky2_read32(hw, B0_Y2_SP_LISR);
	return 0;
}

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct sky2_hw *hw = dev_id;
	struct net_device *dev0 = hw->dev[0];
	u32 status;

	/* Reading this mask interrupts as side effect */
	status = sky2_read32(hw, B0_Y2_SP_ISRC2);
	if (status == 0 || status == ~0)
		return IRQ_NONE;

	prefetch(&hw->st_le[hw->st_idx]);
	if (likely(__netif_rx_schedule_prep(dev0)))
		__netif_rx_schedule(dev0);

	return IRQ_HANDLED;
}

}


static int __devinit sky2_reset(struct sky2_hw *hw)
{
	u32 ctst;
	u16 status;
	u8 t8, pmd_type;
	int i;

	ctst = sky2_read32(hw, B0_CTST);

	sky2_write8(hw, B0_CTST, CS_RST_CLR);

	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",

		return -EOPNOTSUPP;
	}

	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

	/* This rev is really old, and requires untested workarounds */
	if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
		printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
		       pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
		       hw->chip_id, hw->chip_rev);
		return -EOPNOTSUPP;
	}

	/* disable ASF */
	if (hw->chip_id <= CHIP_ID_YUKON_EC) {

	sky2_write8(hw, B0_CTST, CS_RST_CLR);

	/* clear PCI errors, if any */
	status = sky2_pci_read16(hw, PCI_STATUS);

	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
	sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);


	sky2_write8(hw, B0_CTST, CS_MRST_CLR);

	/* clear any PEX errors */
	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
		sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

				       0xffffffffUL);
		pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
	}

	pmd_type = sky2_read8(hw, B2_PMD_TYP);
	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
			++hw->ports;
	}
	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

	sky2_set_power_state(hw, PCI_D0);


	/* Set the list last index */
	sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);

	sky2_write16(hw, STAT_TX_IDX_TH, 10);
	sky2_write8(hw, STAT_FIFO_WM, 16);
		/* WA for dev. #4.3 */
		sky2_write16(hw, STAT_TX_IDX_TH, 0xfff);	/* Tx Threshold */

		/* set Status-FIFO watermark */
		sky2_write8(hw, STAT_FIFO_WM, 0x21);	/* WA for dev. #4.18 */

		/* set Status-FIFO ISR watermark */
		sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07);	/* WA for dev. #4.18 */
		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
	} else {
		sky2_write16(hw, STAT_TX_IDX_TH, 10);
		sky2_write8(hw, STAT_FIFO_WM, 16);

	/* set Status-FIFO ISR watermark */
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
		sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
	else
		sky2_write8(hw, STAT_FIFO_ISR_WM, 16);

	sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
	sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
	sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
	}

	/* enable status unit */
	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

	return 0;
}

static u32 sky2_supported_modes(const struct sky2_hw *hw)
{
	u32 modes;
	if (hw->copper) {

	{ "rx_unicast",    GM_RXF_UC_OK },
	{ "tx_mac_pause",  GM_TXF_MPAUSE },
	{ "rx_mac_pause",  GM_RXF_MPAUSE },
	{ "collisions",    GM_TXF_COL },
	{ "late_collision",GM_TXF_LAT_COL },
	{ "aborted", 	   GM_TXF_ABO_COL },
	{ "single_collisions", GM_TXF_SNG_COL },
	{ "multi_collisions", GM_TXF_MUL_COL },

	{ "rx_short",      GM_RXF_SHT },
	{ "rx_toolong",    GM_RXF_LNG_ERR },
	{ "rx_jabber",     GM_RXF_JAB_PKT },
	{ "rx_runt", 	   GM_RXE_FRAG },
	{ "rx_64_byte_packets", GM_RXF_64B },
	{ "rx_65_to_127_byte_packets", GM_RXF_127B },
	{ "rx_128_to_255_byte_packets", GM_RXF_255B },
	{ "rx_256_to_511_byte_packets", GM_RXF_511B },
	{ "rx_512_to_1023_byte_packets", GM_RXF_1023B },
	{ "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
	{ "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
	{ "rx_too_long",   GM_RXF_LNG_ERR },
	{ "rx_fifo_overflow", GM_RXE_FIFO_OV },
	{ "rx_jabber",     GM_RXF_JAB_PKT },
	{ "rx_fcs_error",   GM_RXF_FCS_ERR },

	{ "tx_64_byte_packets", GM_TXF_64B },
	{ "tx_65_to_127_byte_packets", GM_TXF_127B },
	{ "tx_128_to_255_byte_packets", GM_TXF_255B },
	{ "tx_256_to_511_byte_packets", GM_TXF_511B },
	{ "tx_512_to_1023_byte_packets", GM_TXF_1023B },
	{ "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
	{ "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
	{ "tx_fifo_underrun", GM_TXE_FIFO_UR },
};

static u32 sky2_get_rx_csum(struct net_device *dev)

	sky2->net_stats.rx_bytes = data[1];
	sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
	sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
	sky2->net_stats.multicast = data[3] + data[5];
	sky2->net_stats.collisions = data[10];
	sky2->net_stats.tx_aborted_errors = data[12];


static int sky2_set_mac_address(struct net_device *dev, void *p)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	const struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
	memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
		    dev->dev_addr, ETH_ALEN);
	memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
		    dev->dev_addr, ETH_ALEN);

	/* virtual address for data */
	gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

	/* physical address: used for pause frames */
	gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);

	return 0;
}

		ms = data * 1000;

	/* save initial values */
	spin_lock_bh(&sky2->phy_lock);
	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		sky2_led(hw, port, onoff);
		onoff = !onoff;

		spin_unlock_bh(&sky2->phy_lock);
		interrupted = msleep_interruptible(250);
		spin_lock_bh(&sky2->phy_lock);

		ms -= 250;
	}

		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
	}
	spin_unlock_bh(&sky2->phy_lock);

	return 0;
}

	return err;
}

#ifdef CONFIG_PM
static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	wol->supported = WAKE_MAGIC;
	wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
}

static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
		return -EOPNOTSUPP;

	sky2->wol = wol->wolopts == WAKE_MAGIC;

	if (sky2->wol) {
		memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

		sky2_write16(hw, WOL_CTRL_STAT,
			     WOL_CTL_ENA_PME_ON_MAGIC_PKT |
			     WOL_CTL_ENA_MAGIC_PKT_UNIT);
	} else
		sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

	return 0;
}
#endif

static int sky2_get_coalesce(struct net_device *dev,
			     struct ethtool_coalesce *ecmd)
{

{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
	const u32 tmax = 5000;

	if (ecmd->tx_coalesce_usecs != 0 &&
	    (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
		return -EINVAL;

	if (ecmd->tx_coalesce_usecs > tmax ||
	    ecmd->rx_coalesce_usecs > tmax ||
	    ecmd->rx_coalesce_usecs_irq > tmax)
		return -EINVAL;

	if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
	    (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
		return -EINVAL;
	if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
	if (ecmd->tx_max_coalesced_frames > 0xffff)
		return -EINVAL;
	if (ecmd->rx_max_coalesced_frames > 0xff)
		return -EINVAL;
	if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
		return -EINVAL;

	if (ecmd->tx_coalesce_usecs == 0)

	if (ecmd->rx_coalesce_usecs_irq == 0)
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_ISR_TIMER_INI,
			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
	}

	.set_ringparam = sky2_set_ringparam,
	.get_pauseparam = sky2_get_pauseparam,
	.set_pauseparam = sky2_set_pauseparam,
#ifdef CONFIG_PM
	.get_wol = sky2_get_wol,
	.set_wol = sky2_set_wol,
#endif
	.phys_id = sky2_phys_id,
	.get_stats_count = sky2_get_stats_count,
	.get_ethtool_stats = sky2_get_ethtool_stats,

	sky2->speed = -1;
	sky2->advertising = sky2_supported_modes(hw);

	/* Receive checksum disabled for Yukon XL
	 * because of observed problems with incorrect
	 * values when multiple packets are received in one interrupt
	 */
	sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

	spin_lock_init(&sky2->phy_lock);
	init_MUTEX(&sky2->phy_sema);
	sky2->tx_pending = TX_DEF_PENDING;
	sky2->rx_pending = RX_DEF_PENDING;
	sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);

	hw->dev[port] = dev;

	return dev;
}

static void __devinit sky2_show_addr(struct net_device *dev)
{
	const struct sky2_port *sky2 = netdev_priv(dev);


		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
}

/* Handle software interrupt used during MSI test */
static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
					    struct pt_regs *regs)
{
	struct sky2_hw *hw = dev_id;
	u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);

	if (status == 0)
		return IRQ_NONE;

	if (status & Y2_IS_IRQ_SW) {
		hw->msi_detected = 1;
		wake_up(&hw->msi_wait);
		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
	}
	sky2_write32(hw, B0_Y2_SP_ICR, 2);

	return IRQ_HANDLED;
}

/* Test interrupt path by forcing a a software IRQ */
static int __devinit sky2_test_msi(struct sky2_hw *hw)
{
	struct pci_dev *pdev = hw->pdev;
	int err;

	sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);

	err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
	if (err) {
		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
		       pci_name(pdev), pdev->irq);
		return err;
	}

	init_waitqueue_head (&hw->msi_wait);

	sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
	wmb();

	wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);

	if (!hw->msi_detected) {
		/* MSI test failed, go back to INTx mode */
		printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
		       "switching to INTx mode. Please report this failure to "
		       "the PCI maintainer and include system chipset information.\n",
		       pci_name(pdev));

		err = -EOPNOTSUPP;
		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
	}

	sky2_write32(hw, B0_IMSK, 0);

	free_irq(pdev->irq, hw);

	return err;
}

static int __devinit sky2_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{

		}
	}

#ifdef __BIG_ENDIAN
	/* byte swap descriptors in hardware */
	{
		u32 reg;

		pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
		reg |= PCI_REV_DESC;
		pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
	}
#endif

	err = -ENOMEM;
	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
	if (!hw) {
		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
		       pci_name(pdev));
		goto err_out_free_regions;
	}

	memset(hw, 0, sizeof(*hw));
	hw->pdev = pdev;

	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);

	}
	hw->pm_cap = pm_cap;

#ifdef __BIG_ENDIAN
	/* byte swap descriptors in hardware */
	{
		u32 reg;

		reg = sky2_pci_read32(hw, PCI_DEV_REG2);
		reg |= PCI_REV_DESC;
		sky2_pci_write32(hw, PCI_DEV_REG2, reg);
	}
#endif

	/* ring for status responses */
	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
					 &hw->st_dma);
	if (!hw->st_le)
		goto err_out_iounmap;

	err = sky2_reset(hw);
	if (err)
		goto err_out_iounmap;

		}
	}

	if (!disable_msi && pci_enable_msi(pdev) == 0) {
		err = sky2_test_msi(hw);
		if (err == -EOPNOTSUPP)
 			pci_disable_msi(pdev);
		else if (err)
			goto err_out_unregister;
 	}

	err = request_irq(pdev->irq,  sky2_intr, SA_SHIRQ, DRV_NAME, hw);
	if (err) {
		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
		       pci_name(pdev), pdev->irq);
		goto err_out_unregister;
	}

	sky2_write32(hw, B0_IMSK, Y2_IS_BASE);

	setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
	if (idle_timeout > 0)
		mod_timer(&hw->idle_timer,
			  jiffies + msecs_to_jiffies(idle_timeout));

	pci_set_drvdata(pdev, hw);

	return 0;

err_out_unregister:
	pci_disable_msi(pdev);
	if (dev1) {
		unregister_netdev(dev1);
		free_netdev(dev1);

	if (!hw)
		return;

	del_timer_sync(&hw->idle_timer);

	sky2_write32(hw, B0_IMSK, 0);
	synchronize_irq(hw->pdev->irq);

	dev0 = hw->dev[0];
	dev1 = hw->dev[1];
	if (dev1)
		unregister_netdev(dev1);
	unregister_netdev(dev0);

	sky2_write32(hw, B0_IMSK, 0);
	sky2_set_power_state(hw, PCI_D3hot);
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
	sky2_write8(hw, B0_CTST, CS_RST_SET);
	sky2_read8(hw, B0_CTST);

	free_irq(pdev->irq, hw);
	pci_disable_msi(pdev);
	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
	pci_release_regions(pdev);
	pci_disable_device(pdev);

static int sky2_resume(struct pci_dev *pdev)
{
	struct sky2_hw *hw = pci_get_drvdata(pdev);
	int i, err;

	pci_restore_state(pdev);
	pci_enable_wake(pdev, PCI_D0, 0);
	err = sky2_set_power_state(hw, PCI_D0);
	if (err)
		goto out;

	err = sky2_reset(hw);
	if (err)
		goto out;

	for (i = 0; i < 2; i++) {
		struct net_device *dev = hw->dev[i];
		if (dev && netif_running(dev)) {
			netif_device_attach(dev);
			err = sky2_up(dev);
			if (err) {
				printk(KERN_ERR PFX "%s: could not up: %d\n",
				       dev->name, err);
				dev_close(dev);
				break;
			}
		}
	}
out:
	return err;
}
#endif





#define _SKY2_H

/* PCI config registers */
enum {
	PCI_DEV_REG1	= 0x40,
	PCI_DEV_REG2	= 0x44,
	PCI_DEV_STATUS  = 0x7c,
	PCI_DEV_REG3	= 0x80,
	PCI_DEV_REG4	= 0x84,
	PCI_DEV_REG5    = 0x88,
};

enum {
	PEX_DEV_CAP	= 0xe4,
	PEX_DEV_CTRL	= 0xe8,
	PEX_DEV_STA	= 0xea,
	PEX_LNK_STAT	= 0xf2,
	PEX_UNC_ERR_STAT= 0x104,
};

/* Yukon-2 */
enum pci_dev_reg_1 {

	PCI_USEDATA64	= 1<<0,		/* Use 64Bit Data bus ext */
};

/*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
enum pci_dev_reg_4 {
					/* (Link Training & Status State Machine) */
	P_TIMER_VALUE_MSK	= 0xffL<<16,	/* Bit 23..16:	Timer Value Mask */
					/* (Active State Power Management) */
	P_FORCE_ASPM_REQUEST	= 1<<15, /* Force ASPM Request (A1 only) */
	P_ASPM_GPHY_LINK_DOWN	= 1<<14, /* GPHY Link Down (A1 only) */
	P_ASPM_INT_FIFO_EMPTY	= 1<<13, /* Internal FIFO Empty (A1 only) */
	P_ASPM_CLKRUN_REQUEST	= 1<<12, /* CLKRUN Request (A1 only) */

	P_ASPM_FORCE_CLKREQ_ENA	= 1<<4,	/* Force CLKREQ Enable (A1b only) */
	P_ASPM_CLKREQ_PAD_CTL	= 1<<3,	/* CLKREQ PAD Control (A1 only) */
	P_ASPM_A1_MODE_SELECT	= 1<<2,	/* A1 Mode Select (A1 only) */
	P_CLK_GATE_PEX_UNIT_ENA	= 1<<1,	/* Enable Gate PEX Unit Clock */
	P_CLK_GATE_ROOT_COR_ENA	= 1<<0,	/* Enable Gate Root Core Clock */
	P_ASPM_CONTROL_MSK	= P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
				  | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
};


#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
			       PCI_STATUS_SIG_SYSTEM_ERROR | \

	Y2_IS_CHK_TXS1	= 1<<1,		/* Descriptor error TXS 1 */
	Y2_IS_CHK_TXA1	= 1<<0,		/* Descriptor error TXA 1 */

	Y2_IS_BASE	= Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
	Y2_IS_PORT_1	= Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
		          | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
	Y2_IS_PORT_2	= Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
			  | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
	Y2_IS_PORT_2	= Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
			  Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
};

/*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */

	CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
	CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
	CHIP_REV_YU_EC_A3    = 2,  /* Chip Rev. for Yukon-EC A3 */

	CHIP_REV_YU_EC_U_A0  = 0,
	CHIP_REV_YU_EC_U_A1  = 1,
};

/*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */

};
#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))

/*	Q_F				32 bit	Flag Register */
enum {
	F_ALM_FULL	= 1<<27, /* Rx FIFO: almost full */
	F_EMPTY		= 1<<27, /* Tx FIFO: empty flag */
	F_FIFO_EOF	= 1<<26, /* Tag (EOF Flag) bit in FIFO */
	F_WM_REACHED	= 1<<25, /* Watermark reached */
	F_M_RX_RAM_DIS	= 1<<24, /* MAC Rx RAM Read Port disable */
	F_FIFO_LEVEL	= 0x1fL<<16, /* Bit 23..16:	# of Qwords in FIFO */
	F_WATER_MARK	= 0x0007ffL, /* Bit 10.. 0:	Watermark */
};

/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
enum {

	PHY_BCOM_ID1_C0	= 0x6044,
	PHY_BCOM_ID1_C5	= 0x6047,

	PHY_MARV_ID1_B0	= 0x0C23, /* Yukon 	(PHY 88E1011) */
	PHY_MARV_ID1_B2	= 0x0C25, /* Yukon-Plus (PHY 88E1011) */
	PHY_MARV_ID1_C2	= 0x0CC2, /* Yukon-EC	(PHY 88E1111) */
	PHY_MARV_ID1_Y2	= 0x0C91, /* Yukon-2	(PHY 88E1112) */
	PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE   (PHY 88E3082 Rev.A1) */
	PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
};

/* Advertisement register bits */

	GM_SMI_CTRL	= 0x0080,	/* 16 bit r/w	SMI Control Register */
	GM_SMI_DATA	= 0x0084,	/* 16 bit r/w	SMI Data Register */
	GM_PHY_ADDR	= 0x0088,	/* 16 bit r/w	GPHY Address Register */
/* MIB Counters */
	GM_MIB_CNT_BASE	= 0x0100,	/* Base Address of MIB Counters */
	GM_MIB_CNT_END	= 0x025C,	/* Last MIB counter */
};

/* MIB Counters */
#define GM_MIB_CNT_BASE	0x0100		/* Base Address of MIB Counters */
#define GM_MIB_CNT_SIZE	44		/* Number of MIB Counters */

/*
 * MIB Counters base address definitions (low word) -
 * use offset 4 for access to high word	(32 bit r/o)
 */
enum {
	GM_RXF_UC_OK    = GM_MIB_CNT_BASE + 0,	/* Unicast Frames Received OK */
	GM_RXF_BC_OK	= GM_MIB_CNT_BASE + 8,	/* Broadcast Frames Received OK */
	GM_RXF_MPAUSE	= GM_MIB_CNT_BASE + 16,	/* Pause MAC Ctrl Frames Received */
	GM_RXF_MC_OK	= GM_MIB_CNT_BASE + 24,	/* Multicast Frames Received OK */
	GM_RXF_FCS_ERR	= GM_MIB_CNT_BASE + 32,	/* Rx Frame Check Seq. Error */

	GM_RXO_OK_LO	= GM_MIB_CNT_BASE + 48,	/* Octets Received OK Low */
	GM_RXO_OK_HI	= GM_MIB_CNT_BASE + 56,	/* Octets Received OK High */
	GM_RXO_ERR_LO	= GM_MIB_CNT_BASE + 64,	/* Octets Received Invalid Low */

	GM_RXF_SHT	= GM_MIB_CNT_BASE + 80,	/* Frames <64 Byte Received OK */
	GM_RXE_FRAG	= GM_MIB_CNT_BASE + 88,	/* Frames <64 Byte Received with FCS Err */
	GM_RXF_64B	= GM_MIB_CNT_BASE + 96,	/* 64 Byte Rx Frame */
	GM_RXF_127B	= GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
	GM_RXF_255B	= GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
	GM_RXF_511B	= GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
	GM_RXF_1023B	= GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
	GM_RXF_1518B	= GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
	GM_RXF_MAX_SZ	= GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
	GM_RXF_LNG_ERR	= GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
	GM_RXF_JAB_PKT	= GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */

	GM_RXE_FIFO_OV	= GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
	GM_TXF_UC_OK	= GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
	GM_TXF_BC_OK	= GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
	GM_TXF_MPAUSE	= GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
	GM_TXF_MC_OK	= GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
	GM_TXO_OK_LO	= GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
	GM_TXO_OK_HI	= GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
	GM_TXF_64B	= GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
	GM_TXF_127B	= GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
	GM_TXF_255B	= GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
	GM_TXF_511B	= GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
	GM_TXF_1023B	= GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
	GM_TXF_1518B	= GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
	GM_TXF_MAX_SZ	= GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */

	GM_TXF_COL	= GM_MIB_CNT_BASE + 304,/* Tx Collision */
	GM_TXF_LAT_COL	= GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
	GM_TXF_ABO_COL	= GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
	GM_TXF_MUL_COL	= GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
	GM_TXF_SNG_COL	= GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
	GM_TXE_FIFO_UR	= GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
	GM_TXE_FIFO_UR	= GM_MIB_CNT_BASE + 344,	/* Tx FIFO Underrun Event */
};

/* GMAC Bit Definitions */

	__le16	length;
	u8	ctrl;
	u8	opcode;
} __attribute((packed));

struct sky2_status_le {
	__le32	status;	/* also checksum */

struct ring_info {
	struct sk_buff	*skb;
	dma_addr_t	mapaddr;
	unsigned	idx;
};

struct sky2_port {

	struct net_device    *netdev;
	unsigned	     port;
	u32		     msg_enable;
	spinlock_t	     phy_lock;

	spinlock_t	     tx_lock  ____cacheline_aligned_in_smp;
	struct tx_ring_info  *tx_ring;

	u16		     tx_prod;		/* next le to use */
	u32		     tx_addr64;
	u16		     tx_pending;
	u16		     tx_last_put;
	u16		     tx_last_mss;

	struct ring_info     *rx_ring ____cacheline_aligned_in_smp;

	u16		     rx_next;		/* next re to check */
	u16		     rx_put;		/* next le index to use */
	u16		     rx_pending;
	u16		     rx_last_put;
	u16		     rx_bufsize;
#ifdef SKY2_VLAN_TAG_USED
	u16		     rx_tag;

	u8		     rx_pause;
	u8		     tx_pause;
	u8		     rx_csum;
	u8		     wol;

	struct net_device_stats net_stats;

	struct work_struct   phy_task;
	struct semaphore     phy_sema;
};

struct sky2_hw {
	void __iomem  	     *regs;
	struct pci_dev	     *pdev;
	u32		     intr_mask;
	struct net_device    *dev[2];

	int		     pm_cap;

	struct sky2_status_le *st_le;
	u32		     st_idx;
	dma_addr_t   	     st_dma;

	struct timer_list    idle_timer;
	int		     msi_detected;
	wait_queue_head_t    msi_wait;
};

/* Register accessor for memory mapped device */

	return readb(hw->regs + reg);
}

/* This should probably go away, bus based tweeks suck */
static inline int is_pciex(const struct sky2_hw *hw)
{
	u32 status;
	pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
	return (status & PCI_OS_PCI_X) == 0;
}

static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
{
	writel(val, hw->regs + reg);

	gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
	gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
}

/* PCI config space access */
static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
{
	return sky2_read32(hw, Y2_CFG_SPC + reg);
}

static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
{
	return sky2_read16(hw, Y2_CFG_SPC + reg);
}

static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
{
	sky2_write32(hw, Y2_CFG_SPC + reg, val);
}

static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
{
	sky2_write16(hw, Y2_CFG_SPC + reg, val);
}
#endif

Return to bug 132056

Lines 5-18 Link Here

(-)linux-2.6.15/drivers/net/sky2.h (-69 / +121 lines)
5	#define _SKY2_H	5	#define _SKY2_H
6		6
7	/* PCI config registers */	7	/* PCI config registers */
8	#define PCI_DEV_REG1 0x40	8	enum {
9	#define PCI_DEV_REG2 0x44	9	PCI_DEV_REG1 = 0x40,
10	#define PCI_DEV_STATUS 0x7c	10	PCI_DEV_REG2 = 0x44,
11	#define PCI_OS_PCI_X (1<<26)	11	PCI_DEV_STATUS = 0x7c,
12		12	PCI_DEV_REG3 = 0x80,
13	#define PEX_LNK_STAT 0xf2	13	PCI_DEV_REG4 = 0x84,
14	#define PEX_UNC_ERR_STAT 0x104	14	PCI_DEV_REG5 = 0x88,
15	#define PEX_DEV_CTRL 0xe8	15	};
		16
		17	enum {
		18	PEX_DEV_CAP = 0xe4,
		19	PEX_DEV_CTRL = 0xe8,
		20	PEX_DEV_STA = 0xea,
		21	PEX_LNK_STAT = 0xf2,
		22	PEX_UNC_ERR_STAT= 0x104,
		23	};
16		24
17	/* Yukon-2 */	25	/* Yukon-2 */
18	enum pci_dev_reg_1 {	26	enum pci_dev_reg_1 {
Lines 37-42 enum pci_dev_reg_2 { Link Here
37	PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */	45	PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
38	};	46	};
39		47
		48	/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
		49	enum pci_dev_reg_4 {
		50	/* (Link Training & Status State Machine) */
		51	P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
		52	/* (Active State Power Management) */
		53	P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
		54	P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
		55	P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
		56	P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
		57
		58	P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
		59	P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
		60	P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
		61	P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
		62	P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
		63	P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST \| P_ASPM_GPHY_LINK_DOWN
		64	\| P_ASPM_CLKRUN_REQUEST \| P_ASPM_INT_FIFO_EMPTY,
		65	};
		66
40		67
41	#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY \| \	68	#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY \| \
42	PCI_STATUS_SIG_SYSTEM_ERROR \| \	69	PCI_STATUS_SIG_SYSTEM_ERROR \| \
Lines 251-263 enum { Link Here
251	Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */	278	Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
252	Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */	279	Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
253		280
254	Y2_IS_BASE = Y2_IS_HW_ERR \| Y2_IS_STAT_BMU \|	281	Y2_IS_BASE = Y2_IS_HW_ERR \| Y2_IS_STAT_BMU,
255	Y2_IS_POLL_CHK \| Y2_IS_TWSI_RDY \|	282	Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 \| Y2_IS_IRQ_MAC1
256	Y2_IS_IRQ_SW \| Y2_IS_TIMINT,	283	\| Y2_IS_CHK_TXA1 \| Y2_IS_CHK_RX1,
257	Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 \| Y2_IS_IRQ_MAC1 \|	284	Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 \| Y2_IS_IRQ_MAC2
258	Y2_IS_CHK_RX1 \| Y2_IS_CHK_TXA1 \| Y2_IS_CHK_TXS1,	285	\| Y2_IS_CHK_TXA2 \| Y2_IS_CHK_RX2,
259	Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 \| Y2_IS_IRQ_MAC2 \|
260	Y2_IS_CHK_RX2 \| Y2_IS_CHK_TXA2 \| Y2_IS_CHK_TXS2,
261	};	286	};
262		287
263	/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */	288	/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
Lines 353-358 enum { Link Here
353	CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */	378	CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
354	CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */	379	CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
355	CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */	380	CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
		381
		382	CHIP_REV_YU_EC_U_A0 = 0,
		383	CHIP_REV_YU_EC_U_A1 = 1,
356	};	384	};
357		385
358	/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */	386	/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
Lines 507-512 enum { Link Here
507	};	535	};
508	#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))	536	#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
509		537
		538	/* Q_F 32 bit Flag Register */
		539	enum {
		540	F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
		541	F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
		542	F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
		543	F_WM_REACHED = 1<<25, /* Watermark reached */
		544	F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
		545	F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
		546	F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
		547	};
510		548
511	/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/	549	/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
512	enum {	550	enum {
Lines 909-918 enum { Link Here
909	PHY_BCOM_ID1_C0 = 0x6044,	947	PHY_BCOM_ID1_C0 = 0x6044,
910	PHY_BCOM_ID1_C5 = 0x6047,	948	PHY_BCOM_ID1_C5 = 0x6047,
911		949
912	PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */	950	PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
913	PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */	951	PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
914	PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */	952	PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
915	PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */	953	PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
		954	PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
		955	PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
916	};	956	};
917		957
918	/* Advertisement register bits */	958	/* Advertisement register bits */
Lines 1336-1358 enum { Link Here
1336	GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */	1376	GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1337	GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */	1377	GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1338	GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */	1378	GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
		1379	/* MIB Counters */
		1380	GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
		1381	GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1339	};	1382	};
1340		1383
1341	/* MIB Counters */
1342	#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1343	#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1344		1384
1345	/*	1385	/*
1346	* MIB Counters base address definitions (low word) -	1386	* MIB Counters base address definitions (low word) -
1347	* use offset 4 for access to high word (32 bit r/o)	1387	* use offset 4 for access to high word (32 bit r/o)
1348	*/	1388	*/
1349	enum {	1389	enum {
1350	GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */	1390	GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1351	GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */	1391	GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1352	GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */	1392	GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1353	GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */	1393	GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1354	GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */	1394	GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1355	/* GM_MIB_CNT_BASE + 40: reserved */	1395
1356	GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */	1396	GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1357	GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */	1397	GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1358	GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */	1398	GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
Lines 1360-1396 enum { Link Here
1360	GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */	1400	GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1361	GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */	1401	GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1362	GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */	1402	GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1363	GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */	1403	GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1364	GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */	1404	GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1365	GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */	1405	GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1366	GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */	1406	GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1367	GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */	1407	GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1368	GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */	1408	GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1369	GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */	1409	GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1370	GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */	1410	GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1371	/* GM_MIB_CNT_BASE + 168: reserved */	1411
1372	GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */	1412	GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1373	/* GM_MIB_CNT_BASE + 184: reserved */	1413	GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1374	GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */	1414	GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1375	GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */	1415	GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1376	GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */	1416	GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1377	GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */	1417	GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1378	GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */	1418	GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1379	GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */	1419	GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1380	GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */	1420	GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1381	GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */	1421	GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1382	GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */	1422	GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1383	GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */	1423	GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1384	GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */	1424	GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1385	GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */	1425	GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1386	GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */	1426
1387		1427	GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1388	GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */	1428	GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1389	GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */	1429	GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1390	GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */	1430	GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1391	GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */	1431	GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1392	GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */	1432	GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1393	GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1394	};	1433	};
1395		1434
1396	/* GMAC Bit Definitions */	1435	/* GMAC Bit Definitions */
Lines 1768-1774 struct sky2_rx_le { Link Here
1768	__le16 length;	1807	__le16 length;
1769	u8 ctrl;	1808	u8 ctrl;
1770	u8 opcode;	1809	u8 opcode;
1771	} __attribute((packed));;	1810	} __attribute((packed));
1772		1811
1773	struct sky2_status_le {	1812	struct sky2_status_le {
1774	__le32 status; /* also checksum */	1813	__le32 status; /* also checksum */
Lines 1786-1791 struct tx_ring_info { Link Here
1786	struct ring_info {	1825	struct ring_info {
1787	struct sk_buff *skb;	1826	struct sk_buff *skb;
1788	dma_addr_t mapaddr;	1827	dma_addr_t mapaddr;
		1828	unsigned idx;
1789	};	1829	};
1790		1830
1791	struct sky2_port {	1831	struct sky2_port {
Lines 1793-1798 struct sky2_port { Link Here
1793	struct net_device *netdev;	1833	struct net_device *netdev;
1794	unsigned port;	1834	unsigned port;
1795	u32 msg_enable;	1835	u32 msg_enable;
		1836	spinlock_t phy_lock;
1796		1837
1797	spinlock_t tx_lock ____cacheline_aligned_in_smp;	1838	spinlock_t tx_lock ____cacheline_aligned_in_smp;
1798	struct tx_ring_info *tx_ring;	1839	struct tx_ring_info *tx_ring;
Lines 1801-1807 struct sky2_port { Link Here
1801	u16 tx_prod; /* next le to use */	1842	u16 tx_prod; /* next le to use */
1802	u32 tx_addr64;	1843	u32 tx_addr64;
1803	u16 tx_pending;	1844	u16 tx_pending;
1804	u16 tx_last_put;
1805	u16 tx_last_mss;	1845	u16 tx_last_mss;
1806		1846
1807	struct ring_info *rx_ring ____cacheline_aligned_in_smp;	1847	struct ring_info *rx_ring ____cacheline_aligned_in_smp;
Lines 1810-1816 struct sky2_port { Link Here
1810	u16 rx_next; /* next re to check */	1850	u16 rx_next; /* next re to check */
1811	u16 rx_put; /* next le index to use */	1851	u16 rx_put; /* next le index to use */
1812	u16 rx_pending;	1852	u16 rx_pending;
1813	u16 rx_last_put;
1814	u16 rx_bufsize;	1853	u16 rx_bufsize;
1815	#ifdef SKY2_VLAN_TAG_USED	1854	#ifdef SKY2_VLAN_TAG_USED
1816	u16 rx_tag;	1855	u16 rx_tag;
Lines 1826-1843 struct sky2_port { Link Here
1826	u8 rx_pause;	1865	u8 rx_pause;
1827	u8 tx_pause;	1866	u8 tx_pause;
1828	u8 rx_csum;	1867	u8 rx_csum;
1829	u8 wol;
1830		1868
1831	struct net_device_stats net_stats;	1869	struct net_device_stats net_stats;
1832		1870
1833	struct work_struct phy_task;
1834	struct semaphore phy_sema;
1835	};	1871	};
1836		1872
1837	struct sky2_hw {	1873	struct sky2_hw {
1838	void __iomem *regs;	1874	void __iomem *regs;
1839	struct pci_dev *pdev;	1875	struct pci_dev *pdev;
1840	u32 intr_mask;
1841	struct net_device *dev[2];	1876	struct net_device *dev[2];
1842		1877
1843	int pm_cap;	1878	int pm_cap;
Lines 1849-1854 struct sky2_hw { Link Here
1849	struct sky2_status_le *st_le;	1884	struct sky2_status_le *st_le;
1850	u32 st_idx;	1885	u32 st_idx;
1851	dma_addr_t st_dma;	1886	dma_addr_t st_dma;
		1887
		1888	struct timer_list idle_timer;
		1889	int msi_detected;
		1890	wait_queue_head_t msi_wait;
1852	};	1891	};
1853		1892
1854	/* Register accessor for memory mapped device */	1893	/* Register accessor for memory mapped device */
Lines 1867-1880 static inline u8 sky2_read8(const struct Link Here
1867	return readb(hw->regs + reg);	1906	return readb(hw->regs + reg);
1868	}	1907	}
1869		1908
1870	/* This should probably go away, bus based tweeks suck */
1871	static inline int is_pciex(const struct sky2_hw *hw)
1872	{
1873	u32 status;
1874	pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
1875	return (status & PCI_OS_PCI_X) == 0;
1876	}
1877
1878	static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)	1909	static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1879	{	1910	{
1880	writel(val, hw->regs + reg);	1911	writel(val, hw->regs + reg);
Lines 1919-1922 static inline void gma_set_addr(struct s Link Here
1919	gma_write16(hw, port, reg+4,(u16) addr[2] \| ((u16) addr[3] << 8));	1950	gma_write16(hw, port, reg+4,(u16) addr[2] \| ((u16) addr[3] << 8));
1920	gma_write16(hw, port, reg+8,(u16) addr[4] \| ((u16) addr[5] << 8));	1951	gma_write16(hw, port, reg+8,(u16) addr[4] \| ((u16) addr[5] << 8));
1921	}	1952	}
		1953
		1954	/* PCI config space access */
		1955	static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
		1956	{
		1957	return sky2_read32(hw, Y2_CFG_SPC + reg);
		1958	}
		1959
		1960	static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
		1961	{
		1962	return sky2_read16(hw, Y2_CFG_SPC + reg);
		1963	}
		1964
		1965	static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
		1966	{
		1967	sky2_write32(hw, Y2_CFG_SPC + reg, val);
		1968	}
		1969
		1970	static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
		1971	{
		1972	sky2_write16(hw, Y2_CFG_SPC + reg, val);
		1973	}
1922	#endif	1974	#endif