Attachment #548572 for bug #664868

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  InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)
      : InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}

  bool isLegal(const MachineInstr *MI,
               const TargetInstrInfo *TII) const override {
    if (!InstrConverterBase::isLegal(MI, TII))
      return false;

    // Don't allow copies to/flow GR8/GR16 physical registers.
    // FIXME: Is there some better way to support this?
    unsigned DstReg = MI->getOperand(0).getReg();
    if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
        (X86::GR8RegClass.contains(DstReg) ||
         X86::GR16RegClass.contains(DstReg)))
      return false;
    unsigned SrcReg = MI->getOperand(1).getReg();
    if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
        (X86::GR8RegClass.contains(SrcReg) ||
         X86::GR16RegClass.contains(SrcReg)))
      return false;

    return true;
  }

  double getExtraCost(const MachineInstr *MI,
                      MachineRegisterInfo *MRI) const override {
    assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");




; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s

@b = local_unnamed_addr global i32 0, align 4
@c = local_unnamed_addr global i32 0, align 4
@d = local_unnamed_addr global float 0.000000e+00, align 4

define float @_Z3fn2v() {
; CHECK-LABEL: _Z3fn2v:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq _Z1av
; CHECK-NEXT:    # kill: def $al killed $al def $eax
; CHECK-NEXT:    kmovd %eax, %k1
; CHECK-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT:    vmovss %xmm0, %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT:    cmpl $0, {{.*}}(%rip)
; CHECK-NEXT:    je .LBB0_2
; CHECK-NEXT:  # %bb.1: # %if.then
; CHECK-NEXT:    vcvtsi2ssl {{.*}}(%rip), %xmm1, %xmm1
; CHECK-NEXT:    kmovd %eax, %k1
; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT:    vmovss %xmm2, %xmm0, %xmm1 {%k1}
; CHECK-NEXT:    vmovss %xmm1, {{.*}}(%rip)
; CHECK-NEXT:  .LBB0_2: # %if.end
; CHECK-NEXT:    popq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %call = tail call zeroext i1 @_Z1av()
  %cond = select i1 %call, float 7.500000e-01, float 0.000000e+00
  %0 = load i32, i32* @c, align 4
  %tobool2 = icmp eq i32 %0, 0
  br i1 %tobool2, label %if.end, label %if.then

if.then:                                          ; preds = %entry
  %1 = load i32, i32* @b, align 4
  %2 = sitofp i32 %1 to float
  %conv5 = select i1 %call, float 0.000000e+00, float %2
  store float %conv5, float* @d, align 4
  br label %if.end

if.end:                                           ; preds = %entry, %if.then
  ret float %cond
}

declare zeroext i1 @_Z1av()

Return to bug 664868

Lines 217-222 public: Link Here

(-)a/lib/Target/X86/X86DomainReassignment.cpp (+21 lines)
217	InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)	217	InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)
218	: InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}	218	: InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}
219		219
		220	bool isLegal(const MachineInstr *MI,
		221	const TargetInstrInfo *TII) const override {
		222	if (!InstrConverterBase::isLegal(MI, TII))
		223	return false;
		224
		225	// Don't allow copies to/flow GR8/GR16 physical registers.
		226	// FIXME: Is there some better way to support this?
		227	unsigned DstReg = MI->getOperand(0).getReg();
		228	if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
		229	(X86::GR8RegClass.contains(DstReg) \|\|
		230	X86::GR16RegClass.contains(DstReg)))
		231	return false;
		232	unsigned SrcReg = MI->getOperand(1).getReg();
		233	if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
		234	(X86::GR8RegClass.contains(SrcReg) \|\|
		235	X86::GR16RegClass.contains(SrcReg)))
		236	return false;
		237
		238	return true;
		239	}
		240
220	double getExtraCost(const MachineInstr *MI,	241	double getExtraCost(const MachineInstr *MI,
221	MachineRegisterInfo *MRI) const override {	242	MachineRegisterInfo *MRI) const override {
222	assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");	243	assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");

Line 0 Link Here

(-)a/test/CodeGen/X86/pr38803.ll (-1 / +48 lines)
0	-	1	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
		2	; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown \| FileCheck %s
		3
		4	@b = local_unnamed_addr global i32 0, align 4
		5	@c = local_unnamed_addr global i32 0, align 4
		6	@d = local_unnamed_addr global float 0.000000e+00, align 4
		7
		8	define float @_Z3fn2v() {
		9	; CHECK-LABEL: _Z3fn2v:
		10	; CHECK: # %bb.0: # %entry
		11	; CHECK-NEXT: pushq %rax
		12	; CHECK-NEXT: .cfi_def_cfa_offset 16
		13	; CHECK-NEXT: callq _Z1av
		14	; CHECK-NEXT: # kill: def $al killed $al def $eax
		15	; CHECK-NEXT: kmovd %eax, %k1
		16	; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
		17	; CHECK-NEXT: vmovss %xmm0, %xmm0, %xmm0 {%k1} {z}
		18	; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
		19	; CHECK-NEXT: je .LBB0_2
		20	; CHECK-NEXT: # %bb.1: # %if.then
		21	; CHECK-NEXT: vcvtsi2ssl {{.*}}(%rip), %xmm1, %xmm1
		22	; CHECK-NEXT: kmovd %eax, %k1
		23	; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
		24	; CHECK-NEXT: vmovss %xmm2, %xmm0, %xmm1 {%k1}
		25	; CHECK-NEXT: vmovss %xmm1, {{.*}}(%rip)
		26	; CHECK-NEXT: .LBB0_2: # %if.end
		27	; CHECK-NEXT: popq %rax
		28	; CHECK-NEXT: .cfi_def_cfa_offset 8
		29	; CHECK-NEXT: retq
		30	entry:
		31	%call = tail call zeroext i1 @_Z1av()
		32	%cond = select i1 %call, float 7.500000e-01, float 0.000000e+00
		33	%0 = load i32, i32* @c, align 4
		34	%tobool2 = icmp eq i32 %0, 0
		35	br i1 %tobool2, label %if.end, label %if.then
		36
		37	if.then: ; preds = %entry
		38	%1 = load i32, i32* @b, align 4
		39	%2 = sitofp i32 %1 to float
		40	%conv5 = select i1 %call, float 0.000000e+00, float %2
		41	store float %conv5, float* @d, align 4
		42	br label %if.end
		43
		44	if.end: ; preds = %entry, %if.then
		45	ret float %cond
		46	}
		47
		48	declare zeroext i1 @_Z1av()