Attachment #341316 for bug #453294

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Lines 1-6 Link Here

(-)gcc/config/arm/arm-arches.def (-2 / +2 lines)
1	/* ARM CPU architectures.	1	/* ARM CPU architectures.
2	Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,	2	Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3	2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011	3	2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4	Free Software Foundation, Inc.	4	Free Software Foundation, Inc.
5		5
6	This file is part of GCC.	6	This file is part of GCC.
Lines 57-60 Link Here
57	ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC \| FL_FOR_ARCH7EM)	57	ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC \| FL_FOR_ARCH7EM)
58	ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED \| FL_CIRRUS \| FL_FOR_ARCH4)	58	ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED \| FL_CIRRUS \| FL_FOR_ARCH4)
59	ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT)	59	ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT)
60	ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT)	60	ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT \| FL_IWMMXT2)

Lines 685-690 Link Here

(-)gcc/config/arm/arm.c (-70 / +666 lines)
685	#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */	685	#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
686		686
687	#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */	687	#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
		688	#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
688		689
689	/* Flags that only effect tuning, not available instructions. */	690	/* Flags that only effect tuning, not available instructions. */
690	#define FL_TUNE (FL_WBUF \| FL_VFPV2 \| FL_STRONG \| FL_LDSCHED \	691	#define FL_TUNE (FL_WBUF \| FL_VFPV2 \| FL_STRONG \| FL_LDSCHED \
Lines 766-771 Link Here
766	/* Nonzero if this chip supports Intel Wireless MMX technology. */	767	/* Nonzero if this chip supports Intel Wireless MMX technology. */
767	int arm_arch_iwmmxt = 0;	768	int arm_arch_iwmmxt = 0;
768		769
		770	/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
		771	int arm_arch_iwmmxt2 = 0;
		772
769	/* Nonzero if this chip is an XScale. */	773	/* Nonzero if this chip is an XScale. */
770	int arm_arch_xscale = 0;	774	int arm_arch_xscale = 0;
771		775
Lines 1717-1722 Link Here
1717	arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;	1721	arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1718	arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;	1722	arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1719	arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;	1723	arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
		1724	arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0;
1720	arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;	1725	arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
1721	arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;	1726	arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
1722	arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;	1727	arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
Lines 1817-1830 Link Here
1817	}	1822	}
1818		1823
1819	/* FPA and iWMMXt are incompatible because the insn encodings overlap.	1824	/* FPA and iWMMXt are incompatible because the insn encodings overlap.
1820	VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon	1825	VFP and iWMMXt however can coexist. */
1821	will ever exist. GCC makes no attempt to support this combination. */	1826	if (TARGET_IWMMXT && TARGET_HARD_FLOAT && !TARGET_VFP)
1822	if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)	1827	error ("iWMMXt and non-VFP floating point unit are incompatible");
1823	sorry ("iWMMXt and hardware floating point");	1828
1824		1829	/* iWMMXt and NEON are incompatible. */
1825	/* ??? iWMMXt insn patterns need auditing for Thumb-2. */	1830	if (TARGET_IWMMXT && TARGET_NEON)
1826	if (TARGET_THUMB2 && TARGET_IWMMXT)	1831	error ("iWMMXt and NEON are incompatible");
1827	sorry ("Thumb-2 iWMMXt");	1832
		1833	/* iWMMXt unsupported under Thumb mode. */
		1834	if (TARGET_THUMB && TARGET_IWMMXT)
		1835	error ("iWMMXt unsupported under Thumb mode");
1828		1836
1829	/* __fp16 support currently assumes the core has ldrh. */	1837	/* __fp16 support currently assumes the core has ldrh. */
1830	if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)	1838	if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
Lines 19269-19276 Link Here
19269	FIXME? */	19277	FIXME? */
19270	enum arm_builtins	19278	enum arm_builtins
19271	{	19279	{
19272	ARM_BUILTIN_GETWCX,	19280	ARM_BUILTIN_GETWCGR0,
19273	ARM_BUILTIN_SETWCX,	19281	ARM_BUILTIN_GETWCGR1,
		19282	ARM_BUILTIN_GETWCGR2,
		19283	ARM_BUILTIN_GETWCGR3,
		19284
		19285	ARM_BUILTIN_SETWCGR0,
		19286	ARM_BUILTIN_SETWCGR1,
		19287	ARM_BUILTIN_SETWCGR2,
		19288	ARM_BUILTIN_SETWCGR3,
19274		19289
19275	ARM_BUILTIN_WZERO,	19290	ARM_BUILTIN_WZERO,
19276		19291
Lines 19293-19299 Link Here
19293	ARM_BUILTIN_WSADH,	19308	ARM_BUILTIN_WSADH,
19294	ARM_BUILTIN_WSADHZ,	19309	ARM_BUILTIN_WSADHZ,
19295		19310
19296	ARM_BUILTIN_WALIGN,	19311	ARM_BUILTIN_WALIGNI,
		19312	ARM_BUILTIN_WALIGNR0,
		19313	ARM_BUILTIN_WALIGNR1,
		19314	ARM_BUILTIN_WALIGNR2,
		19315	ARM_BUILTIN_WALIGNR3,
19297		19316
19298	ARM_BUILTIN_TMIA,	19317	ARM_BUILTIN_TMIA,
19299	ARM_BUILTIN_TMIAPH,	19318	ARM_BUILTIN_TMIAPH,
Lines 19429-19434 Link Here
19429	ARM_BUILTIN_WUNPCKELUH,	19448	ARM_BUILTIN_WUNPCKELUH,
19430	ARM_BUILTIN_WUNPCKELUW,	19449	ARM_BUILTIN_WUNPCKELUW,
19431		19450
		19451	ARM_BUILTIN_WABSB,
		19452	ARM_BUILTIN_WABSH,
		19453	ARM_BUILTIN_WABSW,
		19454
		19455	ARM_BUILTIN_WADDSUBHX,
		19456	ARM_BUILTIN_WSUBADDHX,
		19457
		19458	ARM_BUILTIN_WABSDIFFB,
		19459	ARM_BUILTIN_WABSDIFFH,
		19460	ARM_BUILTIN_WABSDIFFW,
		19461
		19462	ARM_BUILTIN_WADDCH,
		19463	ARM_BUILTIN_WADDCW,
		19464
		19465	ARM_BUILTIN_WAVG4,
		19466	ARM_BUILTIN_WAVG4R,
		19467
		19468	ARM_BUILTIN_WMADDSX,
		19469	ARM_BUILTIN_WMADDUX,
		19470
		19471	ARM_BUILTIN_WMADDSN,
		19472	ARM_BUILTIN_WMADDUN,
		19473
		19474	ARM_BUILTIN_WMULWSM,
		19475	ARM_BUILTIN_WMULWUM,
		19476
		19477	ARM_BUILTIN_WMULWSMR,
		19478	ARM_BUILTIN_WMULWUMR,
		19479
		19480	ARM_BUILTIN_WMULWL,
		19481
		19482	ARM_BUILTIN_WMULSMR,
		19483	ARM_BUILTIN_WMULUMR,
		19484
		19485	ARM_BUILTIN_WQMULM,
		19486	ARM_BUILTIN_WQMULMR,
		19487
		19488	ARM_BUILTIN_WQMULWM,
		19489	ARM_BUILTIN_WQMULWMR,
		19490
		19491	ARM_BUILTIN_WADDBHUSM,
		19492	ARM_BUILTIN_WADDBHUSL,
		19493
		19494	ARM_BUILTIN_WQMIABB,
		19495	ARM_BUILTIN_WQMIABT,
		19496	ARM_BUILTIN_WQMIATB,
		19497	ARM_BUILTIN_WQMIATT,
		19498
		19499	ARM_BUILTIN_WQMIABBN,
		19500	ARM_BUILTIN_WQMIABTN,
		19501	ARM_BUILTIN_WQMIATBN,
		19502	ARM_BUILTIN_WQMIATTN,
		19503
		19504	ARM_BUILTIN_WMIABB,
		19505	ARM_BUILTIN_WMIABT,
		19506	ARM_BUILTIN_WMIATB,
		19507	ARM_BUILTIN_WMIATT,
		19508
		19509	ARM_BUILTIN_WMIABBN,
		19510	ARM_BUILTIN_WMIABTN,
		19511	ARM_BUILTIN_WMIATBN,
		19512	ARM_BUILTIN_WMIATTN,
		19513
		19514	ARM_BUILTIN_WMIAWBB,
19515	ARM_BUILTIN_WMIAWBT,
19516	ARM_BUILTIN_WMIAWTB,
19517	ARM_BUILTIN_WMIAWTT,
19518
19519	ARM_BUILTIN_WMIAWBBN,
19520	ARM_BUILTIN_WMIAWBTN,
19521	ARM_BUILTIN_WMIAWTBN,
19522	ARM_BUILTIN_WMIAWTTN,
19523
19524	ARM_BUILTIN_WMERGE,
19525
19432	ARM_BUILTIN_THREAD_POINTER,	19526	ARM_BUILTIN_THREAD_POINTER,
19433		19527
19434	ARM_BUILTIN_NEON_BASE,	19528	ARM_BUILTIN_NEON_BASE,
Lines 19961-19966 Link Here
19961	{ FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \	20055	{ FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
19962	ARM_BUILTIN_##builtin, UNKNOWN, 0 },	20056	ARM_BUILTIN_##builtin, UNKNOWN, 0 },
19963		20057
		20058	#define IWMMXT2_BUILTIN(code, string, builtin) \
		20059	{ FL_IWMMXT2, CODE_FOR_##code, "__builtin_arm_" string, \
		20060	ARM_BUILTIN_##builtin, UNKNOWN, 0 },
		20061
19964	IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)	20062	IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
19965	IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)	20063	IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
19966	IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)	20064	IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
Lines 20017-20060 Link Here
20017	IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)	20115	IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
20018	IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)	20116	IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
20019	IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)	20117	IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
20020	IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)	20118	IWMMXT2_BUILTIN (iwmmxt_waddsubhx, "waddsubhx", WADDSUBHX)
20021	IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)	20119	IWMMXT2_BUILTIN (iwmmxt_wsubaddhx, "wsubaddhx", WSUBADDHX)
		20120	IWMMXT2_BUILTIN (iwmmxt_wabsdiffb, "wabsdiffb", WABSDIFFB)
		20121	IWMMXT2_BUILTIN (iwmmxt_wabsdiffh, "wabsdiffh", WABSDIFFH)
		20122	IWMMXT2_BUILTIN (iwmmxt_wabsdiffw, "wabsdiffw", WABSDIFFW)
		20123	IWMMXT2_BUILTIN (iwmmxt_avg4, "wavg4", WAVG4)
		20124	IWMMXT2_BUILTIN (iwmmxt_avg4r, "wavg4r", WAVG4R)
		20125	IWMMXT2_BUILTIN (iwmmxt_wmulwsm, "wmulwsm", WMULWSM)
		20126	IWMMXT2_BUILTIN (iwmmxt_wmulwum, "wmulwum", WMULWUM)
		20127	IWMMXT2_BUILTIN (iwmmxt_wmulwsmr, "wmulwsmr", WMULWSMR)
		20128	IWMMXT2_BUILTIN (iwmmxt_wmulwumr, "wmulwumr", WMULWUMR)
		20129	IWMMXT2_BUILTIN (iwmmxt_wmulwl, "wmulwl", WMULWL)
		20130	IWMMXT2_BUILTIN (iwmmxt_wmulsmr, "wmulsmr", WMULSMR)
		20131	IWMMXT2_BUILTIN (iwmmxt_wmulumr, "wmulumr", WMULUMR)
		20132	IWMMXT2_BUILTIN (iwmmxt_wqmulm, "wqmulm", WQMULM)
		20133	IWMMXT2_BUILTIN (iwmmxt_wqmulmr, "wqmulmr", WQMULMR)
		20134	IWMMXT2_BUILTIN (iwmmxt_wqmulwm, "wqmulwm", WQMULWM)
		20135	IWMMXT2_BUILTIN (iwmmxt_wqmulwmr, "wqmulwmr", WQMULWMR)
		20136	IWMMXT_BUILTIN (iwmmxt_walignr0, "walignr0", WALIGNR0)
		20137	IWMMXT_BUILTIN (iwmmxt_walignr1, "walignr1", WALIGNR1)
		20138	IWMMXT_BUILTIN (iwmmxt_walignr2, "walignr2", WALIGNR2)
		20139	IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3)
20022		20140
20023	#define IWMMXT_BUILTIN2(code, builtin) \	20141	#define IWMMXT_BUILTIN2(code, builtin) \
20024	{ FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },	20142	{ FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
20025		20143
		20144	#define IWMMXT2_BUILTIN2(code, builtin) \
		20145	{ FL_IWMMXT2, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
		20146
		20147	IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM)
		20148	IWMMXT2_BUILTIN2 (iwmmxt_waddbhusl, WADDBHUSL)
20026	IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)	20149	IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
20027	IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)	20150	IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
20028	IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)	20151	IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
20029	IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)	20152	IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
20030	IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)	20153	IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
20031	IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)	20154	IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
20032	IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)	20155	IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
20033	IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)	20156	IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
20034	IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
20035	IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
20036	IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
20037	IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
20038	IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
20039	IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
20040	IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
20041	IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
20042	IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
20043	IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
20044	IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
20045	IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
20046	IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
20047	IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
20048	IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
20049	IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
20050	IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
20051	IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
20052	IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
20053	IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
20054	IWMMXT_BUILTIN2 (rordi3_di, WRORD)
20055	IWMMXT_BUILTIN2 (rordi3, WRORDI)
20056	IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
20057	IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
20058	};	20157	};
20059		20158
20060	static const struct builtin_description bdesc_1arg[] =	20159	static const struct builtin_description bdesc_1arg[] =
Lines 20077-20082 Link Here
20077	IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)	20176	IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
20078	IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)	20177	IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
20079	IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)	20178	IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
		20179	IWMMXT2_BUILTIN (iwmmxt_wabsv8qi3, "wabsb", WABSB)
		20180	IWMMXT2_BUILTIN (iwmmxt_wabsv4hi3, "wabsh", WABSH)
		20181	IWMMXT2_BUILTIN (iwmmxt_wabsv2si3, "wabsw", WABSW)
		20182	IWMMXT_BUILTIN (tbcstv8qi, "tbcstb", TBCSTB)
		20183	IWMMXT_BUILTIN (tbcstv4hi, "tbcsth", TBCSTH)
		20184	IWMMXT_BUILTIN (tbcstv2si, "tbcstw", TBCSTW)
20080	};	20185	};
20081		20186
20082	/* Set up all the iWMMXt builtins. This is not called if	20187	/* Set up all the iWMMXt builtins. This is not called if
Lines 20092-20100 Link Here
20092	tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);	20197	tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
20093	tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);	20198	tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
20094		20199
20095	tree int_ftype_int
20096	= build_function_type_list (integer_type_node,
20097	integer_type_node, NULL_TREE);
20098	tree v8qi_ftype_v8qi_v8qi_int	20200	tree v8qi_ftype_v8qi_v8qi_int
20099	= build_function_type_list (V8QI_type_node,	20201	= build_function_type_list (V8QI_type_node,
20100	V8QI_type_node, V8QI_type_node,	20202	V8QI_type_node, V8QI_type_node,
Lines 20156-20161 Link Here
20156	tree v4hi_ftype_v2si_v2si	20258	tree v4hi_ftype_v2si_v2si
20157	= build_function_type_list (V4HI_type_node,	20259	= build_function_type_list (V4HI_type_node,
20158	V2SI_type_node, V2SI_type_node, NULL_TREE);	20260	V2SI_type_node, V2SI_type_node, NULL_TREE);
		20261	tree v8qi_ftype_v4hi_v8qi
		20262	= build_function_type_list (V8QI_type_node,
		20263	V4HI_type_node, V8QI_type_node, NULL_TREE);
20159	tree v2si_ftype_v4hi_v4hi	20264	tree v2si_ftype_v4hi_v4hi
20160	= build_function_type_list (V2SI_type_node,	20265	= build_function_type_list (V2SI_type_node,
20161	V4HI_type_node, V4HI_type_node, NULL_TREE);	20266	V4HI_type_node, V4HI_type_node, NULL_TREE);
Lines 20170-20181 Link Here
20170	= build_function_type_list (V2SI_type_node,	20275	= build_function_type_list (V2SI_type_node,
20171	V2SI_type_node, long_long_integer_type_node,	20276	V2SI_type_node, long_long_integer_type_node,
20172	NULL_TREE);	20277	NULL_TREE);
20173	tree void_ftype_int_int
20174	= build_function_type_list (void_type_node,
20175	integer_type_node, integer_type_node,
20176	NULL_TREE);
20177	tree di_ftype_void	20278	tree di_ftype_void
20178	= build_function_type_list (long_long_unsigned_type_node, NULL_TREE);	20279	= build_function_type_list (long_long_unsigned_type_node, NULL_TREE);
		20280	tree int_ftype_void
		20281	= build_function_type_list (integer_type_node, NULL_TREE);
20179	tree di_ftype_v8qi	20282	tree di_ftype_v8qi
20180	= build_function_type_list (long_long_integer_type_node,	20283	= build_function_type_list (long_long_integer_type_node,
20181	V8QI_type_node, NULL_TREE);	20284	V8QI_type_node, NULL_TREE);
Lines 20191-20196 Link Here
20191	tree v4hi_ftype_v8qi	20294	tree v4hi_ftype_v8qi
20192	= build_function_type_list (V4HI_type_node,	20295	= build_function_type_list (V4HI_type_node,
20193	V8QI_type_node, NULL_TREE);	20296	V8QI_type_node, NULL_TREE);
		20297	tree v8qi_ftype_v8qi
		20298	= build_function_type_list (V8QI_type_node,
		20299	V8QI_type_node, NULL_TREE);
		20300	tree v4hi_ftype_v4hi
		20301	= build_function_type_list (V4HI_type_node,
		20302	V4HI_type_node, NULL_TREE);
		20303	tree v2si_ftype_v2si
		20304	= build_function_type_list (V2SI_type_node,
		20305	V2SI_type_node, NULL_TREE);
20194		20306
20195	tree di_ftype_di_v4hi_v4hi	20307	tree di_ftype_di_v4hi_v4hi
20196	= build_function_type_list (long_long_unsigned_type_node,	20308	= build_function_type_list (long_long_unsigned_type_node,
Lines 20203-20208 Link Here
20203	V4HI_type_node,V4HI_type_node,	20315	V4HI_type_node,V4HI_type_node,
20204	NULL_TREE);	20316	NULL_TREE);
20205		20317
		20318	tree v2si_ftype_v2si_v4hi_v4hi
		20319	= build_function_type_list (V2SI_type_node,
		20320	V2SI_type_node, V4HI_type_node,
		20321	V4HI_type_node, NULL_TREE);
		20322
		20323	tree v2si_ftype_v2si_v8qi_v8qi
		20324	= build_function_type_list (V2SI_type_node,
		20325	V2SI_type_node, V8QI_type_node,
		20326	V8QI_type_node, NULL_TREE);
		20327
		20328	tree di_ftype_di_v2si_v2si
		20329	= build_function_type_list (long_long_unsigned_type_node,
		20330	long_long_unsigned_type_node,
		20331	V2SI_type_node, V2SI_type_node,
		20332	NULL_TREE);
		20333
		20334	tree di_ftype_di_di_int
		20335	= build_function_type_list (long_long_unsigned_type_node,
		20336	long_long_unsigned_type_node,
		20337	long_long_unsigned_type_node,
		20338	integer_type_node, NULL_TREE);
		20339
		20340	tree void_ftype_void
		20341	= build_function_type_list (void_type_node,
		20342	NULL_TREE);
		20343
		20344	tree void_ftype_int
		20345	= build_function_type_list (void_type_node,
		20346	integer_type_node, NULL_TREE);
		20347
		20348	tree v8qi_ftype_char
		20349	= build_function_type_list (V8QI_type_node,
		20350	signed_char_type_node, NULL_TREE);
		20351
		20352	tree v4hi_ftype_short
		20353	= build_function_type_list (V4HI_type_node,
		20354	short_integer_type_node, NULL_TREE);
		20355
		20356	tree v2si_ftype_int
		20357	= build_function_type_list (V2SI_type_node,
		20358	integer_type_node, NULL_TREE);
		20359
20206	/* Normal vector binops. */	20360	/* Normal vector binops. */
20207	tree v8qi_ftype_v8qi_v8qi	20361	tree v8qi_ftype_v8qi_v8qi
20208	= build_function_type_list (V8QI_type_node,	20362	= build_function_type_list (V8QI_type_node,
Lines 20260-20268 Link Here
20260	def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \	20414	def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
20261	ARM_BUILTIN_ ## CODE)	20415	ARM_BUILTIN_ ## CODE)
20262		20416
		20417	#define iwmmx2_mbuiltin(NAME, TYPE, CODE) \
		20418	def_mbuiltin (FL_IWMMXT2, "__builtin_arm_" NAME, (TYPE), \
		20419	ARM_BUILTIN_ ## CODE)
		20420
20263	iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);	20421	iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
20264	iwmmx_mbuiltin ("setwcx", void_ftype_int_int, SETWCX);	20422	iwmmx_mbuiltin ("setwcgr0", void_ftype_int, SETWCGR0);
20265	iwmmx_mbuiltin ("getwcx", int_ftype_int, GETWCX);	20423	iwmmx_mbuiltin ("setwcgr1", void_ftype_int, SETWCGR1);
		20424	iwmmx_mbuiltin ("setwcgr2", void_ftype_int, SETWCGR2);
		20425	iwmmx_mbuiltin ("setwcgr3", void_ftype_int, SETWCGR3);
		20426	iwmmx_mbuiltin ("getwcgr0", int_ftype_void, GETWCGR0);
		20427	iwmmx_mbuiltin ("getwcgr1", int_ftype_void, GETWCGR1);
		20428	iwmmx_mbuiltin ("getwcgr2", int_ftype_void, GETWCGR2);
		20429	iwmmx_mbuiltin ("getwcgr3", int_ftype_void, GETWCGR3);
20266		20430
20267	iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);	20431	iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
20268	iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);	20432	iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
Lines 20294-20301 Link Here
20294		20458
20295	iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);	20459	iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
20296		20460
20297	iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi, WSADB);	20461	iwmmx_mbuiltin ("wsadb", v2si_ftype_v2si_v8qi_v8qi, WSADB);
20298	iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi, WSADH);	20462	iwmmx_mbuiltin ("wsadh", v2si_ftype_v2si_v4hi_v4hi, WSADH);
		20463	iwmmx_mbuiltin ("wmadds", v2si_ftype_v4hi_v4hi, WMADDS);
		20464	iwmmx2_mbuiltin ("wmaddsx", v2si_ftype_v4hi_v4hi, WMADDSX);
		20465	iwmmx2_mbuiltin ("wmaddsn", v2si_ftype_v4hi_v4hi, WMADDSN);
		20466	iwmmx_mbuiltin ("wmaddu", v2si_ftype_v4hi_v4hi, WMADDU);
		20467	iwmmx2_mbuiltin ("wmaddux", v2si_ftype_v4hi_v4hi, WMADDUX);
		20468	iwmmx2_mbuiltin ("wmaddun", v2si_ftype_v4hi_v4hi, WMADDUN);
20299	iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);	20469	iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
20300	iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);	20470	iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
20301		20471
Lines 20317-20322 Link Here
20317	iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);	20487	iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
20318	iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);	20488	iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
20319		20489
		20490	iwmmx2_mbuiltin ("waddbhusm", v8qi_ftype_v4hi_v8qi, WADDBHUSM);
		20491	iwmmx2_mbuiltin ("waddbhusl", v8qi_ftype_v4hi_v8qi, WADDBHUSL);
		20492
20320	iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);	20493	iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
20321	iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);	20494	iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
20322	iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);	20495	iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
Lines 20342-20348 Link Here
20342	iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);	20515	iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
20343	iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);	20516	iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
20344		20517
20345	iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGN);	20518	iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGNI);
20346	iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);	20519	iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
20347	iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);	20520	iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
20348	iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);	20521	iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
Lines 20350-20356 Link Here
20350	iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);	20523	iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
20351	iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);	20524	iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
20352		20525
		20526	iwmmx2_mbuiltin ("wabsb", v8qi_ftype_v8qi, WABSB);
		20527	iwmmx2_mbuiltin ("wabsh", v4hi_ftype_v4hi, WABSH);
		20528	iwmmx2_mbuiltin ("wabsw", v2si_ftype_v2si, WABSW);
		20529
		20530	iwmmx2_mbuiltin ("wqmiabb", v2si_ftype_v2si_v4hi_v4hi, WQMIABB);
		20531	iwmmx2_mbuiltin ("wqmiabt", v2si_ftype_v2si_v4hi_v4hi, WQMIABT);
		20532	iwmmx2_mbuiltin ("wqmiatb", v2si_ftype_v2si_v4hi_v4hi, WQMIATB);
		20533	iwmmx2_mbuiltin ("wqmiatt", v2si_ftype_v2si_v4hi_v4hi, WQMIATT);
		20534
		20535	iwmmx2_mbuiltin ("wqmiabbn", v2si_ftype_v2si_v4hi_v4hi, WQMIABBN);
		20536	iwmmx2_mbuiltin ("wqmiabtn", v2si_ftype_v2si_v4hi_v4hi, WQMIABTN);
		20537	iwmmx2_mbuiltin ("wqmiatbn", v2si_ftype_v2si_v4hi_v4hi, WQMIATBN);
		20538	iwmmx2_mbuiltin ("wqmiattn", v2si_ftype_v2si_v4hi_v4hi, WQMIATTN);
		20539
		20540	iwmmx2_mbuiltin ("wmiabb", di_ftype_di_v4hi_v4hi, WMIABB);
		20541	iwmmx2_mbuiltin ("wmiabt", di_ftype_di_v4hi_v4hi, WMIABT);
		20542	iwmmx2_mbuiltin ("wmiatb", di_ftype_di_v4hi_v4hi, WMIATB);
		20543	iwmmx2_mbuiltin ("wmiatt", di_ftype_di_v4hi_v4hi, WMIATT);
		20544
		20545	iwmmx2_mbuiltin ("wmiabbn", di_ftype_di_v4hi_v4hi, WMIABBN);
		20546	iwmmx2_mbuiltin ("wmiabtn", di_ftype_di_v4hi_v4hi, WMIABTN);
		20547	iwmmx2_mbuiltin ("wmiatbn", di_ftype_di_v4hi_v4hi, WMIATBN);
		20548	iwmmx2_mbuiltin ("wmiattn", di_ftype_di_v4hi_v4hi, WMIATTN);
		20549
		20550	iwmmx2_mbuiltin ("wmiawbb", di_ftype_di_v2si_v2si, WMIAWBB);
		20551	iwmmx2_mbuiltin ("wmiawbt", di_ftype_di_v2si_v2si, WMIAWBT);
		20552	iwmmx2_mbuiltin ("wmiawtb", di_ftype_di_v2si_v2si, WMIAWTB);
		20553	iwmmx2_mbuiltin ("wmiawtt", di_ftype_di_v2si_v2si, WMIAWTT);
		20554
		20555	iwmmx2_mbuiltin ("wmiawbbn", di_ftype_di_v2si_v2si, WMIAWBBN);
		20556	iwmmx2_mbuiltin ("wmiawbtn", di_ftype_di_v2si_v2si, WMIAWBTN);
		20557	iwmmx2_mbuiltin ("wmiawtbn", di_ftype_di_v2si_v2si, WMIAWTBN);
		20558	iwmmx2_mbuiltin ("wmiawttn", di_ftype_di_v2si_v2si, WMIAWTTN);
		20559
		20560	iwmmx2_mbuiltin ("wmerge", di_ftype_di_di_int, WMERGE);
		20561
		20562	iwmmx_mbuiltin ("tbcstb", v8qi_ftype_char, TBCSTB);
		20563	iwmmx_mbuiltin ("tbcsth", v4hi_ftype_short, TBCSTH);
		20564	iwmmx_mbuiltin ("tbcstw", v2si_ftype_int, TBCSTW);
		20565
20353	#undef iwmmx_mbuiltin	20566	#undef iwmmx_mbuiltin
		20567	#undef iwmmx2_mbuiltin
20354	}	20568	}
20355		20569
20356	static void	20570	static void
Lines 20507-20513 Link Here
20507	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))	20721	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20508	target = gen_reg_rtx (tmode);	20722	target = gen_reg_rtx (tmode);
20509		20723
20510	gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);	20724	gcc_assert ((GET_MODE (op0) == mode0 \|\| GET_MODE (op0) == VOIDmode)
		20725	&& (GET_MODE (op1) == mode1 \|\| GET_MODE (op1) == VOIDmode));
20511		20726
20512	if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))	20727	if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20513	op0 = copy_to_mode_reg (mode0, op0);	20728	op0 = copy_to_mode_reg (mode0, op0);
Lines 21015-21020 Link Here
21015	enum machine_mode mode0;	21230	enum machine_mode mode0;
21016	enum machine_mode mode1;	21231	enum machine_mode mode1;
21017	enum machine_mode mode2;	21232	enum machine_mode mode2;
		21233	int opint;
		21234	int selector;
		21235	int mask;
		21236	int imm;
21018		21237
21019	if (fcode >= ARM_BUILTIN_NEON_BASE)	21238	if (fcode >= ARM_BUILTIN_NEON_BASE)
21020	return arm_expand_neon_builtin (fcode, exp, target);	21239	return arm_expand_neon_builtin (fcode, exp, target);
Lines 21049-21054 Link Here
21049	error ("selector must be an immediate");	21268	error ("selector must be an immediate");
21050	return gen_reg_rtx (tmode);	21269	return gen_reg_rtx (tmode);
21051	}	21270	}
		21271
		21272	opint = INTVAL (op1);
		21273	if (fcode == ARM_BUILTIN_TEXTRMSB \|\| fcode == ARM_BUILTIN_TEXTRMUB)
		21274	{
		21275	if (opint > 7 \|\| opint < 0)
		21276	error ("the range of selector should be in 0 to 7");
		21277	}
		21278	else if (fcode == ARM_BUILTIN_TEXTRMSH \|\| fcode == ARM_BUILTIN_TEXTRMUH)
		21279	{
		21280	if (opint > 3 \|\| opint < 0)
		21281	error ("the range of selector should be in 0 to 3");
		21282	}
		21283	else /* ARM_BUILTIN_TEXTRMSW \|\| ARM_BUILTIN_TEXTRMUW. */
		21284	{
		21285	if (opint > 1 \|\| opint < 0)
		21286	error ("the range of selector should be in 0 to 1");
		21287	}
		21288
21052	if (target == 0	21289	if (target == 0
21053	\|\| GET_MODE (target) != tmode	21290	\|\| GET_MODE (target) != tmode
21054	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))	21291	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
Lines 21059-21069 Link Here
21059	emit_insn (pat);	21296	emit_insn (pat);
21060	return target;	21297	return target;
21061		21298
		21299	case ARM_BUILTIN_WALIGNI:
		21300	/* If op2 is immediate, call walighi, else call walighr. */
		21301	arg0 = CALL_EXPR_ARG (exp, 0);
		21302	arg1 = CALL_EXPR_ARG (exp, 1);
		21303	arg2 = CALL_EXPR_ARG (exp, 2);
		21304	op0 = expand_normal (arg0);
		21305	op1 = expand_normal (arg1);
		21306	op2 = expand_normal (arg2);
		21307	if (GET_CODE (op2) == CONST_INT)
		21308	{
		21309	icode = CODE_FOR_iwmmxt_waligni;
		21310	tmode = insn_data[icode].operand[0].mode;
		21311	mode0 = insn_data[icode].operand[1].mode;
		21312	mode1 = insn_data[icode].operand[2].mode;
		21313	mode2 = insn_data[icode].operand[3].mode;
		21314	if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
		21315	op0 = copy_to_mode_reg (mode0, op0);
		21316	if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
		21317	op1 = copy_to_mode_reg (mode1, op1);
		21318	gcc_assert ((*insn_data[icode].operand[3].predicate) (op2, mode2));
		21319	selector = INTVAL (op2);
		21320	if (selector > 7 \|\| selector < 0)
		21321	error ("the range of selector should be in 0 to 7");
		21322	}
		21323	else
		21324	{
		21325	icode = CODE_FOR_iwmmxt_walignr;
		21326	tmode = insn_data[icode].operand[0].mode;
		21327	mode0 = insn_data[icode].operand[1].mode;
		21328	mode1 = insn_data[icode].operand[2].mode;
		21329	mode2 = insn_data[icode].operand[3].mode;
		21330	if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
		21331	op0 = copy_to_mode_reg (mode0, op0);
		21332	if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
		21333	op1 = copy_to_mode_reg (mode1, op1);
		21334	if (!(*insn_data[icode].operand[3].predicate) (op2, mode2))
		21335	op2 = copy_to_mode_reg (mode2, op2);
		21336	}
		21337	if (target == 0
		21338	\|\| GET_MODE (target) != tmode
		21339	\|\| !(*insn_data[icode].operand[0].predicate) (target, tmode))
		21340	target = gen_reg_rtx (tmode);
		21341	pat = GEN_FCN (icode) (target, op0, op1, op2);
		21342	if (!pat)
		21343	return 0;
		21344	emit_insn (pat);
		21345	return target;
		21346
21062	case ARM_BUILTIN_TINSRB:	21347	case ARM_BUILTIN_TINSRB:
21063	case ARM_BUILTIN_TINSRH:	21348	case ARM_BUILTIN_TINSRH:
21064	case ARM_BUILTIN_TINSRW:	21349	case ARM_BUILTIN_TINSRW:
		21350	case ARM_BUILTIN_WMERGE:
21065	icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb	21351	icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
21066	: fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh	21352	: fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
		21353	: fcode == ARM_BUILTIN_WMERGE ? CODE_FOR_iwmmxt_wmerge
21067	: CODE_FOR_iwmmxt_tinsrw);	21354	: CODE_FOR_iwmmxt_tinsrw);
21068	arg0 = CALL_EXPR_ARG (exp, 0);	21355	arg0 = CALL_EXPR_ARG (exp, 0);
21069	arg1 = CALL_EXPR_ARG (exp, 1);	21356	arg1 = CALL_EXPR_ARG (exp, 1);
Lines 21082-21091 Link Here
21082	op1 = copy_to_mode_reg (mode1, op1);	21369	op1 = copy_to_mode_reg (mode1, op1);
21083	if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))	21370	if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
21084	{	21371	{
21085	/* @@@ better error message */
21086	error ("selector must be an immediate");	21372	error ("selector must be an immediate");
21087	return const0_rtx;	21373	return const0_rtx;
21088	}	21374	}
		21375	if (icode == CODE_FOR_iwmmxt_wmerge)
		21376	{
		21377	selector = INTVAL (op2);
		21378	if (selector > 7 \|\| selector < 0)
		21379	error ("the range of selector should be in 0 to 7");
		21380	}
		21381	if ((icode == CODE_FOR_iwmmxt_tinsrb)
		21382	\|\| (icode == CODE_FOR_iwmmxt_tinsrh)
		21383	\|\| (icode == CODE_FOR_iwmmxt_tinsrw))
		21384	{
		21385	mask = 0x01;
		21386	selector= INTVAL (op2);
		21387	if (icode == CODE_FOR_iwmmxt_tinsrb && (selector < 0 \|\| selector > 7))
		21388	error ("the range of selector should be in 0 to 7");
		21389	else if (icode == CODE_FOR_iwmmxt_tinsrh && (selector < 0 \|\|selector > 3))
		21390	error ("the range of selector should be in 0 to 3");
		21391	else if (icode == CODE_FOR_iwmmxt_tinsrw && (selector < 0 \|\|selector > 1))
		21392	error ("the range of selector should be in 0 to 1");
		21393	mask <<= selector;
		21394	op2 = gen_rtx_CONST_INT (SImode, mask);
		21395	}
21089	if (target == 0	21396	if (target == 0
21090	\|\| GET_MODE (target) != tmode	21397	\|\| GET_MODE (target) != tmode
21091	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))	21398	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
Lines 21096-21114 Link Here
21096	emit_insn (pat);	21403	emit_insn (pat);
21097	return target;	21404	return target;
21098		21405
21099	case ARM_BUILTIN_SETWCX:	21406	case ARM_BUILTIN_SETWCGR0:
		21407	case ARM_BUILTIN_SETWCGR1:
		21408	case ARM_BUILTIN_SETWCGR2:
		21409	case ARM_BUILTIN_SETWCGR3:
		21410	icode = (fcode == ARM_BUILTIN_SETWCGR0 ? CODE_FOR_iwmmxt_setwcgr0
		21411	: fcode == ARM_BUILTIN_SETWCGR1 ? CODE_FOR_iwmmxt_setwcgr1
		21412	: fcode == ARM_BUILTIN_SETWCGR2 ? CODE_FOR_iwmmxt_setwcgr2
		21413	: CODE_FOR_iwmmxt_setwcgr3);
21100	arg0 = CALL_EXPR_ARG (exp, 0);	21414	arg0 = CALL_EXPR_ARG (exp, 0);
21101	arg1 = CALL_EXPR_ARG (exp, 1);	21415	op0 = expand_normal (arg0);
21102	op0 = force_reg (SImode, expand_normal (arg0));	21416	mode0 = insn_data[icode].operand[0].mode;
21103	op1 = expand_normal (arg1);	21417	if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
21104	emit_insn (gen_iwmmxt_tmcr (op1, op0));	21418	op0 = copy_to_mode_reg (mode0, op0);
		21419	pat = GEN_FCN (icode) (op0);
		21420	if (!pat)
		21421	return 0;
		21422	emit_insn (pat);
21105	return 0;	21423	return 0;
21106		21424
21107	case ARM_BUILTIN_GETWCX:	21425	case ARM_BUILTIN_GETWCGR0:
21108	arg0 = CALL_EXPR_ARG (exp, 0);	21426	case ARM_BUILTIN_GETWCGR1:
21109	op0 = expand_normal (arg0);	21427	case ARM_BUILTIN_GETWCGR2:
21110	target = gen_reg_rtx (SImode);	21428	case ARM_BUILTIN_GETWCGR3:
21111	emit_insn (gen_iwmmxt_tmrc (target, op0));	21429	icode = (fcode == ARM_BUILTIN_GETWCGR0 ? CODE_FOR_iwmmxt_getwcgr0
		21430	: fcode == ARM_BUILTIN_GETWCGR1 ? CODE_FOR_iwmmxt_getwcgr1
		21431	: fcode == ARM_BUILTIN_GETWCGR2 ? CODE_FOR_iwmmxt_getwcgr2
		21432	: CODE_FOR_iwmmxt_getwcgr3);
		21433	tmode = insn_data[icode].operand[0].mode;
		21434	if (target == 0
		21435	\|\| GET_MODE (target) != tmode
		21436	\|\| !(*insn_data[icode].operand[0].predicate) (target, tmode))
		21437	target = gen_reg_rtx (tmode);
		21438	pat = GEN_FCN (icode) (target);
		21439	if (!pat)
		21440	return 0;
		21441	emit_insn (pat);
21112	return target;	21442	return target;
21113		21443
21114	case ARM_BUILTIN_WSHUFH:	21444	case ARM_BUILTIN_WSHUFH:
Lines 21125-21134 Link Here
21125	op0 = copy_to_mode_reg (mode1, op0);	21455	op0 = copy_to_mode_reg (mode1, op0);
21126	if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))	21456	if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21127	{	21457	{
21128	/* @@@ better error message */
21129	error ("mask must be an immediate");	21458	error ("mask must be an immediate");
21130	return const0_rtx;	21459	return const0_rtx;
21131	}	21460	}
		21461	selector = INTVAL (op1);
		21462	if (selector < 0 \|\| selector > 255)
		21463	error ("the range of mask should be in 0 to 255");
21132	if (target == 0	21464	if (target == 0
21133	\|\| GET_MODE (target) != tmode	21465	\|\| GET_MODE (target) != tmode
21134	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))	21466	\|\| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
Lines 21139-21148 Link Here
21139	emit_insn (pat);	21471	emit_insn (pat);
21140	return target;	21472	return target;
21141		21473
21142	case ARM_BUILTIN_WSADB:	21474	case ARM_BUILTIN_WMADDS:
21143	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);	21475	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmadds, exp, target);
21144	case ARM_BUILTIN_WSADH:	21476	case ARM_BUILTIN_WMADDSX:
21145	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);	21477	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsx, exp, target);
		21478	case ARM_BUILTIN_WMADDSN:
		21479	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddsn, exp, target);
		21480	case ARM_BUILTIN_WMADDU:
		21481	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddu, exp, target);
		21482	case ARM_BUILTIN_WMADDUX:
		21483	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddux, exp, target);
		21484	case ARM_BUILTIN_WMADDUN:
		21485	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wmaddun, exp, target);
21146	case ARM_BUILTIN_WSADBZ:	21486	case ARM_BUILTIN_WSADBZ:
21147	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);	21487	return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
21148	case ARM_BUILTIN_WSADHZ:	21488	case ARM_BUILTIN_WSADHZ:
Lines 21151-21163 Link Here
21151	/* Several three-argument builtins. */	21491	/* Several three-argument builtins. */
21152	case ARM_BUILTIN_WMACS:	21492	case ARM_BUILTIN_WMACS:
21153	case ARM_BUILTIN_WMACU:	21493	case ARM_BUILTIN_WMACU:
21154	case ARM_BUILTIN_WALIGN:
21155	case ARM_BUILTIN_TMIA:	21494	case ARM_BUILTIN_TMIA:
21156	case ARM_BUILTIN_TMIAPH:	21495	case ARM_BUILTIN_TMIAPH:
21157	case ARM_BUILTIN_TMIATT:	21496	case ARM_BUILTIN_TMIATT:
21158	case ARM_BUILTIN_TMIATB:	21497	case ARM_BUILTIN_TMIATB:
21159	case ARM_BUILTIN_TMIABT:	21498	case ARM_BUILTIN_TMIABT:
21160	case ARM_BUILTIN_TMIABB:	21499	case ARM_BUILTIN_TMIABB:
		21500	case ARM_BUILTIN_WQMIABB:
		21501	case ARM_BUILTIN_WQMIABT:
		21502	case ARM_BUILTIN_WQMIATB:
		21503	case ARM_BUILTIN_WQMIATT:
		21504	case ARM_BUILTIN_WQMIABBN:
		21505	case ARM_BUILTIN_WQMIABTN:
		21506	case ARM_BUILTIN_WQMIATBN:
		21507	case ARM_BUILTIN_WQMIATTN:
		21508	case ARM_BUILTIN_WMIABB:
		21509	case ARM_BUILTIN_WMIABT:
		21510	case ARM_BUILTIN_WMIATB:
		21511	case ARM_BUILTIN_WMIATT:
		21512	case ARM_BUILTIN_WMIABBN:
		21513	case ARM_BUILTIN_WMIABTN:
		21514	case ARM_BUILTIN_WMIATBN:
		21515	case ARM_BUILTIN_WMIATTN:
		21516	case ARM_BUILTIN_WMIAWBB:
		21517	case ARM_BUILTIN_WMIAWBT:
		21518	case ARM_BUILTIN_WMIAWTB:
		21519	case ARM_BUILTIN_WMIAWTT:
		21520	case ARM_BUILTIN_WMIAWBBN:
		21521	case ARM_BUILTIN_WMIAWBTN:
		21522	case ARM_BUILTIN_WMIAWTBN:
		21523	case ARM_BUILTIN_WMIAWTTN:
		21524	case ARM_BUILTIN_WSADB:
		21525	case ARM_BUILTIN_WSADH:
21161	icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs	21526	icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
21162	: fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu	21527	: fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
21163	: fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia	21528	: fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
Lines 21166-21172 Link Here
21166	: fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt	21531	: fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
21167	: fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb	21532	: fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
21168	: fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt	21533	: fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
21169	: CODE_FOR_iwmmxt_walign);	21534	: fcode == ARM_BUILTIN_WQMIABB ? CODE_FOR_iwmmxt_wqmiabb
		21535	: fcode == ARM_BUILTIN_WQMIABT ? CODE_FOR_iwmmxt_wqmiabt
		21536	: fcode == ARM_BUILTIN_WQMIATB ? CODE_FOR_iwmmxt_wqmiatb
		21537	: fcode == ARM_BUILTIN_WQMIATT ? CODE_FOR_iwmmxt_wqmiatt
		21538	: fcode == ARM_BUILTIN_WQMIABBN ? CODE_FOR_iwmmxt_wqmiabbn
		21539	: fcode == ARM_BUILTIN_WQMIABTN ? CODE_FOR_iwmmxt_wqmiabtn
		21540	: fcode == ARM_BUILTIN_WQMIATBN ? CODE_FOR_iwmmxt_wqmiatbn
		21541	: fcode == ARM_BUILTIN_WQMIATTN ? CODE_FOR_iwmmxt_wqmiattn
		21542	: fcode == ARM_BUILTIN_WMIABB ? CODE_FOR_iwmmxt_wmiabb
		21543	: fcode == ARM_BUILTIN_WMIABT ? CODE_FOR_iwmmxt_wmiabt
		21544	: fcode == ARM_BUILTIN_WMIATB ? CODE_FOR_iwmmxt_wmiatb
		21545	: fcode == ARM_BUILTIN_WMIATT ? CODE_FOR_iwmmxt_wmiatt
		21546	: fcode == ARM_BUILTIN_WMIABBN ? CODE_FOR_iwmmxt_wmiabbn
		21547	: fcode == ARM_BUILTIN_WMIABTN ? CODE_FOR_iwmmxt_wmiabtn
		21548	: fcode == ARM_BUILTIN_WMIATBN ? CODE_FOR_iwmmxt_wmiatbn
		21549	: fcode == ARM_BUILTIN_WMIATTN ? CODE_FOR_iwmmxt_wmiattn
		21550	: fcode == ARM_BUILTIN_WMIAWBB ? CODE_FOR_iwmmxt_wmiawbb
		21551	: fcode == ARM_BUILTIN_WMIAWBT ? CODE_FOR_iwmmxt_wmiawbt
		21552	: fcode == ARM_BUILTIN_WMIAWTB ? CODE_FOR_iwmmxt_wmiawtb
		21553	: fcode == ARM_BUILTIN_WMIAWTT ? CODE_FOR_iwmmxt_wmiawtt
		21554	: fcode == ARM_BUILTIN_WMIAWBBN ? CODE_FOR_iwmmxt_wmiawbbn
		21555	: fcode == ARM_BUILTIN_WMIAWBTN ? CODE_FOR_iwmmxt_wmiawbtn
		21556	: fcode == ARM_BUILTIN_WMIAWTBN ? CODE_FOR_iwmmxt_wmiawtbn
		21557	: fcode == ARM_BUILTIN_WMIAWTTN ? CODE_FOR_iwmmxt_wmiawttn
		21558	: fcode == ARM_BUILTIN_WSADB ? CODE_FOR_iwmmxt_wsadb
		21559	: CODE_FOR_iwmmxt_wsadh);
21170	arg0 = CALL_EXPR_ARG (exp, 0);	21560	arg0 = CALL_EXPR_ARG (exp, 0);
21171	arg1 = CALL_EXPR_ARG (exp, 1);	21561	arg1 = CALL_EXPR_ARG (exp, 1);
21172	arg2 = CALL_EXPR_ARG (exp, 2);	21562	arg2 = CALL_EXPR_ARG (exp, 2);
Lines 21199-21204 Link Here
21199	emit_insn (gen_iwmmxt_clrdi (target));	21589	emit_insn (gen_iwmmxt_clrdi (target));
21200	return target;	21590	return target;
21201		21591
		21592	case ARM_BUILTIN_WSRLHI:
		21593	case ARM_BUILTIN_WSRLWI:
		21594	case ARM_BUILTIN_WSRLDI:
		21595	case ARM_BUILTIN_WSLLHI:
		21596	case ARM_BUILTIN_WSLLWI:
		21597	case ARM_BUILTIN_WSLLDI:
		21598	case ARM_BUILTIN_WSRAHI:
		21599	case ARM_BUILTIN_WSRAWI:
		21600	case ARM_BUILTIN_WSRADI:
		21601	case ARM_BUILTIN_WRORHI:
		21602	case ARM_BUILTIN_WRORWI:
		21603	case ARM_BUILTIN_WRORDI:
		21604	case ARM_BUILTIN_WSRLH:
		21605	case ARM_BUILTIN_WSRLW:
		21606	case ARM_BUILTIN_WSRLD:
		21607	case ARM_BUILTIN_WSLLH:
		21608	case ARM_BUILTIN_WSLLW:
		21609	case ARM_BUILTIN_WSLLD:
		21610	case ARM_BUILTIN_WSRAH:
		21611	case ARM_BUILTIN_WSRAW:
		21612	case ARM_BUILTIN_WSRAD:
		21613	case ARM_BUILTIN_WRORH:
		21614	case ARM_BUILTIN_WRORW:
		21615	case ARM_BUILTIN_WRORD:
		21616	icode = (fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt
		21617	: fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt
		21618	: fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt
		21619	: fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt
		21620	: fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt
		21621	: fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt
		21622	: fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt
		21623	: fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt
		21624	: fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt
		21625	: fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3
		21626	: fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3
		21627	: fcode == ARM_BUILTIN_WRORDI ? CODE_FOR_rordi3
		21628	: fcode == ARM_BUILTIN_WSRLH ? CODE_FOR_lshrv4hi3_di
		21629	: fcode == ARM_BUILTIN_WSRLW ? CODE_FOR_lshrv2si3_di
		21630	: fcode == ARM_BUILTIN_WSRLD ? CODE_FOR_lshrdi3_di
		21631	: fcode == ARM_BUILTIN_WSLLH ? CODE_FOR_ashlv4hi3_di
		21632	: fcode == ARM_BUILTIN_WSLLW ? CODE_FOR_ashlv2si3_di
		21633	: fcode == ARM_BUILTIN_WSLLD ? CODE_FOR_ashldi3_di
		21634	: fcode == ARM_BUILTIN_WSRAH ? CODE_FOR_ashrv4hi3_di
		21635	: fcode == ARM_BUILTIN_WSRAW ? CODE_FOR_ashrv2si3_di
		21636	: fcode == ARM_BUILTIN_WSRAD ? CODE_FOR_ashrdi3_di
		21637	: fcode == ARM_BUILTIN_WRORH ? CODE_FOR_rorv4hi3_di
		21638	: fcode == ARM_BUILTIN_WRORW ? CODE_FOR_rorv2si3_di
		21639	: fcode == ARM_BUILTIN_WRORD ? CODE_FOR_rordi3_di
		21640	: CODE_FOR_nothing);
		21641	arg1 = CALL_EXPR_ARG (exp, 1);
		21642	op1 = expand_normal (arg1);
		21643	if (GET_MODE (op1) == VOIDmode)
		21644	{
		21645	imm = INTVAL (op1);
		21646	if ((fcode == ARM_BUILTIN_WRORHI \|\| fcode == ARM_BUILTIN_WRORWI
		21647	\|\| fcode == ARM_BUILTIN_WRORH \|\| fcode == ARM_BUILTIN_WRORW)
		21648	&& (imm < 0 \|\| imm > 32))
		21649	{
		21650	if (fcode == ARM_BUILTIN_WRORHI)
		21651	error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi16 in code.");
		21652	else if (fcode == ARM_BUILTIN_WRORWI)
		21653	error ("the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi32 in code.");
		21654	else if (fcode == ARM_BUILTIN_WRORH)
		21655	error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi16 in code.");
21656	else
21657	error ("the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi32 in code.");
21658	}
21659	else if ((fcode == ARM_BUILTIN_WRORDI \|\| fcode == ARM_BUILTIN_WRORD)
21660	&& (imm < 0 \|\| imm > 64))
21661	{
21662	if (fcode == ARM_BUILTIN_WRORDI)
21663	error ("the range of count should be in 0 to 64. please check the intrinsic _mm_rori_si64 in code.");
21664	else
21665	error ("the range of count should be in 0 to 64. please check the intrinsic _mm_ror_si64 in code.");
21666	}
21667	else if (imm < 0)
21668	{
21669	if (fcode == ARM_BUILTIN_WSRLHI)
21670	error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi16 in code.");
21671	else if (fcode == ARM_BUILTIN_WSRLWI)
21672	error ("the count should be no less than 0. please check the intrinsic _mm_srli_pi32 in code.");
21673	else if (fcode == ARM_BUILTIN_WSRLDI)
21674	error ("the count should be no less than 0. please check the intrinsic _mm_srli_si64 in code.");
21675	else if (fcode == ARM_BUILTIN_WSLLHI)
21676	error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi16 in code.");
21677	else if (fcode == ARM_BUILTIN_WSLLWI)
21678	error ("the count should be no less than 0. please check the intrinsic _mm_slli_pi32 in code.");
21679	else if (fcode == ARM_BUILTIN_WSLLDI)
21680	error ("the count should be no less than 0. please check the intrinsic _mm_slli_si64 in code.");
21681	else if (fcode == ARM_BUILTIN_WSRAHI)
21682	error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi16 in code.");
21683	else if (fcode == ARM_BUILTIN_WSRAWI)
21684	error ("the count should be no less than 0. please check the intrinsic _mm_srai_pi32 in code.");
21685	else if (fcode == ARM_BUILTIN_WSRADI)
21686	error ("the count should be no less than 0. please check the intrinsic _mm_srai_si64 in code.");
21687	else if (fcode == ARM_BUILTIN_WSRLH)
21688	error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi16 in code.");
21689	else if (fcode == ARM_BUILTIN_WSRLW)
21690	error ("the count should be no less than 0. please check the intrinsic _mm_srl_pi32 in code.");
21691	else if (fcode == ARM_BUILTIN_WSRLD)
21692	error ("the count should be no less than 0. please check the intrinsic _mm_srl_si64 in code.");
21693	else if (fcode == ARM_BUILTIN_WSLLH)
21694	error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi16 in code.");
21695	else if (fcode == ARM_BUILTIN_WSLLW)
21696	error ("the count should be no less than 0. please check the intrinsic _mm_sll_pi32 in code.");
21697	else if (fcode == ARM_BUILTIN_WSLLD)
21698	error ("the count should be no less than 0. please check the intrinsic _mm_sll_si64 in code.");
21699	else if (fcode == ARM_BUILTIN_WSRAH)
21700	error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi16 in code.");
21701	else if (fcode == ARM_BUILTIN_WSRAW)
21702	error ("the count should be no less than 0. please check the intrinsic _mm_sra_pi32 in code.");
21703	else
21704	error ("the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code.");
21705	}
21706	}
21707	return arm_expand_binop_builtin (icode, exp, target);
21708
21202	case ARM_BUILTIN_THREAD_POINTER:	21709	case ARM_BUILTIN_THREAD_POINTER:
21203	return arm_load_tp (target);	21710	return arm_load_tp (target);
21204		21711
Lines 24287-24292 Link Here
24287	return "";	24794	return "";
24288	}	24795	}
24289		24796
		24797	/* Output assembly for a WMMX immediate shift instruction. */
		24798	const char *
		24799	arm_output_iwmmxt_shift_immediate (const char insn_name, rtx operands, bool wror_or_wsra)
		24800	{
		24801	int shift = INTVAL (operands[2]);
		24802	char templ[50];
		24803	enum machine_mode opmode = GET_MODE (operands[0]);
		24804
		24805	gcc_assert (shift >= 0);
		24806
		24807	/* If the shift value in the register versions is > 63 (for D qualifier),
		24808	31 (for W qualifier) or 15 (for H qualifier). */
		24809	if (((opmode == V4HImode) && (shift > 15))
		24810	\|\| ((opmode == V2SImode) && (shift > 31))
		24811	\|\| ((opmode == DImode) && (shift > 63)))
		24812	{
		24813	if (wror_or_wsra)
		24814	{
		24815	sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32);
		24816	output_asm_insn (templ, operands);
		24817	if (opmode == DImode)
		24818	{
		24819	sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, 32);
		24820	output_asm_insn (templ, operands);
		24821	}
		24822	}
		24823	else
		24824	{
		24825	/* The destination register will contain all zeros. */
		24826	sprintf (templ, "wzero\t%%0");
		24827	output_asm_insn (templ, operands);
		24828	}
		24829	return "";
		24830	}
		24831
		24832	if ((opmode == DImode) && (shift > 32))
		24833	{
		24834	sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32);
		24835	output_asm_insn (templ, operands);
		24836	sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, shift - 32);
		24837	output_asm_insn (templ, operands);
		24838	}
		24839	else
		24840	{
		24841	sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, shift);
		24842	output_asm_insn (templ, operands);
		24843	}
		24844	return "";
		24845	}
		24846
		24847	/* Output assembly for a WMMX tinsr instruction. */
		24848	const char *
		24849	arm_output_iwmmxt_tinsr (rtx *operands)
		24850	{
		24851	int mask = INTVAL (operands[3]);
		24852	int i;
		24853	char templ[50];
		24854	int units = mode_nunits[GET_MODE (operands[0])];
		24855	gcc_assert ((mask & (mask - 1)) == 0);
		24856	for (i = 0; i < units; ++i)
		24857	{
		24858	if ((mask & 0x01) == 1)
		24859	{
		24860	break;
24861	}
24862	mask >>= 1;
24863	}
24864	gcc_assert (i < units);
24865	{
24866	switch (GET_MODE (operands[0]))
24867	{
24868	case V8QImode:
24869	sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i);
24870	break;
24871	case V4HImode:
24872	sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i);
24873	break;
24874	case V2SImode:
24875	sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i);
24876	break;
24877	default:
24878	gcc_unreachable ();
24879	break;
24880	}
24881	output_asm_insn (templ, operands);
24882	}
24883	return "";
24884	}
24885
24290	/* Output a Thumb-1 casesi dispatch sequence. */	24886	/* Output a Thumb-1 casesi dispatch sequence. */
24291	const char *	24887	const char *
24292	thumb1_output_casesi (rtx *operands)	24888	thumb1_output_casesi (rtx *operands)

Lines 1-5 Link Here

(-)gcc/config/arm/arm-cores.def (-2 / +2 lines)
1	/* ARM CPU Cores	1	/* ARM CPU Cores
2	Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010	2	Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2012
3	Free Software Foundation, Inc.	3	Free Software Foundation, Inc.
4	Written by CodeSourcery, LLC	4	Written by CodeSourcery, LLC
5		5
Lines 105-111 Link Here
105	ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul)	105	ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul)
106	ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE, xscale)	106	ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE, xscale)
107	ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE \| FL_IWMMXT, xscale)	107	ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE \| FL_IWMMXT, xscale)
108	ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE \| FL_IWMMXT, xscale)	108	ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED \| FL_STRONG \| FL_XSCALE \| FL_IWMMXT \| FL_IWMMXT2, xscale)
109	ARM_CORE("fa606te", fa606te, 5TE, FL_LDSCHED, 9e)	109	ARM_CORE("fa606te", fa606te, 5TE, FL_LDSCHED, 9e)
110	ARM_CORE("fa626te", fa626te, 5TE, FL_LDSCHED, 9e)	110	ARM_CORE("fa626te", fa626te, 5TE, FL_LDSCHED, 9e)
111	ARM_CORE("fmp626", fmp626, 5TE, FL_LDSCHED, 9e)	111	ARM_CORE("fmp626", fmp626, 5TE, FL_LDSCHED, 9e)

Lines 97-102 Link Here

(-)gcc/config/arm/arm.h (+7 lines)
97	builtin_define ("__XSCALE__"); \	97	builtin_define ("__XSCALE__"); \
98	if (arm_arch_iwmmxt) \	98	if (arm_arch_iwmmxt) \
99	builtin_define ("__IWMMXT__"); \	99	builtin_define ("__IWMMXT__"); \
		100	if (arm_arch_iwmmxt2) \
		101	builtin_define ("__IWMMXT2__"); \
100	if (TARGET_AAPCS_BASED) \	102	if (TARGET_AAPCS_BASED) \
101	{ \	103	{ \
102	if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \	104	if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
Lines 194-200 Link Here
194	#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)	196	#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
195	#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)	197	#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
196	#define TARGET_IWMMXT (arm_arch_iwmmxt)	198	#define TARGET_IWMMXT (arm_arch_iwmmxt)
		199	#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
197	#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)	200	#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
		201	#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
198	#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)	202	#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
199	#define TARGET_ARM (! TARGET_THUMB)	203	#define TARGET_ARM (! TARGET_THUMB)
200	#define TARGET_EITHER 1 /* (TARGET_ARM \| TARGET_THUMB) */	204	#define TARGET_EITHER 1 /* (TARGET_ARM \| TARGET_THUMB) */
Lines 410-415 Link Here
410	/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */	414	/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
411	extern int arm_arch_iwmmxt;	415	extern int arm_arch_iwmmxt;
412		416
		417	/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
		418	extern int arm_arch_iwmmxt2;
		419
413	/* Nonzero if this chip is an XScale. */	420	/* Nonzero if this chip is an XScale. */
414	extern int arm_arch_xscale;	421	extern int arm_arch_xscale;
415		422




;; UNSPEC Usage:
;; Note: sin and cos are no-longer used.
;; Unspec enumerators for Neon are defined in neon.md.
;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md

(define_c_enum "unspec" [
  UNSPEC_SIN            ; `sin' operation (MODE_FLOAT):

  UNSPEC_WMACSZ         ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
  UNSPEC_WMACUZ         ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
  UNSPEC_CLRDI          ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
  UNSPEC_WALIGNI        ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
  UNSPEC_WMADDU         ; Used by the intrinsic form of the iWMMXt WMADDU instruction.
  UNSPEC_TLS            ; A symbol that has been treated properly for TLS usage.
  UNSPEC_PIC_LABEL      ; A label used for PIC access that does not appear in the
                        ; instruction stream.

; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
; arm_arch6.  This attribute is used to compute attribute "enabled",
; use type "any" to enable an alternative in all cases.
(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,nota8,iwmmxt,iwmmxt2"
  (const_string "any"))

(define_attr "arch_enabled" "no,yes"


	 (and (eq_attr "arch" "nota8")
	      (not (eq_attr "tune" "cortexa8")))
	 (const_string "yes")

	 (and (eq_attr "arch" "iwmmxt2")
	      (match_test "TARGET_REALLY_IWMMXT2"))
	 (const_string "yes")]
	(const_string "no")))


	       (const_string "yes")
	       (const_string "no")))

; wtype for WMMX insn scheduling purposes.
(define_attr "wtype"
        "none,wor,wxor,wand,wandn,wmov,tmcrr,tmrrc,wldr,wstr,tmcr,tmrc,wadd,wsub,wmul,wmac,wavg2,tinsr,textrm,wshufh,wcmpeq,wcmpgt,wmax,wmin,wpack,wunpckih,wunpckil,wunpckeh,wunpckel,wror,wsra,wsrl,wsll,wmadd,tmia,tmiaph,tmiaxy,tbcst,tmovmsk,wacc,waligni,walignr,tandc,textrc,torc,torvsc,wsad,wabs,wabsdiff,waddsubhx,wsubaddhx,wavg4,wmulw,wqmulm,wqmulwm,waddbhus,wqmiaxy,wmiaxy,wmiawxy,wmerge" (const_string "none"))

; Load scheduling, set from the arm_ld_sched variable
; initialized by arm_option_override()
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))

	  (const_string "yes")
	  (const_string "no"))))

(include "marvell-f-iwmmxt.md")
(include "arm-generic.md")
(include "arm926ejs.md")
(include "arm1020e.md")

Lines 156-161 Link Here

(-)gcc/config/arm/arm-protos.h (+2 lines)
156	extern void arm_set_return_address (rtx, rtx);	156	extern void arm_set_return_address (rtx, rtx);
157	extern int arm_eliminable_register (rtx);	157	extern int arm_eliminable_register (rtx);
158	extern const char arm_output_shift(rtx , int);	158	extern const char arm_output_shift(rtx , int);
		159	extern const char arm_output_iwmmxt_shift_immediate (const char , rtx *, bool);
		160	extern const char arm_output_iwmmxt_tinsr (rtx );
159	extern unsigned int arm_sync_loop_insns (rtx , rtx *);	161	extern unsigned int arm_sync_loop_insns (rtx , rtx *);
160	extern int arm_attr_length_push_multi(rtx, rtx);	162	extern int arm_attr_length_push_multi(rtx, rtx);
161	extern void arm_expand_compare_and_swap (rtx op[]);	163	extern void arm_expand_compare_and_swap (rtx op[]);

Lines 1-5 Link Here

(-)gcc/config/arm/iterators.md (-1 / +3 lines)
1	;; Code and mode itertator and attribute definitions for the ARM backend	1	;; Code and mode itertator and attribute definitions for the ARM backend
2	;; Copyright (C) 2010 Free Software Foundation, Inc.	2	;; Copyright (C) 2010, 2012 Free Software Foundation, Inc.
3	;; Contributed by ARM Ltd.	3	;; Contributed by ARM Ltd.
4	;;	4	;;
5	;; This file is part of GCC.	5	;; This file is part of GCC.
Lines 45-50 Link Here
45	;; Integer element sizes implemented by IWMMXT.	45	;; Integer element sizes implemented by IWMMXT.
46	(define_mode_iterator VMMX [V2SI V4HI V8QI])	46	(define_mode_iterator VMMX [V2SI V4HI V8QI])
47		47
		48	(define_mode_iterator VMMX2 [V4HI V2SI])
		49
48	;; Integer element sizes for shifts.	50	;; Integer element sizes for shifts.
49	(define_mode_iterator VSHFT [V4HI V2SI DI])	51	(define_mode_iterator VSHFT [V4HI V2SI DI])
50		52




;; Patterns for the Intel Wireless MMX technology architecture.
;; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
;; Written by Marvell, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

(define_c_enum "unspec" [
  UNSPEC_WADDC		; Used by the intrinsic form of the iWMMXt WADDC instruction.
  UNSPEC_WABS		; Used by the intrinsic form of the iWMMXt WABS instruction.
  UNSPEC_WQMULWMR	; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
  UNSPEC_WQMULMR	; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
  UNSPEC_WQMULWM	; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
  UNSPEC_WQMULM		; Used by the intrinsic form of the iWMMXt WQMULM instruction.
  UNSPEC_WQMIAxyn	; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
  UNSPEC_WQMIAxy	; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
  UNSPEC_TANDC		; Used by the intrinsic form of the iWMMXt TANDC instruction.
  UNSPEC_TORC		; Used by the intrinsic form of the iWMMXt TORC instruction.
  UNSPEC_TORVSC		; Used by the intrinsic form of the iWMMXt TORVSC instruction.
  UNSPEC_TEXTRC		; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
])

(define_insn "iwmmxt_wabs<mode>3"
  [(set (match_operand:VMMX               0 "register_operand" "=y")
        (unspec:VMMX [(match_operand:VMMX 1 "register_operand"  "y")] UNSPEC_WABS))]
  "TARGET_REALLY_IWMMXT"
  "wabs<MMX_char>%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wabs")]
)

(define_insn "iwmmxt_wabsdiffb"
  [(set (match_operand:V8QI                          0 "register_operand" "=y")
	(truncate:V8QI
	  (abs:V8HI
	    (minus:V8HI
	      (zero_extend:V8HI (match_operand:V8QI  1 "register_operand"  "y"))
	      (zero_extend:V8HI (match_operand:V8QI  2 "register_operand"  "y"))))))]
 "TARGET_REALLY_IWMMXT"
 "wabsdiffb%?\\t%0, %1, %2"
 [(set_attr "predicable" "yes")
  (set_attr "wtype" "wabsdiff")]
)

(define_insn "iwmmxt_wabsdiffh"
  [(set (match_operand:V4HI                          0 "register_operand" "=y")
        (truncate: V4HI
          (abs:V4SI
            (minus:V4SI
              (zero_extend:V4SI (match_operand:V4HI  1 "register_operand"  "y"))
	      (zero_extend:V4SI (match_operand:V4HI  2 "register_operand"  "y"))))))]
  "TARGET_REALLY_IWMMXT"
  "wabsdiffh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wabsdiff")]
)

(define_insn "iwmmxt_wabsdiffw"
  [(set (match_operand:V2SI                          0 "register_operand" "=y")
        (truncate: V2SI
	  (abs:V2DI
	    (minus:V2DI
	      (zero_extend:V2DI (match_operand:V2SI  1 "register_operand"  "y"))
	      (zero_extend:V2DI (match_operand:V2SI  2 "register_operand"  "y"))))))]
 "TARGET_REALLY_IWMMXT"
 "wabsdiffw%?\\t%0, %1, %2"
 [(set_attr "predicable" "yes")
  (set_attr "wtype" "wabsdiff")]
)

(define_insn "iwmmxt_waddsubhx"
  [(set (match_operand:V4HI                                        0 "register_operand" "=y")
	(vec_merge:V4HI
	  (ss_minus:V4HI
	    (match_operand:V4HI                                    1 "register_operand" "y")
	    (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
	                     (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
	  (ss_plus:V4HI
	    (match_dup 1)
	    (vec_select:V4HI (match_dup 2)
	                     (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
	  (const_int 10)))]
  "TARGET_REALLY_IWMMXT"
  "waddsubhx%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "waddsubhx")]
)

(define_insn "iwmmxt_wsubaddhx"
  [(set (match_operand:V4HI                                        0 "register_operand" "=y")
	(vec_merge:V4HI
	  (ss_plus:V4HI
	    (match_operand:V4HI                                    1 "register_operand" "y")
	    (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
	                     (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
	  (ss_minus:V4HI
	    (match_dup 1)
	    (vec_select:V4HI (match_dup 2)
	                     (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))
	  (const_int 10)))]
  "TARGET_REALLY_IWMMXT"
  "wsubaddhx%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsubaddhx")]
)

(define_insn "addc<mode>3"
  [(set (match_operand:VMMX2      0 "register_operand" "=y")
	(unspec:VMMX2
          [(plus:VMMX2
             (match_operand:VMMX2 1 "register_operand"  "y")
	     (match_operand:VMMX2 2 "register_operand"  "y"))] UNSPEC_WADDC))]
  "TARGET_REALLY_IWMMXT"
  "wadd<MMX_char>c%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "iwmmxt_avg4"
[(set (match_operand:V8QI                                 0 "register_operand" "=y")
      (truncate:V8QI
        (vec_select:V8HI
	  (vec_merge:V8HI
	    (lshiftrt:V8HI
	      (plus:V8HI
	        (plus:V8HI
		  (plus:V8HI
	            (plus:V8HI
		      (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
		      (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
		    (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
		                     (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
				                (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
		  (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
		                   (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
				              (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
	        (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)
	                            (const_int 1) (const_int 1) (const_int 1) (const_int 1)]))
	      (const_int 2))
	    (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
	                        (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
	    (const_int 254))
	  (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
	             (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
  "TARGET_REALLY_IWMMXT"
  "wavg4%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg4")]
)

(define_insn "iwmmxt_avg4r"
  [(set (match_operand:V8QI                                   0 "register_operand" "=y")
	(truncate:V8QI
	  (vec_select:V8HI
	    (vec_merge:V8HI
	      (lshiftrt:V8HI
	        (plus:V8HI
		  (plus:V8HI
		    (plus:V8HI
		      (plus:V8HI
		        (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
		        (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
		      (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
		                       (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
				                  (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
		    (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
		                     (parallel [(const_int 7) (const_int 0) (const_int 1) (const_int 2)
				                (const_int 3) (const_int 4) (const_int 5) (const_int 6)])))
		  (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
		                      (const_int 2) (const_int 2) (const_int 2) (const_int 2)]))
	        (const_int 2))
	      (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)
	                          (const_int 0) (const_int 0) (const_int 0) (const_int 0)])
	      (const_int 254))
	    (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
	               (const_int 5) (const_int 6) (const_int 7) (const_int 0)]))))]
  "TARGET_REALLY_IWMMXT"
  "wavg4r%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg4")]
)

(define_insn "iwmmxt_wmaddsx"
  [(set (match_operand:V2SI                                        0 "register_operand" "=y")
	(plus:V2SI
	  (mult:V2SI
	    (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)]))
	    (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                     (parallel [(const_int 0) (const_int 2)])))
	  (mult:V2SI
	    (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
	                     (parallel [(const_int 0) (const_int 2)]))
	    (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
	                     (parallel [(const_int 1) (const_int 3)])))))]
 "TARGET_REALLY_IWMMXT"
  "wmaddsx%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
	(set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_wmaddux"
  [(set (match_operand:V2SI                                        0 "register_operand" "=y")
	(plus:V2SI
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                     (parallel [(const_int 0) (const_int 2)])))
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
	                     (parallel [(const_int 0) (const_int 2)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
	                     (parallel [(const_int 1) (const_int 3)])))))]
  "TARGET_REALLY_IWMMXT"
  "wmaddux%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_wmaddsn"
 [(set (match_operand:V2SI                                     0 "register_operand" "=y")
    (minus:V2SI
      (mult:V2SI
        (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                 (parallel [(const_int 0) (const_int 2)]))
        (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                 (parallel [(const_int 0) (const_int 2)])))
      (mult:V2SI
        (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
	                 (parallel [(const_int 1) (const_int 3)]))
        (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
	                 (parallel [(const_int 1) (const_int 3)])))))]
 "TARGET_REALLY_IWMMXT"
 "wmaddsn%?\\t%0, %1, %2"
 [(set_attr "predicable" "yes")
  (set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_wmaddun"
  [(set (match_operand:V2SI                                        0 "register_operand" "=y")
	(minus:V2SI
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                     (parallel [(const_int 0) (const_int 2)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                     (parallel [(const_int 0) (const_int 2)])))
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
	                     (parallel [(const_int 1) (const_int 3)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
	                     (parallel [(const_int 1) (const_int 3)])))))]
  "TARGET_REALLY_IWMMXT"
  "wmaddun%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_wmulwsm"
  [(set (match_operand:V2SI                         0 "register_operand" "=y")
	(truncate:V2SI
	  (ashiftrt:V2DI
	    (mult:V2DI
	      (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	      (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
	    (const_int 32))))]
  "TARGET_REALLY_IWMMXT"
  "wmulwsm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmulw")]
)

(define_insn "iwmmxt_wmulwum"
  [(set (match_operand:V2SI                         0 "register_operand" "=y")
	(truncate:V2SI
          (lshiftrt:V2DI
	    (mult:V2DI
	      (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	      (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
	    (const_int 32))))]
  "TARGET_REALLY_IWMMXT"
  "wmulwum%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmulw")]
)

(define_insn "iwmmxt_wmulsmr"
  [(set (match_operand:V4HI                           0 "register_operand" "=y")
	(truncate:V4HI
	  (ashiftrt:V4SI
	    (plus:V4SI
	      (mult:V4SI
	        (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
		(sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	      (const_vector:V4SI [(const_int 32768)
	                          (const_int 32768)
				  (const_int 32768)]))
	    (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulsmr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "iwmmxt_wmulumr"
  [(set (match_operand:V4HI                           0 "register_operand" "=y")
	(truncate:V4HI
	  (lshiftrt:V4SI
	    (plus:V4SI
	      (mult:V4SI
	        (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
		(zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	      (const_vector:V4SI [(const_int 32768)
				  (const_int 32768)
				  (const_int 32768)
				  (const_int 32768)]))
	  (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulumr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "iwmmxt_wmulwsmr"
  [(set (match_operand:V2SI                           0 "register_operand" "=y")
	(truncate:V2SI
	  (ashiftrt:V2DI
	    (plus:V2DI
	      (mult:V2DI
	        (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
		(sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
	      (const_vector:V2DI [(const_int 2147483648)
				  (const_int 2147483648)]))
	    (const_int 32))))]
  "TARGET_REALLY_IWMMXT"
  "wmulwsmr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "iwmmxt_wmulwumr"
  [(set (match_operand:V2SI                           0 "register_operand" "=y")
	(truncate:V2SI
	  (lshiftrt:V2DI
	    (plus:V2DI
	      (mult:V2DI
	        (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
		(zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
	      (const_vector:V2DI [(const_int 2147483648)
			          (const_int 2147483648)]))
	    (const_int 32))))]
  "TARGET_REALLY_IWMMXT"
  "wmulwumr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmulw")]
)

(define_insn "iwmmxt_wmulwl"
  [(set (match_operand:V2SI   0 "register_operand" "=y")
        (mult:V2SI
          (match_operand:V2SI 1 "register_operand" "y")
	  (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmulwl%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmulw")]
)

(define_insn "iwmmxt_wqmulm"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULM))]
  "TARGET_REALLY_IWMMXT"
  "wqmulm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmulm")]
)

(define_insn "iwmmxt_wqmulwm"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
	(unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
		      (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWM))]
  "TARGET_REALLY_IWMMXT"
  "wqmulwm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmulwm")]
)

(define_insn "iwmmxt_wqmulmr"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WQMULMR))]
  "TARGET_REALLY_IWMMXT"
  "wqmulmr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmulm")]
)

(define_insn "iwmmxt_wqmulwmr"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
		      (match_operand:V2SI 2 "register_operand" "y")] UNSPEC_WQMULWMR))]
  "TARGET_REALLY_IWMMXT"
  "wqmulwmr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmulwm")]
)

(define_insn "iwmmxt_waddbhusm"
  [(set (match_operand:V8QI                          0 "register_operand" "=y")
	(vec_concat:V8QI
	  (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])
	  (us_truncate:V4QI
	    (ss_plus:V4HI
	      (match_operand:V4HI                    1 "register_operand" "y")
	      (zero_extend:V4HI
	        (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
	                         (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)])))))))]
  "TARGET_REALLY_IWMMXT"
  "waddbhusm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "waddbhus")]
)

(define_insn "iwmmxt_waddbhusl"
  [(set (match_operand:V8QI                          0 "register_operand" "=y")
	(vec_concat:V8QI
	  (us_truncate:V4QI
	    (ss_plus:V4HI
	      (match_operand:V4HI                    1 "register_operand" "y")
	      (zero_extend:V4HI
		(vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
		                 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))))
	  (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)])))]
  "TARGET_REALLY_IWMMXT"
  "waddbhusl%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "waddbhus")]
)

(define_insn "iwmmxt_wqmiabb"
  [(set (match_operand:V2SI	                             0 "register_operand" "=y")
	(unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
		      (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
		      (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
		      (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
		      (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
  "TARGET_REALLY_IWMMXT"
  "wqmiabb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiabt"
  [(set (match_operand:V2SI	                             0 "register_operand" "=y")
	(unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
	              (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
		      (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
		      (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
		      (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
  "TARGET_REALLY_IWMMXT"
  "wqmiabt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiatb"
  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
	              (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
	              (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
	              (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
	              (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxy))]
  "TARGET_REALLY_IWMMXT"
  "wqmiatb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiatt"
  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
	              (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
	              (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
	              (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
	              (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxy))]
  "TARGET_REALLY_IWMMXT"
  "wqmiatt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiabbn"
  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
                      (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
	              (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
	              (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
	              (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
  "TARGET_REALLY_IWMMXT"
  "wqmiabbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiabtn"
  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
                      (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 0))
	              (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 32))
	              (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
	              (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
  "TARGET_REALLY_IWMMXT"
  "wqmiabtn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiatbn"
  [(set (match_operand:V2SI                                  0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
                      (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
	              (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
	              (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 0))
	              (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 32))] UNSPEC_WQMIAxyn))]
  "TARGET_REALLY_IWMMXT"
  "wqmiatbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wqmiattn"
 [(set (match_operand:V2SI                                  0 "register_operand" "=y")
       (unspec:V2SI [(match_operand:V2SI                    1 "register_operand" "0")
                     (zero_extract:V4HI (match_operand:V4HI 2 "register_operand" "y") (const_int 16) (const_int 16))
	             (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int 48))
	             (zero_extract:V4HI (match_operand:V4HI 3 "register_operand" "y") (const_int 16) (const_int 16))
	             (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int 48))] UNSPEC_WQMIAxyn))]
  "TARGET_REALLY_IWMMXT"
  "wqmiattn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wqmiaxy")]
)

(define_insn "iwmmxt_wmiabb"
  [(set	(match_operand:DI	                          0 "register_operand" "=y")
	(plus:DI (match_operand:DI	                  1 "register_operand" "0")
		 (plus:DI
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				      (parallel [(const_int 0)])))
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				      (parallel [(const_int 0)]))))
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_dup 2)
			              (parallel [(const_int 2)])))
		     (sign_extend:DI
		       (vec_select:HI (match_dup 3)
				      (parallel [(const_int 2)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiabb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiabt"
  [(set	(match_operand:DI	                          0 "register_operand" "=y")
	(plus:DI (match_operand:DI	                  1 "register_operand" "0")
		 (plus:DI
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				      (parallel [(const_int 0)])))
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				      (parallel [(const_int 1)]))))
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_dup 2)
				      (parallel [(const_int 2)])))
		     (sign_extend:DI
		       (vec_select:HI (match_dup 3)
				      (parallel [(const_int 3)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiabt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiatb"
  [(set	(match_operand:DI	                          0 "register_operand" "=y")
	(plus:DI (match_operand:DI	                  1 "register_operand" "0")
		 (plus:DI
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				      (parallel [(const_int 1)])))
		     (sign_extend:DI
		       (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				      (parallel [(const_int 0)]))))
		   (mult:DI
		     (sign_extend:DI
		       (vec_select:HI (match_dup 2)
				      (parallel [(const_int 3)])))
		     (sign_extend:DI
		       (vec_select:HI (match_dup 3)
				      (parallel [(const_int 2)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiatb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiatt"
  [(set	(match_operand:DI	                   0 "register_operand" "=y")
        (plus:DI (match_operand:DI	           1 "register_operand" "0")
          (plus:DI
            (mult:DI
              (sign_extend:DI
                (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
	                       (parallel [(const_int 1)])))
	      (sign_extend:DI
	        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
	                       (parallel [(const_int 1)]))))
            (mult:DI
	      (sign_extend:DI
                (vec_select:HI (match_dup 2)
	                       (parallel [(const_int 3)])))
              (sign_extend:DI
                (vec_select:HI (match_dup 3)
	                       (parallel [(const_int 3)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiatt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiabbn"
  [(set	(match_operand:DI	                           0 "register_operand" "=y")
	(minus:DI (match_operand:DI	                   1 "register_operand" "0")
		  (plus:DI
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				       (parallel [(const_int 0)])))
		      (sign_extend:DI
		        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				       (parallel [(const_int 0)]))))
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_dup 2)
				       (parallel [(const_int 2)])))
		      (sign_extend:DI
		        (vec_select:HI (match_dup 3)
				       (parallel [(const_int 2)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiabbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiabtn"
  [(set	(match_operand:DI	                           0 "register_operand" "=y")
	(minus:DI (match_operand:DI	                   1 "register_operand" "0")
		  (plus:DI
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				       (parallel [(const_int 0)])))
		      (sign_extend:DI
		        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				       (parallel [(const_int 1)]))))
		    (mult:DI
		      (sign_extend:DI
		        (vec_select:HI (match_dup 2)
				       (parallel [(const_int 2)])))
		      (sign_extend:DI
			(vec_select:HI (match_dup 3)
				       (parallel [(const_int 3)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiabtn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiatbn"
  [(set (match_operand:DI	                           0 "register_operand" "=y")
	(minus:DI (match_operand:DI	                   1 "register_operand" "0")
		  (plus:DI
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				       (parallel [(const_int 1)])))
		      (sign_extend:DI
		        (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				       (parallel [(const_int 0)]))))
		    (mult:DI
		      (sign_extend:DI
		        (vec_select:HI (match_dup 2)
				       (parallel [(const_int 3)])))
		      (sign_extend:DI
			(vec_select:HI (match_dup 3)
				       (parallel [(const_int 2)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiatbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiattn"
  [(set (match_operand:DI	                           0 "register_operand" "=y")
	(minus:DI (match_operand:DI	                   1 "register_operand" "0")
		  (plus:DI
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
				       (parallel [(const_int 1)])))
		      (sign_extend:DI
			(vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
				       (parallel [(const_int 1)]))))
		    (mult:DI
		      (sign_extend:DI
			(vec_select:HI (match_dup 2)
				       (parallel [(const_int 3)])))
		      (sign_extend:DI
			(vec_select:HI (match_dup 3)
				       (parallel [(const_int 3)])))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiattn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiaxy")]
)

(define_insn "iwmmxt_wmiawbb"
  [(set (match_operand:DI	0 "register_operand" "=y")
	(plus:DI
	  (match_operand:DI      1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawbb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawbt"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(plus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawbt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawtb"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(plus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawtb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawtt"
[(set (match_operand:DI	                                     0 "register_operand" "=y")
      (plus:DI
	(match_operand:DI                                    1 "register_operand" "0")
	(mult:DI
	  (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
	  (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawtt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawbbn"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(minus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawbbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawbtn"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(minus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 0)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawbtn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawtbn"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(minus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 0)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawtbn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmiawttn"
  [(set (match_operand:DI	                               0 "register_operand" "=y")
	(minus:DI
	  (match_operand:DI                                    1 "register_operand" "0")
	  (mult:DI
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 2 "register_operand" "y") (parallel [(const_int 1)])))
	    (sign_extend:DI (vec_select:SI (match_operand:V2SI 3 "register_operand" "y") (parallel [(const_int 1)]))))))]
  "TARGET_REALLY_IWMMXT"
  "wmiawttn%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmiawxy")]
)

(define_insn "iwmmxt_wmerge"
  [(set (match_operand:DI         0 "register_operand" "=y")
	(ior:DI
	  (ashift:DI
	    (match_operand:DI     2 "register_operand" "y")
	    (minus:SI
	      (const_int 64)
	      (mult:SI
	        (match_operand:SI 3 "immediate_operand" "i")
		(const_int 8))))
	  (lshiftrt:DI
	    (ashift:DI
	      (match_operand:DI   1 "register_operand" "y")
	      (mult:SI
	        (match_dup 3)
		(const_int 8)))
	    (mult:SI
	      (match_dup 3)
	      (const_int 8)))))]
  "TARGET_REALLY_IWMMXT"
  "wmerge%?\\t%0, %1, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmerge")]
)

(define_insn "iwmmxt_tandc<mode>3"
  [(set (reg:CC CC_REGNUM)
	(subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0))
   (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)]
  "TARGET_REALLY_IWMMXT"
  "tandc<MMX_char>%?\\t r15"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tandc")]
)

(define_insn "iwmmxt_torc<mode>3"
  [(set (reg:CC CC_REGNUM)
	(subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0))
   (unspec:CC [(reg:SI 15)] UNSPEC_TORC)]
  "TARGET_REALLY_IWMMXT"
  "torc<MMX_char>%?\\t r15"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "torc")]
)

(define_insn "iwmmxt_torvsc<mode>3"
  [(set (reg:CC CC_REGNUM)
	(subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0))
   (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)]
  "TARGET_REALLY_IWMMXT"
  "torvsc<MMX_char>%?\\t r15"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "torvsc")]
)

(define_insn "iwmmxt_textrc<mode>3"
  [(set (reg:CC CC_REGNUM)
	(subreg:CC (unspec:VMMX [(const_int 0)
		                 (match_operand:SI 0 "immediate_operand" "i")] UNSPEC_TEXTRC) 0))
   (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)]
  "TARGET_REALLY_IWMMXT"
  "textrc<MMX_char>%?\\t r15, %0"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrc")]
)




;; ??? This file needs auditing for thumb2
;; Patterns for the Intel Wireless MMX technology architecture.
;; Copyright (C) 2003, 2004, 2005, 2007, 2008, 2010, 2012
;; Free Software Foundation, Inc.
;; Contributed by Red Hat.


;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Register numbers
(define_constants
  [(WCGR0           43)
   (WCGR1           44)
   (WCGR2           45)
   (WCGR3           46)
  ]
)

(define_insn "tbcstv8qi"
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
        (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstb%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tbcst")]
)

(define_insn "tbcstv4hi"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
        (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcsth%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tbcst")]
)

(define_insn "tbcstv2si"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
        (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tbcst")]
)

(define_insn "iwmmxt_iordi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")

   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")
   (set_attr "wtype" "wor,none,none")]
)

(define_insn "iwmmxt_xordi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")

   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")
   (set_attr "wtype" "wxor,none,none")]
)

(define_insn "iwmmxt_anddi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")

   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")
   (set_attr "wtype" "wand,none,none")]
)

(define_insn "iwmmxt_nanddi3"
  [(set (match_operand:DI                 0 "register_operand" "=y")

		(not:DI (match_operand:DI 2 "register_operand"  "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wandn%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wandn")]
)

(define_insn "*iwmmxt_arm_movdi"
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,yr,y,yrUy,*w, r,*w,*w, *Uv")
        (match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,r,y,yr,y,yrUy,y, r,*w,*w,*Uvi,*w"))]
  "TARGET_REALLY_IWMMXT
   && (   register_operand (operands[0], DImode)
       || register_operand (operands[1], DImode))"
  "*
{
  switch (which_alternative)
    {
    default:
      return output_move_double (operands, true, NULL);
    case 0:
    case 1:
    case 2:
      return \"#\";
    case 3: case 4:
      return output_move_double (operands, true, NULL);
    case 5:
      return \"wmov%?\\t%0,%1\";
    case 6:
      return \"tmcrr%?\\t%0,%Q1,%R1\";
    case 7:
      return \"tmrrc%?\\t%Q0,%R0,%1\";
    case 8:
      return \"wldrd%?\\t%0,%1\";
    case 9:
      return \"wstrd%?\\t%1,%0\";
    case 10:
      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
    case 11:
      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
    case 12:
      if (TARGET_VFP_SINGLE)
	return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
      else
	return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
    case 13: case 14:
      return output_move_vfp (operands);
    default:
      gcc_unreachable ();
    }
  "
  [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
                              (eq_attr "alternative" "1") (const_int 12)
                              (eq_attr "alternative" "2") (const_int 16)
                              (eq_attr "alternative" "12")
                               (if_then_else
                                 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
                                 (const_int 8)
                                 (const_int 4))]
                              (const_int 4)))
   (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
   (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
   (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")
   (set_attr "wtype" "*,*,*,*,*,wmov,tmcrr,tmrrc,wldr,wstr,*,*,*,*,*")]
)

(define_insn "*iwmmxt_movsi_insn"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t  ,*Uv")
	(match_operand:SI 1 "general_operand"      " rk,I,K,j,mi,rk,r,z,Uy,  z, r,*t,*t,*Uvi, *t"))]
  "TARGET_REALLY_IWMMXT
   && (   register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "*
   switch (which_alternative)
     {
     case 0: return \"mov\\t%0, %1\";
     case 1: return \"mov\\t%0, %1\";
     case 2: return \"mvn\\t%0, #%B1\";
     case 3: return \"movw\\t%0, %1\";
     case 4: return \"ldr\\t%0, %1\";
     case 5: return \"str\\t%1, %0\";
     case 6: return \"tmcr\\t%0, %1\";
     case 7: return \"tmrc\\t%0, %1\";
     case 8: return arm_output_load_gr (operands);
     case 9: return \"wstrw\\t%1, %0\";
     case 10:return \"fmsr\\t%0, %1\";
     case 11:return \"fmrs\\t%0, %1\";
     case 12:return \"fcpys\\t%0, %1\\t%@ int\";
     case 13: case 14:
       return output_move_vfp (operands);
     default:
       gcc_unreachable ();
     }"
  [(set_attr "type"           "*,*,*,*,load1,store1,*,*,*,*,r_2_f,f_2_r,fcpys,f_loads,f_stores")
   (set_attr "length"         "*,*,*,*,*,        *,*,*,  16,     *,*,*,*,*,*")
   (set_attr "pool_range"     "*,*,*,*,4096,     *,*,*,1024,     *,*,*,*,1020,*")
   (set_attr "neg_pool_range" "*,*,*,*,4084,     *,*,*,   *,  1012,*,*,*,1008,*")
   ;; Note - the "predicable" attribute is not allowed to have alternatives.
   ;; Since the wSTRw wCx instruction is not predicable, we cannot support
   ;; predicating any of the alternatives in this template.  Instead,

   ;; Also - we have to pretend that these insns clobber the condition code
   ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
   ;; them.
   (set_attr "conds" "clob")
   (set_attr "wtype" "*,*,*,*,*,*,tmcr,tmrc,wldr,wstr,*,*,*,*,*")]
)

;; Because iwmmxt_movsi_insn is not predicable, we provide the

   }"
  [(set_attr "predicable" "yes")
   (set_attr "length"         "4,     4,   4,4,4,8,   8,8")
   (set_attr "type"           "*,*,*,*,*,*,load1,store1")
   (set_attr "pool_range"     "*,     *, 256,*,*,*, 256,*")
   (set_attr "neg_pool_range" "*,     *, 244,*,*,*, 244,*")
   (set_attr "wtype"          "wmov,wstr,wldr,tmrrc,tmcrr,*,*,*")]
)

(define_expand "iwmmxt_setwcgr0"
  [(set (reg:SI WCGR0)
	(match_operand:SI 0 "register_operand"  ""))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_setwcgr1"
  [(set (reg:SI WCGR1)
	(match_operand:SI 0 "register_operand"  ""))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_setwcgr2"
  [(set (reg:SI WCGR2)
	(match_operand:SI 0 "register_operand"  ""))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_setwcgr3"
  [(set (reg:SI WCGR3)
	(match_operand:SI 0 "register_operand"  ""))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_getwcgr0"
  [(set (match_operand:SI 0 "register_operand"  "")
        (reg:SI WCGR0))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_getwcgr1"
  [(set (match_operand:SI 0 "register_operand"  "")
        (reg:SI WCGR1))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_getwcgr2"
  [(set (match_operand:SI 0 "register_operand"  "")
        (reg:SI WCGR2))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_expand "iwmmxt_getwcgr3"
  [(set (match_operand:SI 0 "register_operand"  "")
        (reg:SI WCGR3))]
  "TARGET_REALLY_IWMMXT"
  {}
)

(define_insn "*and<mode>3_iwmmxt"
  [(set (match_operand:VMMX           0 "register_operand" "=y")
        (and:VMMX (match_operand:VMMX 1 "register_operand"  "y")
	          (match_operand:VMMX 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wand\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wand")]
)

(define_insn "*ior<mode>3_iwmmxt"
  [(set (match_operand:VMMX           0 "register_operand" "=y")
        (ior:VMMX (match_operand:VMMX 1 "register_operand"  "y")
	          (match_operand:VMMX 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wor\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wor")]
)

(define_insn "*xor<mode>3_iwmmxt"
  [(set (match_operand:VMMX           0 "register_operand" "=y")
        (xor:VMMX (match_operand:VMMX 1 "register_operand"  "y")
	          (match_operand:VMMX 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wxor\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wxor")]
)


;; Vector add/subtract

(define_insn "*add<mode>3_iwmmxt"
  [(set (match_operand:VMMX            0 "register_operand" "=y")
        (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
	           (match_operand:VMMX 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wadd<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "ssaddv8qi3"
  [(set (match_operand:V8QI               0 "register_operand" "=y")

		      (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddbss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "ssaddv4hi3"
  [(set (match_operand:V4HI               0 "register_operand" "=y")

		      (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "ssaddv2si3"
  [(set (match_operand:V2SI               0 "register_operand" "=y")

		      (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "usaddv8qi3"
  [(set (match_operand:V8QI               0 "register_operand" "=y")

		      (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddbus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "usaddv4hi3"
  [(set (match_operand:V4HI               0 "register_operand" "=y")

		      (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "usaddv2si3"
  [(set (match_operand:V2SI               0 "register_operand" "=y")

		      (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wadd")]
)

(define_insn "*sub<mode>3_iwmmxt"
  [(set (match_operand:VMMX             0 "register_operand" "=y")

		    (match_operand:VMMX 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsub<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "sssubv8qi3"
  [(set (match_operand:V8QI                0 "register_operand" "=y")

		       (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubbss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "sssubv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")

		       (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "sssubv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")

		       (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "ussubv8qi3"
  [(set (match_operand:V8QI                0 "register_operand" "=y")

		       (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubbus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "ussubv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")

		       (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "ussubv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")

		       (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsub")]
)

(define_insn "*mulv4hi3_iwmmxt"
  [(set (match_operand:V4HI            0 "register_operand" "=y")

		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmulul%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "smulv4hi3_highpart"
  [(set (match_operand:V4HI 0 "register_operand" "=y")
	  (truncate:V4HI
	    (lshiftrt:V4SI
	      (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	      (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulsm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "umulv4hi3_highpart"
  [(set (match_operand:V4HI 0 "register_operand" "=y")
	  (truncate:V4HI
	    (lshiftrt:V4SI
	      (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	      (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulum%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmul")]
)

(define_insn "iwmmxt_wmacs"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:DI   1 "register_operand" "0")
	            (match_operand:V4HI 2 "register_operand" "y")
	            (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
  "TARGET_REALLY_IWMMXT"
  "wmacs%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmac")]
)

(define_insn "iwmmxt_wmacsz"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
	            (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
  "TARGET_REALLY_IWMMXT"
  "wmacsz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmac")]
)

(define_insn "iwmmxt_wmacu"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:DI   1 "register_operand" "0")
	            (match_operand:V4HI 2 "register_operand" "y")
	            (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
  "TARGET_REALLY_IWMMXT"
  "wmacu%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmac")]
)

(define_insn "iwmmxt_wmacuz"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
	            (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
  "TARGET_REALLY_IWMMXT"
  "wmacuz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmac")]
)

;; Same as xordi3, but don't show input operands so that we don't think
;; they are live.

        (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wxor")]
)

;; Seems like cse likes to generate these, so we have to support them.

(define_insn "iwmmxt_clrv8qi"
  [(set (match_operand:V8QI 0 "s_register_operand" "=y")
        (const_vector:V8QI [(const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wxor")]
)

(define_insn "iwmmxt_clrv4hi"
  [(set (match_operand:V4HI 0 "s_register_operand" "=y")
        (const_vector:V4HI [(const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wxor")]
)

(define_insn "iwmmxt_clrv2si"
  [(set (match_operand:V2SI 0 "register_operand" "=y")
        (const_vector:V2SI [(const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wxor")]
)

;; Unsigned averages/sum of absolute differences

(define_insn "iwmmxt_uavgrndv8qi3"
  [(set (match_operand:V8QI                                    0 "register_operand" "=y")
        (truncate:V8QI
	  (lshiftrt:V8HI
	    (plus:V8HI
	      (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	                 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
	      (const_vector:V8HI [(const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)]))
	    (const_int 1))))]
  "TARGET_REALLY_IWMMXT"
  "wavg2br%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg2")]
)

(define_insn "iwmmxt_uavgrndv4hi3"
  [(set (match_operand:V4HI                                    0 "register_operand" "=y")
        (truncate:V4HI
	  (lshiftrt:V4SI
            (plus:V4SI
	      (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	      (const_vector:V4SI [(const_int 1)
	                          (const_int 1)
	                          (const_int 1)
	                          (const_int 1)]))
	    (const_int 1))))]
  "TARGET_REALLY_IWMMXT"
  "wavg2hr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg2")]
)

(define_insn "iwmmxt_uavgv8qi3"
  [(set (match_operand:V8QI                                  0 "register_operand" "=y")
        (truncate:V8QI
	  (lshiftrt:V8HI
	    (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	               (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
	    (const_int 1))))]
  "TARGET_REALLY_IWMMXT"
  "wavg2b%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg2")]
)

(define_insn "iwmmxt_uavgv4hi3"
  [(set (match_operand:V4HI                                  0 "register_operand" "=y")
        (truncate:V4HI
	  (lshiftrt:V4SI
	    (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	               (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	    (const_int 1))))]
  "TARGET_REALLY_IWMMXT"
  "wavg2h%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wavg2")]
)
  [(set (match_operand:V8QI                       0 "register_operand" "=y")
        (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
			      (match_operand:V8QI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "psadbw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])


;; Insert/extract/shuffle

(define_insn "iwmmxt_tinsrb"
  [(set (match_operand:V8QI                0 "register_operand" "=y")
        (vec_merge:V8QI
	  (vec_duplicate:V8QI
	    (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
	  (match_operand:V8QI              1 "register_operand"     "0")
	  (match_operand:SI                3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "*
   {
     return arm_output_iwmmxt_tinsr (operands);
   }
   "
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tinsr")]
)

(define_insn "iwmmxt_tinsrh"
  [(set (match_operand:V4HI                0 "register_operand"    "=y")
        (vec_merge:V4HI
          (vec_duplicate:V4HI
            (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
	  (match_operand:V4HI              1 "register_operand"     "0")
	  (match_operand:SI                3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "*
   {
     return arm_output_iwmmxt_tinsr (operands);
   }
   "
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tinsr")]
)

(define_insn "iwmmxt_tinsrw"
  [(set (match_operand:V2SI   0 "register_operand"    "=y")
        (vec_merge:V2SI
          (vec_duplicate:V2SI
            (match_operand:SI 2 "nonimmediate_operand" "r"))
          (match_operand:V2SI 1 "register_operand"     "0")
          (match_operand:SI   3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "*
   {
     return arm_output_iwmmxt_tinsr (operands);
   }
   "
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tinsr")]
)

(define_insn "iwmmxt_textrmub"
  [(set (match_operand:SI                                   0 "register_operand" "=r")
        (zero_extend:SI (vec_select:QI (match_operand:V8QI  1 "register_operand" "y")
		                       (parallel
				         [(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrm")]
)

(define_insn "iwmmxt_textrmsb"
  [(set (match_operand:SI                                   0 "register_operand" "=r")
        (sign_extend:SI (vec_select:QI (match_operand:V8QI  1 "register_operand" "y")
				       (parallel
				         [(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrm")]
)

(define_insn "iwmmxt_textrmuh"
  [(set (match_operand:SI                                   0 "register_operand" "=r")
        (zero_extend:SI (vec_select:HI (match_operand:V4HI  1 "register_operand" "y")
				       (parallel
				         [(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrm")]
)

(define_insn "iwmmxt_textrmsh"
  [(set (match_operand:SI                                   0 "register_operand" "=r")
        (sign_extend:SI (vec_select:HI (match_operand:V4HI  1 "register_operand" "y")
				       (parallel
				         [(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrm")]
)

;; There are signed/unsigned variants of this instruction, but they are
;; pointless.

		       (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
  "TARGET_REALLY_IWMMXT"
  "textrmsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "textrm")]
)

(define_insn "iwmmxt_wshufh"
  [(set (match_operand:V4HI               0 "register_operand" "=y")

		      (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
  "TARGET_REALLY_IWMMXT"
  "wshufh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wshufh")]
)

;; Mask-generating comparisons
;;

;; into the entire destination vector, (with the '1' going into the least
;; significant element of the vector).  This is not how these instructions
;; behave.
;;
;; Unfortunately the current patterns are illegal.  They are SET insns
;; without a SET in them.  They work in most cases for ordinary code
;; generation, but there are circumstances where they can cause gcc to fail.
;; XXX - FIXME.

(define_insn "eqv8qi3"
  [(set (match_operand:V8QI                        0 "register_operand" "=y")
	(unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
	                       (match_operand:V8QI 2 "register_operand"  "y")]
	                      VUNSPEC_WCMP_EQ))]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpeq")]
)

(define_insn "eqv4hi3"
  [(set (match_operand:V4HI                        0 "register_operand" "=y")
	(unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
		               (match_operand:V4HI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_EQ))]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpeq")]
)

(define_insn "eqv2si3"
  [(set (match_operand:V2SI    0 "register_operand" "=y")
	(unspec_volatile:V2SI
	  [(match_operand:V2SI 1 "register_operand"  "y")
	   (match_operand:V2SI 2 "register_operand"  "y")]
           VUNSPEC_WCMP_EQ))]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpeq")]
)

(define_insn "gtuv8qi3"
  [(set (match_operand:V8QI                        0 "register_operand" "=y")
	(unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
	                       (match_operand:V8QI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_GTU))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

(define_insn "gtuv4hi3"
  [(set (match_operand:V4HI                        0 "register_operand" "=y")
        (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
                               (match_operand:V4HI 2 "register_operand"  "y")]
                               VUNSPEC_WCMP_GTU))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

(define_insn "gtuv2si3"
  [(set (match_operand:V2SI                        0 "register_operand" "=y")
	(unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand"  "y")
	                       (match_operand:V2SI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_GTU))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtuw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

(define_insn "gtv8qi3"
  [(set (match_operand:V8QI                        0 "register_operand" "=y")
	(unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand"  "y")
	                       (match_operand:V8QI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_GT))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

(define_insn "gtv4hi3"
  [(set (match_operand:V4HI                        0 "register_operand" "=y")
	(unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand"  "y")
	                       (match_operand:V4HI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_GT))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

(define_insn "gtv2si3"
  [(set (match_operand:V2SI                        0 "register_operand" "=y")
	(unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand"  "y")
	                       (match_operand:V2SI 2 "register_operand"  "y")]
	                       VUNSPEC_WCMP_GT))]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wcmpgt")]
)

;; Max/min insns


		   (match_operand:VMMX 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxs<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmax")]
)

(define_insn "*umax<mode>3_iwmmxt"
  [(set (match_operand:VMMX            0 "register_operand" "=y")

		   (match_operand:VMMX 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxu<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmax")]
)

(define_insn "*smin<mode>3_iwmmxt"
  [(set (match_operand:VMMX            0 "register_operand" "=y")

		   (match_operand:VMMX 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmins<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmin")]
)

(define_insn "*umin<mode>3_iwmmxt"
  [(set (match_operand:VMMX            0 "register_operand" "=y")

		   (match_operand:VMMX 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminu<MMX_char>%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmin")]
)

;; Pack/unpack insns.

(define_insn "iwmmxt_wpackhss"
  [(set (match_operand:V8QI                     0 "register_operand" "=y")
	(vec_concat:V8QI
	  (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
	  (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wpackwss"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
        (vec_concat:V4HI
	  (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
	  (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wpackdss"
  [(set (match_operand:V2SI                 0 "register_operand" "=y")
	(vec_concat:V2SI
	  (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
	  (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackdss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wpackhus"
  [(set (match_operand:V8QI                     0 "register_operand" "=y")
	(vec_concat:V8QI
	  (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
	  (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wpackwus"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
	(vec_concat:V4HI
	  (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
	  (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wpackdus"
  [(set (match_operand:V2SI                 0 "register_operand" "=y")
	(vec_concat:V2SI
	  (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
	  (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackdus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wpack")]
)

(define_insn "iwmmxt_wunpckihb"
  [(set (match_operand:V8QI                                      0 "register_operand" "=y")
	(vec_merge:V8QI
	  (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
		           (parallel [(const_int 4)
			              (const_int 0)
			              (const_int 5)
			              (const_int 1)
			              (const_int 6)
			              (const_int 2)
			              (const_int 7)
			              (const_int 3)]))
          (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
			   (parallel [(const_int 0)
			              (const_int 4)
			              (const_int 1)
			              (const_int 5)
			              (const_int 2)
			              (const_int 6)
			              (const_int 3)
			              (const_int 7)]))
          (const_int 85)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckih")]
)

(define_insn "iwmmxt_wunpckihh"
  [(set (match_operand:V4HI                                      0 "register_operand" "=y")
	(vec_merge:V4HI
	  (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
		           (parallel [(const_int 2)
			              (const_int 0)
			              (const_int 3)
			              (const_int 1)]))
	  (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
		           (parallel [(const_int 0)
			              (const_int 2)
			              (const_int 1)
			              (const_int 3)]))
          (const_int 5)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckih")]
)

(define_insn "iwmmxt_wunpckihw"
  [(set (match_operand:V2SI                    0 "register_operand" "=y")
	(vec_merge:V2SI
	  (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
		           (parallel [(const_int 1)
		                      (const_int 0)]))
          (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
		           (parallel [(const_int 0)
			              (const_int 1)]))
          (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckih")]
)

(define_insn "iwmmxt_wunpckilb"
  [(set (match_operand:V8QI                                      0 "register_operand" "=y")
	(vec_merge:V8QI
	  (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
		           (parallel [(const_int 0)
			              (const_int 4)
			              (const_int 1)
			              (const_int 5)
		                      (const_int 2)
				      (const_int 6)
				      (const_int 3)
				      (const_int 7)]))
	  (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
		           (parallel [(const_int 4)
			              (const_int 0)
			              (const_int 5)
			              (const_int 1)
			              (const_int 6)
			              (const_int 2)
			              (const_int 7)
			              (const_int 3)]))
	  (const_int 85)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckil")]
)

(define_insn "iwmmxt_wunpckilh"
  [(set (match_operand:V4HI                                      0 "register_operand" "=y")
	(vec_merge:V4HI
	  (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
		           (parallel [(const_int 0)
			              (const_int 2)
			              (const_int 1)
			              (const_int 3)]))
	  (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
			   (parallel [(const_int 2)
			              (const_int 0)
			              (const_int 3)
			              (const_int 1)]))
	  (const_int 5)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckil")]
)

(define_insn "iwmmxt_wunpckilw"
  [(set (match_operand:V2SI                    0 "register_operand" "=y")
	(vec_merge:V2SI
	  (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
		           (parallel [(const_int 0)
				      (const_int 1)]))
	  (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
		           (parallel [(const_int 1)
			              (const_int 0)]))
	  (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckil")]
)

(define_insn "iwmmxt_wunpckehub"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
	(vec_select:V4HI
	  (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	  (parallel [(const_int 4) (const_int 5)
	             (const_int 6) (const_int 7)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehub%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckehuh"
  [(set (match_operand:V2SI                     0 "register_operand" "=y")
	(vec_select:V2SI
	  (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	  (parallel [(const_int 2) (const_int 3)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehuh%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckehuw"
  [(set (match_operand:DI                       0 "register_operand" "=y")
	(vec_select:DI
	  (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	  (parallel [(const_int 1)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehuw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckehsb"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
        (vec_select:V4HI
	  (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	  (parallel [(const_int 4) (const_int 5)
	             (const_int 6) (const_int 7)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsb%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckehsh"
  [(set (match_operand:V2SI                     0 "register_operand" "=y")
	(vec_select:V2SI
	  (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	  (parallel [(const_int 2) (const_int 3)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsh%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckehsw"
  [(set (match_operand:DI                       0 "register_operand" "=y")
	(vec_select:DI
	  (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	  (parallel [(const_int 1)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckeh")]
)

(define_insn "iwmmxt_wunpckelub"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
	(vec_select:V4HI
	  (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	  (parallel [(const_int 0) (const_int 1)
		     (const_int 2) (const_int 3)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelub%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

(define_insn "iwmmxt_wunpckeluh"
  [(set (match_operand:V2SI                     0 "register_operand" "=y")
	(vec_select:V2SI
	  (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	  (parallel [(const_int 0) (const_int 1)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckeluh%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

(define_insn "iwmmxt_wunpckeluw"
  [(set (match_operand:DI                       0 "register_operand" "=y")
	(vec_select:DI
	  (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	  (parallel [(const_int 0)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckeluw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

(define_insn "iwmmxt_wunpckelsb"
  [(set (match_operand:V4HI                     0 "register_operand" "=y")
	(vec_select:V4HI
	  (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
	  (parallel [(const_int 0) (const_int 1)
		     (const_int 2) (const_int 3)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsb%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

(define_insn "iwmmxt_wunpckelsh"
  [(set (match_operand:V2SI                     0 "register_operand" "=y")
	(vec_select:V2SI
	  (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	  (parallel [(const_int 0) (const_int 1)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsh%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

(define_insn "iwmmxt_wunpckelsw"
  [(set (match_operand:DI                       0 "register_operand" "=y")
        (vec_select:DI
	  (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
	  (parallel [(const_int 0)])))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wunpckel")]
)

;; Shifts

(define_insn "ror<mode>3"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		        (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
  "TARGET_REALLY_IWMMXT"
  "wrorhg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch  (which_alternative)
    {
    case 0:
      return \"wror<MMX_char>g%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wror, wror")]
)

(define_insn "ashr<mode>3_iwmmxt"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
			(match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch  (which_alternative)
    {
    case 0:
      return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsra, wsra")]
)

(define_insn "lshr<mode>3_iwmmxt"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
			(match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch  (which_alternative)
    {
    case 0:
      return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsrl, wsrl")]
)

(define_insn "ashl<mode>3_iwmmxt"
  [(set (match_operand:VSHFT               0 "register_operand" "=y,y")
        (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		      (match_operand:SI    2 "imm_or_reg_operand" "z,i")))]
  "TARGET_REALLY_IWMMXT"
  "wsll<MMX_char>g%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv4hi3_di"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrorh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv2si3_di"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrorw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rordi3_di"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(rotatert:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrord%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrv4hi3_di"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch  (which_alternative)
    {
    case 0:
      return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsll, wsll")]
)

(define_insn "ror<mode>3_di"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		        (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch (which_alternative)
    {
    case 0:
      return \"wror<MMX_char>%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wror, wror")]
)

(define_insn "ashr<mode>3_di"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		        (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch (which_alternative)
    {
    case 0:
      return \"wsra<MMX_char>%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsra, wsra")]
)

(define_insn "lshr<mode>3_di"
  [(set (match_operand:VSHFT                 0 "register_operand" "=y,y")
        (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		        (match_operand:DI    2 "register_operand" "y,i")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch (which_alternative)
    {
    case 0:
      return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsrl, wsrl")]
)

(define_insn "ashl<mode>3_di"
  [(set (match_operand:VSHFT               0 "register_operand" "=y,y")
        (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
		      (match_operand:DI    2 "imm_or_reg_operand" "y,i")))]
  "TARGET_REALLY_IWMMXT"
  "wsrld%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv4hi3_di"
  [(set (match_operand:V4HI              0 "register_operand" "=y")
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
		     (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsllh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv2si3_di"
  [(set (match_operand:V2SI              0 "register_operand" "=y")
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsllw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashldi3_di"
  [(set (match_operand:DI            0 "register_operand" "=y")
	(ashift:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:DI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "*
  switch (which_alternative)
    {
    case 0:
      return \"wsll<MMX_char>%?\\t%0, %1, %2\";
    case 1:
      return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
    default:
      gcc_unreachable ();
    }
  "
  [(set_attr "predicable" "yes")
   (set_attr "arch" "*, iwmmxt2")
   (set_attr "wtype" "wsll, wsll")]
)

(define_insn "iwmmxt_wmadds"
  [(set (match_operand:V2SI                                        0 "register_operand" "=y")
	(plus:V2SI
	  (mult:V2SI
	    (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)]))
	    (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)])))
	  (mult:V2SI
	    (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
	                     (parallel [(const_int 0) (const_int 2)]))
	    (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
	                     (parallel [(const_int 0) (const_int 2)])))))]
  "TARGET_REALLY_IWMMXT"
  "wmadds%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_wmaddu"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
	(plus:V2SI
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
	                     (parallel [(const_int 1) (const_int 3)])))
	  (mult:V2SI
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
	                     (parallel [(const_int 0) (const_int 2)]))
	    (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
	                     (parallel [(const_int 0) (const_int 2)])))))]
  "TARGET_REALLY_IWMMXT"
  "wmaddu%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wmadd")]
)

(define_insn "iwmmxt_tmia"
  [(set (match_operand:DI                     0 "register_operand" "=y")
	(plus:DI (match_operand:DI            1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			    (match_operand:SI 2 "register_operand" "r"))
			  (sign_extend:DI
			    (match_operand:SI 3 "register_operand" "r")))))]
  "TARGET_REALLY_IWMMXT"
  "tmia%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmia")]
)

(define_insn "iwmmxt_tmiaph"
  [(set (match_operand:DI                                    0 "register_operand" "=y")
	(plus:DI (match_operand:DI                           1 "register_operand" "0")
		 (plus:DI
		   (mult:DI (sign_extend:DI
			      (truncate:HI (match_operand:SI 2 "register_operand" "r")))
			    (sign_extend:DI
			      (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
		   (mult:DI (sign_extend:DI
			      (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
			    (sign_extend:DI
			      (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiaph%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmiaph")]
)

(define_insn "iwmmxt_tmiabb"
  [(set (match_operand:DI                                  0 "register_operand" "=y")
	(plus:DI (match_operand:DI                         1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			    (truncate:HI (match_operand:SI 2 "register_operand" "r")))
			  (sign_extend:DI
			    (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiabb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmiaxy")]
)

(define_insn "iwmmxt_tmiatb"
  [(set (match_operand:DI                         0 "register_operand" "=y")
	(plus:DI (match_operand:DI                1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			    (truncate:HI
			      (ashiftrt:SI
				(match_operand:SI 2 "register_operand" "r")
				(const_int 16))))
			  (sign_extend:DI
			    (truncate:HI
			      (match_operand:SI   3 "register_operand" "r"))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiatb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmiaxy")]
)

(define_insn "iwmmxt_tmiabt"
  [(set (match_operand:DI                         0 "register_operand" "=y")
	(plus:DI (match_operand:DI                1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			    (truncate:HI
			      (match_operand:SI   2 "register_operand" "r")))
			  (sign_extend:DI
			    (truncate:HI
			      (ashiftrt:SI
				(match_operand:SI 3 "register_operand" "r")
				(const_int 16)))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiabt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmiaxy")]
)

(define_insn "iwmmxt_tmiatt"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			    (truncate:HI
			      (ashiftrt:SI
				(match_operand:SI 2 "register_operand" "r")
				(const_int 16))))
			  (sign_extend:DI
			    (truncate:HI
			      (ashiftrt:SI
				(match_operand:SI 3 "register_operand" "r")
				(const_int 16)))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiatt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmiaxy")]
)
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
	(vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tbcsthi"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcsth%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tbcstsi"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmovmskb"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskb%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmovmsk")]
)

(define_insn "iwmmxt_tmovmskh"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskh%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmovmsk")]
)

(define_insn "iwmmxt_tmovmskw"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "tmovmsk")]
)

(define_insn "iwmmxt_waccb"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "waccb%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wacc")]
)

(define_insn "iwmmxt_wacch"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "wacch%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wacc")]
)

(define_insn "iwmmxt_waccw"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "waccw%?\\t%0, %1"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wacc")]
)

;; use unspec here to prevent 8 * imm to be optimized by cse
(define_insn "iwmmxt_waligni"
  [(set (match_operand:V8QI                                0 "register_operand" "=y")
	(unspec:V8QI [(subreg:V8QI
		        (ashiftrt:TI
		          (subreg:TI (vec_concat:V16QI
				       (match_operand:V8QI 1 "register_operand" "y")
				       (match_operand:V8QI 2 "register_operand" "y")) 0)
		          (mult:SI
		            (match_operand:SI              3 "immediate_operand" "i")
		            (const_int 8))) 0)] UNSPEC_WALIGNI))]
  "TARGET_REALLY_IWMMXT"
  "waligni%?\\t%0, %1, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "waligni")]
)

(define_insn "iwmmxt_walignr"
  [(set (match_operand:V8QI                           0 "register_operand" "=y")
	(subreg:V8QI (ashiftrt:TI
		       (subreg:TI (vec_concat:V16QI
				    (match_operand:V8QI 1 "register_operand" "y")
				    (match_operand:V8QI 2 "register_operand" "y")) 0)
		       (mult:SI
		         (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0))
		         (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "walignr%U3%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "walignr")]
)

(define_insn "iwmmxt_walignr0"
  [(set (match_operand:V8QI                           0 "register_operand" "=y")
	(subreg:V8QI (ashiftrt:TI
		       (subreg:TI (vec_concat:V16QI
				    (match_operand:V8QI 1 "register_operand" "y")
				    (match_operand:V8QI 2 "register_operand" "y")) 0)
		       (mult:SI
		         (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0))
		         (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "walignr0%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "walignr")]
)

(define_insn "iwmmxt_walignr1"
  [(set (match_operand:V8QI                           0 "register_operand" "=y")
	(subreg:V8QI (ashiftrt:TI
		       (subreg:TI (vec_concat:V16QI
				    (match_operand:V8QI 1 "register_operand" "y")
				    (match_operand:V8QI 2 "register_operand" "y")) 0)
		       (mult:SI
		         (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0))
		         (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "walignr1%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "walignr")]
)

(define_insn "iwmmxt_walignr2"
  [(set (match_operand:V8QI                           0 "register_operand" "=y")
	(subreg:V8QI (ashiftrt:TI
		       (subreg:TI (vec_concat:V16QI
				    (match_operand:V8QI 1 "register_operand" "y")
				    (match_operand:V8QI 2 "register_operand" "y")) 0)
		       (mult:SI
		         (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0))
		         (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "walignr2%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "walignr")]
)

(define_insn "iwmmxt_walignr3"
  [(set (match_operand:V8QI                           0 "register_operand" "=y")
	(subreg:V8QI (ashiftrt:TI
		       (subreg:TI (vec_concat:V16QI
				    (match_operand:V8QI 1 "register_operand" "y")
				    (match_operand:V8QI 2 "register_operand" "y")) 0)
		       (mult:SI
		         (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0))
		         (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "walignr3%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "walignr")]
)

(define_insn "iwmmxt_wsadb"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (unspec:V2SI [
		      (match_operand:V2SI 1 "register_operand" "0")
		      (match_operand:V8QI 2 "register_operand" "y")
		      (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))]
  "TARGET_REALLY_IWMMXT"
  "wsadb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsad")]
)

(define_insn "iwmmxt_wsadh"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (unspec:V2SI [
		      (match_operand:V2SI 1 "register_operand" "0")
		      (match_operand:V4HI 2 "register_operand" "y")
		      (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))]
  "TARGET_REALLY_IWMMXT"
  "wsadh%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsad")]
)

(define_insn "iwmmxt_wsadbz"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
		      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
  "TARGET_REALLY_IWMMXT"
  "wsadbz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsad")]
)

(define_insn "iwmmxt_wsadhz"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
  "TARGET_REALLY_IWMMXT"
  "wsadhz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")
   (set_attr "wtype" "wsad")]
)

(include "iwmmxt2.md")




;; Marvell WMMX2 pipeline description
;; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
;; Written by Marvell, Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.


(define_automaton "marvell_f_iwmmxt")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Pipelines
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;; This is a 7-stage pipelines:
;;
;;    MD | MI | ME1 | ME2 | ME3 | ME4 | MW
;;
;; There are various bypasses modelled to a greater or lesser extent.
;;
;; Latencies in this file correspond to the number of cycles after
;; the issue stage that it takes for the result of the instruction to
;; be computed, or for its side-effects to occur.

(define_cpu_unit "mf_iwmmxt_MD" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_MI" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_ME1" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_ME2" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_ME3" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_ME4" "marvell_f_iwmmxt")
(define_cpu_unit "mf_iwmmxt_MW" "marvell_f_iwmmxt")

(define_reservation "mf_iwmmxt_ME"
      "mf_iwmmxt_ME1,mf_iwmmxt_ME2,mf_iwmmxt_ME3,mf_iwmmxt_ME4"
)

(define_reservation "mf_iwmmxt_pipeline"
      "mf_iwmmxt_MD, mf_iwmmxt_MI, mf_iwmmxt_ME, mf_iwmmxt_MW"
)

;; An attribute to indicate whether our reservations are applicable.
(define_attr "marvell_f_iwmmxt" "yes,no"
  (const (if_then_else (symbol_ref "arm_arch_iwmmxt")
                       (const_string "yes") (const_string "no"))))

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; instruction classes
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;; An attribute appended to instructions for classification

(define_attr "wmmxt_shift" "yes,no"
  (if_then_else (eq_attr "wtype" "wror, wsll, wsra, wsrl")
		(const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_pack" "yes,no"
  (if_then_else (eq_attr "wtype" "waligni, walignr, wmerge, wpack, wshufh, wunpckeh, wunpckih, wunpckel, wunpckil")
		(const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_mult_c1" "yes,no"
  (if_then_else (eq_attr "wtype" "wmac, wmadd, wmiaxy, wmiawxy, wmulw, wqmiaxy, wqmulwm")
		(const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_mult_c2" "yes,no"
  (if_then_else (eq_attr "wtype" "wmul, wqmulm")
		(const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_alu_c1" "yes,no"
  (if_then_else (eq_attr "wtype" "wabs, wabsdiff, wand, wandn, wmov, wor, wxor")
	        (const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_alu_c2" "yes,no"
  (if_then_else (eq_attr "wtype" "wacc, wadd, waddsubhx, wavg2, wavg4, wcmpeq, wcmpgt, wmax, wmin, wsub, waddbhus, wsubaddhx")
		(const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_alu_c3" "yes,no"
  (if_then_else (eq_attr "wtype" "wsad")
	        (const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_transfer_c1" "yes,no"
  (if_then_else (eq_attr "wtype" "tbcst, tinsr, tmcr, tmcrr")
                (const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_transfer_c2" "yes,no"
  (if_then_else (eq_attr "wtype" "textrm, tmovmsk, tmrc, tmrrc")
	        (const_string "yes") (const_string "no"))
)

(define_attr "wmmxt_transfer_c3" "yes,no"
  (if_then_else (eq_attr "wtype" "tmia, tmiaph, tmiaxy")
	        (const_string "yes") (const_string "no"))
)

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Main description
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(define_insn_reservation "marvell_f_iwmmxt_alu_c1" 1
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_alu_c1" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_pack" 1
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_pack" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_shift" 1
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_shift" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_transfer_c1" 1
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_transfer_c1" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_transfer_c2" 5
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_transfer_c2" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_alu_c2" 2
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_alu_c2" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_alu_c3" 3
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_alu_c3" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_transfer_c3" 4
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_transfer_c3" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_mult_c1" 4
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_mult_c1" "yes"))
  "mf_iwmmxt_pipeline")

;There is a forwarding path from ME3 stage
(define_insn_reservation "marvell_f_iwmmxt_mult_c2" 3
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wmmxt_mult_c2" "yes"))
  "mf_iwmmxt_pipeline")

(define_insn_reservation "marvell_f_iwmmxt_wstr" 0
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wtype" "wstr"))
  "mf_iwmmxt_pipeline")

;There is a forwarding path from MW stage
(define_insn_reservation "marvell_f_iwmmxt_wldr" 5
  (and (eq_attr "marvell_f_iwmmxt" "yes")
       (eq_attr "wtype" "wldr"))
  "mf_iwmmxt_pipeline")




/* Copyright (C) 2002, 2003, 2004, 2009, 2012 Free Software Foundation, Inc.

   This file is part of GCC.


#ifndef _MMINTRIN_H_INCLUDED
#define _MMINTRIN_H_INCLUDED

#ifndef __IWMMXT__
#error mmintrin.h included without enabling WMMX/WMMX2 instructions (e.g. -march=iwmmxt or -march=iwmmxt2)
#endif


#if defined __cplusplus
extern "C" {
/* Intrinsics use C name-mangling.  */
#endif /* __cplusplus */

/* The data type intended for user use.  */
typedef unsigned long long __m64, __int64;

/* Internal data types for implementing the intrinsics.  */
typedef int __v2si __attribute__ ((vector_size (8)));
typedef short __v4hi __attribute__ ((vector_size (8)));
typedef signed char __v8qi __attribute__ ((vector_size (8)));

/* "Convert" __m64 and __int64 into each other.  */
static __inline __m64
_mm_cvtsi64_m64 (__int64 __i)
{
  return __i;

static __inline __int64
_mm_cvtsi32_si64 (int __i)
{
  return (__i & 0xffffffff);
}

/* Pack the four 16-bit values from M1 into the lower four 8-bit values of

static __inline __m64
_mm_andnot_si64 (__m64 __m1, __m64 __m2)
{
  return __builtin_arm_wandn (__m2, __m1);
}

/* Bit-wise inclusive OR the 64-bit values in M1 and M2.  */

static __inline __m64
_mm_sad_pu8 (__m64 __A, __m64 __B)
{
  return (__m64) __builtin_arm_wsadbz ((__v8qi)__A, (__v8qi)__B);
}

static __inline __m64
_mm_sada_pu8 (__m64 __A, __m64 __B, __m64 __C)
{
  return (__m64) __builtin_arm_wsadb ((__v2si)__A, (__v8qi)__B, (__v8qi)__C);
}

/* Compute the sum of the absolute differences of the unsigned 16-bit

static __inline __m64
_mm_sad_pu16 (__m64 __A, __m64 __B)
{
  return (__m64) __builtin_arm_wsadhz ((__v4hi)__A, (__v4hi)__B);
}

static __inline __m64
_mm_sada_pu16 (__m64 __A, __m64 __B, __m64 __C)
{
  return (__m64) __builtin_arm_wsadh ((__v2si)__A, (__v4hi)__B, (__v4hi)__C);
}


/* Compute the sum of the absolute differences of the unsigned 8-bit
   values in A and B.  Return the value in the lower 16-bit word; the
   upper words are cleared.  */

  return (__m64) __builtin_arm_wsadhz ((__v4hi)__A, (__v4hi)__B);
}

#define _mm_align_si64(__A,__B, N) \
  (__m64) __builtin_arm_walign ((__v8qi) (__A),(__v8qi) (__B), (N))
{
  return (__m64) __builtin_arm_walign ((__v8qi)__A, (__v8qi)__B, __C);
}

/* Creates a 64-bit zero.  */
static __inline __m64

{
  switch (__regno)
    {
    case 0:
      __asm __volatile ("tmcr wcid, %0" :: "r"(__value));
      break;
    case 1:
      __asm __volatile ("tmcr wcon, %0" :: "r"(__value));
      break;
    case 2:
      __asm __volatile ("tmcr wcssf, %0" :: "r"(__value));
      break;
    case 3:
      __asm __volatile ("tmcr wcasf, %0" :: "r"(__value));
      break;
    case 8:
      __builtin_arm_setwcgr0 (__value);
      break;
    case 9:
      __builtin_arm_setwcgr1 (__value);
      break;
    case 10:
      __builtin_arm_setwcgr2 (__value);
      break;
    case 11:
      __builtin_arm_setwcgr3 (__value);
      break;
    default:
      break;
    }
}

static __inline int
_mm_getwcx (const int __regno)
{
  int __value;
  switch (__regno)
    {
    case 0:
      __asm __volatile ("tmrc %0, wcid" : "=r"(__value));
      break;
    case 1:
      __asm __volatile ("tmrc %0, wcon" : "=r"(__value));
      break;
    case 2:
      __asm __volatile ("tmrc %0, wcssf" : "=r"(__value));
      break;
    case 3:
      __asm __volatile ("tmrc %0, wcasf" : "=r"(__value));
      break;
    case 8:
      return __builtin_arm_getwcgr0 ();
    case 9:
      return __builtin_arm_getwcgr1 ();
    case 10:
      return __builtin_arm_getwcgr2 ();
    case 11:
      return __builtin_arm_getwcgr3 ();
    default:
      break;
    }
  return __value;
}

/* Creates a vector of two 32-bit values; I0 is least significant.  */
static __inline __m64
_mm_set_pi32 (int __i1, int __i0)
{
  union
  {
    __m64 __q;
    struct
    {
      unsigned int __i0;
      unsigned int __i1;
    } __s;

static __inline __m64
_mm_set_pi16 (short __w3, short __w2, short __w1, short __w0)
{
  unsigned int __i1 = (unsigned short) __w3 << 16 | (unsigned short) __w2;
  unsigned int __i0 = (unsigned short) __w1 << 16 | (unsigned short) __w0;

  return _mm_set_pi32 (__i1, __i0);
		       
}

/* Creates a vector of eight 8-bit values; B0 is least significant.  */

  return _mm_set1_pi32 (__i);
}

#ifdef __IWMMXT2__
static __inline __m64
_mm_abs_pi8 (__m64 m1)
{
  return (__m64) __builtin_arm_wabsb ((__v8qi)m1);
}

static __inline __m64
_mm_abs_pi16 (__m64 m1)
{
  return (__m64) __builtin_arm_wabsh ((__v4hi)m1);

}

static __inline __m64
_mm_abs_pi32 (__m64 m1)
{
  return (__m64) __builtin_arm_wabsw ((__v2si)m1);

}

static __inline __m64
_mm_addsubhx_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_waddsubhx ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_absdiff_pu8 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wabsdiffb ((__v8qi)a, (__v8qi)b);
}

static __inline __m64
_mm_absdiff_pu16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wabsdiffh ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_absdiff_pu32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wabsdiffw ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_addc_pu16 (__m64 a, __m64 b)
{
  __m64 result;
  __asm__ __volatile__ ("waddhc	%0, %1, %2" : "=y" (result) : "y" (a),  "y" (b));
  return result;
}

static __inline __m64
_mm_addc_pu32 (__m64 a, __m64 b)
{
  __m64 result;
  __asm__ __volatile__ ("waddwc	%0, %1, %2" : "=y" (result) : "y" (a),  "y" (b));
  return result;
}

static __inline __m64
_mm_avg4_pu8 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wavg4 ((__v8qi)a, (__v8qi)b);
}

static __inline __m64
_mm_avg4r_pu8 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wavg4r ((__v8qi)a, (__v8qi)b);
}

static __inline __m64
_mm_maddx_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmaddsx ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_maddx_pu16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmaddux ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_msub_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmaddsn ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_msub_pu16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmaddun ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_mulhi_pi32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulwsm ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_mulhi_pu32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulwum ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_mulhir_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulsmr ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_mulhir_pi32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulwsmr ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_mulhir_pu16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulumr ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_mulhir_pu32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulwumr ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_mullo_pi32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wmulwl ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_qmulm_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wqmulm ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_qmulm_pi32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wqmulwm ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_qmulmr_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wqmulmr ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_qmulmr_pi32 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wqmulwmr ((__v2si)a, (__v2si)b);
}

static __inline __m64
_mm_subaddhx_pi16 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_wsubaddhx ((__v4hi)a, (__v4hi)b);
}

static __inline __m64
_mm_addbhusl_pu8 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_waddbhusl ((__v4hi)a, (__v8qi)b);
}

static __inline __m64
_mm_addbhusm_pu8 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_waddbhusm ((__v4hi)a, (__v8qi)b);
}

#define _mm_qmiabb_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiabb ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiabbn_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiabbn ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiabt_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiabt ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiabtn_pi32(acc, m1, m2) \
  ({\
   __m64 _acc=acc;\
   __m64 _m1=m1;\
   __m64 _m2=m2;\
   _acc = (__m64) __builtin_arm_wqmiabtn ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiatb_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiatb ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiatbn_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiatbn ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiatt_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiatt ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_qmiattn_pi32(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wqmiattn ((__v2si)_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiabb_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiabb (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiabbn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiabbn (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiabt_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiabt (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiabtn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiabtn (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiatb_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiatb (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiatbn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiatbn (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiatt_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiatt (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiattn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiattn (_acc, (__v4hi)_m1, (__v4hi)_m2);\
   _acc;\
   })

#define _mm_wmiawbb_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawbb (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawbbn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawbbn (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawbt_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawbt (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawbtn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawbtn (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawtb_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawtb (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawtbn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawtbn (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawtt_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawtt (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

#define _mm_wmiawttn_si64(acc, m1, m2) \
  ({\
   __m64 _acc = acc;\
   __m64 _m1 = m1;\
   __m64 _m2 = m2;\
   _acc = (__m64) __builtin_arm_wmiawttn (_acc, (__v2si)_m1, (__v2si)_m2);\
   _acc;\
   })

/* The third arguments should be an immediate.  */
#define _mm_merge_si64(a, b, n) \
  ({\
   __m64 result;\
   result = (__m64) __builtin_arm_wmerge ((__m64) (a), (__m64) (b), (n));\
   result;\
   })
#endif  /* __IWMMXT2__ */

static __inline __m64
_mm_alignr0_si64 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_walignr0 ((__v8qi) a, (__v8qi) b);
}

static __inline __m64
_mm_alignr1_si64 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_walignr1 ((__v8qi) a, (__v8qi) b);
}

static __inline __m64
_mm_alignr2_si64 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_walignr2 ((__v8qi) a, (__v8qi) b);
}

static __inline __m64
_mm_alignr3_si64 (__m64 a, __m64 b)
{
  return (__m64) __builtin_arm_walignr3 ((__v8qi) a, (__v8qi) b);
}

static __inline void
_mm_tandcb ()
{
  __asm __volatile ("tandcb r15");
}

static __inline void
_mm_tandch ()
{
  __asm __volatile ("tandch r15");
}

static __inline void
_mm_tandcw ()
{
  __asm __volatile ("tandcw r15");
}

#define _mm_textrcb(n) \
  ({\
   __asm__ __volatile__ (\
     "textrcb r15, %0" : : "i" (n));\
   })

#define _mm_textrch(n) \
  ({\
   __asm__ __volatile__ (\
     "textrch r15, %0" : : "i" (n));\
   })

#define _mm_textrcw(n) \
  ({\
   __asm__ __volatile__ (\
     "textrcw r15, %0" : : "i" (n));\
   })

static __inline void
_mm_torcb ()
{
  __asm __volatile ("torcb r15");
}

static __inline void
_mm_torch ()
{
  __asm __volatile ("torch r15");
}

static __inline void
_mm_torcw ()
{
  __asm __volatile ("torcw r15");
}

#ifdef __IWMMXT2__
static __inline void
_mm_torvscb ()
{
  __asm __volatile ("torvscb r15");
}

static __inline void
_mm_torvsch ()
{
  __asm __volatile ("torvsch r15");
}

static __inline void
_mm_torvscw ()
{
  __asm __volatile ("torvscw r15");
}
#endif /* __IWMMXT2__ */

static __inline __m64
_mm_tbcst_pi8 (int value)
{
  return (__m64) __builtin_arm_tbcstb ((signed char) value);
}

static __inline __m64
_mm_tbcst_pi16 (int value)
{
  return (__m64) __builtin_arm_tbcsth ((short) value);
}

static __inline __m64
_mm_tbcst_pi32 (int value)
{
  return (__m64) __builtin_arm_tbcstw (value);
}

#define _m_packsswb _mm_packs_pi16

#define _m_paligniq _mm_align_si64
#define _m_cvt_si2pi _mm_cvtsi64_m64
#define _m_cvt_pi2si _mm_cvtm64_si64
#define _m_from_int _mm_cvtsi32_si64
#define _m_to_int _mm_cvtsi64_si32

#if defined __cplusplus
}; /* End "C" */
#endif /* __cplusplus */

#endif /* _MMINTRIN_H_INCLUDED */

Lines 1-5 Link Here

(-)gcc/config/arm/predicates.md (-1 / +6 lines)
1	;; Predicate definitions for ARM and Thumb	1	;; Predicate definitions for ARM and Thumb
2	;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.	2	;; Copyright (C) 2004, 2007, 2008, 2010, 2012 Free Software Foundation, Inc.
3	;; Contributed by ARM Ltd.	3	;; Contributed by ARM Ltd.
4		4
5	;; This file is part of GCC.	5	;; This file is part of GCC.
Lines 619-624 Link Here
619	(and (match_code "const_int")	619	(and (match_code "const_int")
620	(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))	620	(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
621		621
		622	;; iWMMXt predicates
		623
		624	(define_predicate "imm_or_reg_operand"
		625	(ior (match_operand 0 "immediate_operand")
		626	(match_operand 0 "register_operand")))
622		627
623	;; Neon predicates	628	;; Neon predicates
624		629

Return to bug 453294

Lines 62-67 Link Here

(-)gcc/config/arm/arm.md (-3 / +12 lines)
62	;; UNSPEC Usage:	62	;; UNSPEC Usage:
63	;; Note: sin and cos are no-longer used.	63	;; Note: sin and cos are no-longer used.
64	;; Unspec enumerators for Neon are defined in neon.md.	64	;; Unspec enumerators for Neon are defined in neon.md.
		65	;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
65		66
66	(define_c_enum "unspec" [	67	(define_c_enum "unspec" [
67	UNSPEC_SIN ; `sin' operation (MODE_FLOAT):	68	UNSPEC_SIN ; `sin' operation (MODE_FLOAT):
Lines 98-105 Link Here
98	UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.	99	UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
99	UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.	100	UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
100	UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.	101	UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
101	UNSPEC_WMADDS ; Used by the intrinsic form of the iWMMXt WMADDS instruction.	102	UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
102	UNSPEC_WMADDU ; Used by the intrinsic form of the iWMMXt WMADDU instruction.
103	UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.	103	UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.
104	UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the	104	UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the
105	; instruction stream.	105	; instruction stream.
Lines 196-202 Link Here
196	; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without	196	; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
197	; arm_arch6. This attribute is used to compute attribute "enabled",	197	; arm_arch6. This attribute is used to compute attribute "enabled",
198	; use type "any" to enable an alternative in all cases.	198	; use type "any" to enable an alternative in all cases.
199	(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,nota8"	199	(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,nota8,iwmmxt,iwmmxt2"
200	(const_string "any"))	200	(const_string "any"))
201		201
202	(define_attr "arch_enabled" "no,yes"	202	(define_attr "arch_enabled" "no,yes"
Lines 237-242 Link Here
237		237
238	(and (eq_attr "arch" "nota8")	238	(and (eq_attr "arch" "nota8")
239	(not (eq_attr "tune" "cortexa8")))	239	(not (eq_attr "tune" "cortexa8")))
		240	(const_string "yes")
		241
		242	(and (eq_attr "arch" "iwmmxt2")
		243	(match_test "TARGET_REALLY_IWMMXT2"))
240	(const_string "yes")]	244	(const_string "yes")]
241	(const_string "no")))	245	(const_string "no")))
242		246
Lines 351-356 Link Here
351	(const_string "yes")	355	(const_string "yes")
352	(const_string "no")))	356	(const_string "no")))
353		357
		358	; wtype for WMMX insn scheduling purposes.
		359	(define_attr "wtype"
		360	"none,wor,wxor,wand,wandn,wmov,tmcrr,tmrrc,wldr,wstr,tmcr,tmrc,wadd,wsub,wmul,wmac,wavg2,tinsr,textrm,wshufh,wcmpeq,wcmpgt,wmax,wmin,wpack,wunpckih,wunpckil,wunpckeh,wunpckel,wror,wsra,wsrl,wsll,wmadd,tmia,tmiaph,tmiaxy,tbcst,tmovmsk,wacc,waligni,walignr,tandc,textrc,torc,torvsc,wsad,wabs,wabsdiff,waddsubhx,wsubaddhx,wavg4,wmulw,wqmulm,wqmulwm,waddbhus,wqmiaxy,wmiaxy,wmiawxy,wmerge" (const_string "none"))
		361
354	; Load scheduling, set from the arm_ld_sched variable	362	; Load scheduling, set from the arm_ld_sched variable
355	; initialized by arm_option_override()	363	; initialized by arm_option_override()
356	(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))	364	(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
Lines 527-532 Link Here
527	(const_string "yes")	535	(const_string "yes")
528	(const_string "no"))))	536	(const_string "no"))))
529		537
		538	(include "marvell-f-iwmmxt.md")
530	(include "arm-generic.md")	539	(include "arm-generic.md")
531	(include "arm926ejs.md")	540	(include "arm926ejs.md")
532	(include "arm1020e.md")	541	(include "arm1020e.md")

Line 0 Link Here

(-)gcc/config/arm/marvell-f-iwmmxt.md (+179 lines)
		1	;; Marvell WMMX2 pipeline description
		2	;; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
		3	;; Written by Marvell, Inc.
		4
		5	;; This file is part of GCC.
		6
		7	;; GCC is free software; you can redistribute it and/or modify it
		8	;; under the terms of the GNU General Public License as published
		9	;; by the Free Software Foundation; either version 3, or (at your
		10	;; option) any later version.
		11
		12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
		13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
		14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
		15	;; License for more details.
		16
		17	;; You should have received a copy of the GNU General Public License
		18	;; along with GCC; see the file COPYING3. If not see
		19	;; <http://www.gnu.org/licenses/>.
		20
		21
		22	(define_automaton "marvell_f_iwmmxt")
		23
		24	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		25	;; Pipelines
		26	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		27
		28	;; This is a 7-stage pipelines:
		29	;;
		30	;; MD \| MI \| ME1 \| ME2 \| ME3 \| ME4 \| MW
		31	;;
		32	;; There are various bypasses modelled to a greater or lesser extent.
		33	;;
		34	;; Latencies in this file correspond to the number of cycles after
		35	;; the issue stage that it takes for the result of the instruction to
		36	;; be computed, or for its side-effects to occur.
		37
		38	(define_cpu_unit "mf_iwmmxt_MD" "marvell_f_iwmmxt")
		39	(define_cpu_unit "mf_iwmmxt_MI" "marvell_f_iwmmxt")
		40	(define_cpu_unit "mf_iwmmxt_ME1" "marvell_f_iwmmxt")
		41	(define_cpu_unit "mf_iwmmxt_ME2" "marvell_f_iwmmxt")
		42	(define_cpu_unit "mf_iwmmxt_ME3" "marvell_f_iwmmxt")
		43	(define_cpu_unit "mf_iwmmxt_ME4" "marvell_f_iwmmxt")
		44	(define_cpu_unit "mf_iwmmxt_MW" "marvell_f_iwmmxt")
		45
		46	(define_reservation "mf_iwmmxt_ME"
		47	"mf_iwmmxt_ME1,mf_iwmmxt_ME2,mf_iwmmxt_ME3,mf_iwmmxt_ME4"
		48	)
		49
		50	(define_reservation "mf_iwmmxt_pipeline"
		51	"mf_iwmmxt_MD, mf_iwmmxt_MI, mf_iwmmxt_ME, mf_iwmmxt_MW"
		52	)
		53
		54	;; An attribute to indicate whether our reservations are applicable.
		55	(define_attr "marvell_f_iwmmxt" "yes,no"
		56	(const (if_then_else (symbol_ref "arm_arch_iwmmxt")
		57	(const_string "yes") (const_string "no"))))
		58
		59	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		60	;; instruction classes
		61	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		62
		63	;; An attribute appended to instructions for classification
		64
65	(define_attr "wmmxt_shift" "yes,no"
66	(if_then_else (eq_attr "wtype" "wror, wsll, wsra, wsrl")
67	(const_string "yes") (const_string "no"))
68	)
69
70	(define_attr "wmmxt_pack" "yes,no"
71	(if_then_else (eq_attr "wtype" "waligni, walignr, wmerge, wpack, wshufh, wunpckeh, wunpckih, wunpckel, wunpckil")
72	(const_string "yes") (const_string "no"))
73	)
74
75	(define_attr "wmmxt_mult_c1" "yes,no"
76	(if_then_else (eq_attr "wtype" "wmac, wmadd, wmiaxy, wmiawxy, wmulw, wqmiaxy, wqmulwm")
77	(const_string "yes") (const_string "no"))
78	)
79
80	(define_attr "wmmxt_mult_c2" "yes,no"
81	(if_then_else (eq_attr "wtype" "wmul, wqmulm")
82	(const_string "yes") (const_string "no"))
83	)
84
85	(define_attr "wmmxt_alu_c1" "yes,no"
86	(if_then_else (eq_attr "wtype" "wabs, wabsdiff, wand, wandn, wmov, wor, wxor")
87	(const_string "yes") (const_string "no"))
88	)
89
90	(define_attr "wmmxt_alu_c2" "yes,no"
91	(if_then_else (eq_attr "wtype" "wacc, wadd, waddsubhx, wavg2, wavg4, wcmpeq, wcmpgt, wmax, wmin, wsub, waddbhus, wsubaddhx")
92	(const_string "yes") (const_string "no"))
93	)
94
95	(define_attr "wmmxt_alu_c3" "yes,no"
96	(if_then_else (eq_attr "wtype" "wsad")
97	(const_string "yes") (const_string "no"))
98	)
99
100	(define_attr "wmmxt_transfer_c1" "yes,no"
101	(if_then_else (eq_attr "wtype" "tbcst, tinsr, tmcr, tmcrr")
102	(const_string "yes") (const_string "no"))
103	)
104
105	(define_attr "wmmxt_transfer_c2" "yes,no"
106	(if_then_else (eq_attr "wtype" "textrm, tmovmsk, tmrc, tmrrc")
107	(const_string "yes") (const_string "no"))
108	)
109
110	(define_attr "wmmxt_transfer_c3" "yes,no"
111	(if_then_else (eq_attr "wtype" "tmia, tmiaph, tmiaxy")
112	(const_string "yes") (const_string "no"))
113	)
114
115	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
116	;; Main description
117	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
118
119	(define_insn_reservation "marvell_f_iwmmxt_alu_c1" 1
120	(and (eq_attr "marvell_f_iwmmxt" "yes")
121	(eq_attr "wmmxt_alu_c1" "yes"))
122	"mf_iwmmxt_pipeline")
123
124	(define_insn_reservation "marvell_f_iwmmxt_pack" 1
125	(and (eq_attr "marvell_f_iwmmxt" "yes")
126	(eq_attr "wmmxt_pack" "yes"))
127	"mf_iwmmxt_pipeline")
128
129	(define_insn_reservation "marvell_f_iwmmxt_shift" 1
130	(and (eq_attr "marvell_f_iwmmxt" "yes")
131	(eq_attr "wmmxt_shift" "yes"))
132	"mf_iwmmxt_pipeline")
133
134	(define_insn_reservation "marvell_f_iwmmxt_transfer_c1" 1
135	(and (eq_attr "marvell_f_iwmmxt" "yes")
136	(eq_attr "wmmxt_transfer_c1" "yes"))
137	"mf_iwmmxt_pipeline")
138
139	(define_insn_reservation "marvell_f_iwmmxt_transfer_c2" 5
140	(and (eq_attr "marvell_f_iwmmxt" "yes")
141	(eq_attr "wmmxt_transfer_c2" "yes"))
142	"mf_iwmmxt_pipeline")
143
144	(define_insn_reservation "marvell_f_iwmmxt_alu_c2" 2
145	(and (eq_attr "marvell_f_iwmmxt" "yes")
146	(eq_attr "wmmxt_alu_c2" "yes"))
147	"mf_iwmmxt_pipeline")
148
149	(define_insn_reservation "marvell_f_iwmmxt_alu_c3" 3
150	(and (eq_attr "marvell_f_iwmmxt" "yes")
151	(eq_attr "wmmxt_alu_c3" "yes"))
152	"mf_iwmmxt_pipeline")
153
154	(define_insn_reservation "marvell_f_iwmmxt_transfer_c3" 4
155	(and (eq_attr "marvell_f_iwmmxt" "yes")
156	(eq_attr "wmmxt_transfer_c3" "yes"))
157	"mf_iwmmxt_pipeline")
158
159	(define_insn_reservation "marvell_f_iwmmxt_mult_c1" 4
160	(and (eq_attr "marvell_f_iwmmxt" "yes")
161	(eq_attr "wmmxt_mult_c1" "yes"))
162	"mf_iwmmxt_pipeline")
163
164	;There is a forwarding path from ME3 stage
165	(define_insn_reservation "marvell_f_iwmmxt_mult_c2" 3
166	(and (eq_attr "marvell_f_iwmmxt" "yes")
167	(eq_attr "wmmxt_mult_c2" "yes"))
168	"mf_iwmmxt_pipeline")
169
170	(define_insn_reservation "marvell_f_iwmmxt_wstr" 0
171	(and (eq_attr "marvell_f_iwmmxt" "yes")
172	(eq_attr "wtype" "wstr"))
173	"mf_iwmmxt_pipeline")
174
175	;There is a forwarding path from MW stage
176	(define_insn_reservation "marvell_f_iwmmxt_wldr" 5
177	(and (eq_attr "marvell_f_iwmmxt" "yes")
178	(eq_attr "wtype" "wldr"))
179	"mf_iwmmxt_pipeline")

Lines 1-6 Link Here

(-)gcc/config/arm/t-arm (-1 / +3 lines)
1	# Rules common to all arm targets	1	# Rules common to all arm targets
2	#	2	#
3	# Copyright (C) 2004, 2005, 2007, 2008, 2009, 2010, 2011	3	# Copyright (C) 2004, 2005, 2007, 2008, 2009, 2010, 2011, 2012
4	# Free Software Foundation, Inc.	4	# Free Software Foundation, Inc.
5	#	5	#
6	# This file is part of GCC.	6	# This file is part of GCC.
Lines 49-55 Link Here
49	$(srcdir)/config/arm/fpa.md \	49	$(srcdir)/config/arm/fpa.md \
50	$(srcdir)/config/arm/iterators.md \	50	$(srcdir)/config/arm/iterators.md \
51	$(srcdir)/config/arm/iwmmxt.md \	51	$(srcdir)/config/arm/iwmmxt.md \
		52	$(srcdir)/config/arm/iwmmxt2.md \
52	$(srcdir)/config/arm/ldmstm.md \	53	$(srcdir)/config/arm/ldmstm.md \
		54	$(srcdir)/config/arm/marvell-f-iwmmxt.md \
53	$(srcdir)/config/arm/neon.md \	55	$(srcdir)/config/arm/neon.md \
54	$(srcdir)/config/arm/predicates.md \	56	$(srcdir)/config/arm/predicates.md \
55	$(srcdir)/config/arm/sync.md \	57	$(srcdir)/config/arm/sync.md \