Attachment #22205 for bug #35819

Line 0 Link Here

(-)linux-2.4.22/CHANGES (+11 lines)
	1	2.4.22-ben2 : - Remove a hack on the MachineCheck exception handler that seemed
	2	to actually cause a problem on some machines
	3	- Turn legacy serial driver into a module (used by pcmcia modems)
	4	instead of built-in in pmac defconfig
	5	- Export a couple of symbols needed by recent DRI
	6	- Hopefully close a few possible SMP races along with making the
	7	IO ops more robust vs. store reordering.
	8	- Fix build without CONFIG_PMAC_PBOOK
	9
	10	2.4.22-ben1 : First release
	11





  If unsure, say N.

CONFIG_CPU_FREQ
  Clock scaling allows you to change the clock speed of CPUs on the
  fly. This is a nice method to save battery power on notebooks,
  because the lower the clock speed, the less power the CPU consumes.

  For more information, take a look at linux/Documentation/cpufreq or
  at <http://www.brodo.de/cpufreq/>

  If in doubt, say N.

CONFIG_CPU_FREQ_24_API
  This enables the /proc/sys/cpu/ sysctl interface for controlling
  CPUFreq, as known from the 2.4.-kernel patches for CPUFreq. Note
  that some drivers do not support this interface or offer less
  functionality. 

  If you say N here, you'll be able to control CPUFreq using the
  new /proc/cpufreq interface.

  For details, take a look at linux/Documentation/cpufreq. 

  If in doubt, say N.

NatSemi SCx200 support
CONFIG_SCx200
  This provides basic support for the National Semiconductor SCx200




     CPU frequency and voltage scaling code in the Linux(TM) kernel


		         L i n u x    C P U F r e q




		    Dominik Brodowski  <linux@brodo.de>
		     David Kimdon <dwhedon@debian.org>



   Clock scaling allows you to change the clock speed of the CPUs on the
    fly. This is a nice method to save battery power, because the lower
            the clock speed, the less power the CPU consumes.



Contents:
---------
1.  Supported architectures
2.  User interface
2.1   /proc/cpufreq interface  [2.6]
2.2.  /proc/sys/cpu/ interface [2.4]
3.  CPUFreq core and interfaces
3.1   General information
3.2   CPUFreq notifiers
3.3   CPUFreq architecture drivers
4.  Mailing list and Links



1. Supported architectures
==========================

ARM:
    ARM Integrator, SA 1100, SA1110
--------------------------------
    This driver will be ported to new CPUFreq core soon, so
    far it will not work.


AMD Elan:
    SC400, SC410
--------------------------------
    You need to specify the highest allowed CPU frequency as 
    a module parameter ("max_freq") or as boot parameter 
    ("elanfreq="). Else the available speed range will be 
    limited to the speed at which the CPU runs while this
    module is loaded.


VIA Cyrix Longhaul:
    VIA Samuel/CyrixIII, VIA Cyrix Samuel/C3, 
    VIA Cyrix Ezra, VIA Cyrix Ezra-T
--------------------------------
    If you do not want to scale the Front Side Bus or voltage,
    pass the module parameter "dont_scale_fsb 1" or
    "dont_scale_voltage 1". Additionally, it is advised that
    you pass the current Front Side Bus speed (in MHz) to 
    this module as module parameter "current_fsb", e.g. 
    "current_fsb 133" for a Front Side Bus speed of 133 MHz.


Intel SpeedStep:
    certain mobile Intel Pentium III (Coppermine), and all mobile
    Intel Pentium III-M (Tualatin) and mobile Intel Pentium 4 P4-Ms.
--------------------------------
    Unfortunately only modern Intel ICH2-M and ICH3-M chipsets are 
    supported.


P4 CPU Clock Modulation:
    Intel Pentium 4 Xeon processors
---------------------------------
    Note that you can only switch the speed of two logical CPUs at
    once - but each phyiscal CPU may have different throttling levels.


PowerNow! K6:
    mobile AMD K6-2+ / mobile K6-3+:
--------------------------------
    No known issues.


Transmeta Crusoe Longrun:
    Transmeta Crusoe processors:
--------------------------------
    Does not work with the 2.4. /proc/sys/cpu/ interface.



2. User Interface
=================

2.1   /proc/cpufreq interface [2.6]
***********************************

Starting in the patches for kernel 2.5.33, CPUFreq uses a "policy"
interface /proc/cpufreq.

When you "cat" this file, you'll find something like:

--
          minimum CPU frequency  -  maximum CPU frequency  -  policy
CPU  0       1200000 ( 75%)      -     1600000 (100%)      -  performance
--

This means the current policy allows this CPU to be run anywhere
between 1.2 GHz (the value is in kHz) and 1.6 GHz with an eye towards
performance.

To change the policy, "echo" the desired new policy into
/proc/cpufreq. Use one of the following formats:

cpu_nr:min_freq:max_freq:policy
cpu_nr%min_freq%max_freq%policy
min_freq:max_freq:policy
min_freq%max_freq%policy

with cpu_nr being the CPU which shall be affected, min_freq and
max_freq the lower and upper limit of the CPU core frequency in kHz,
and policy either "performance" or "powersave".
A few examples:

root@notebook:#echo -n "0:0:0:powersave" > /proc/cpufreq
     sets the CPU #0 to the lowest supported frequency.

root@notebook:#echo -n "1%100%100%performance" > /proc/cpufreq
     sets the CPU #1 to the highest supported frequency.

root@notebook:#echo -n "1000000:2000000:performance" > /proc/cpufreq
     to set the frequency of all CPUs between 1 GHz and 2 GHz and to
     the policy "performance".

Please note that the values you "echo" into /proc/cpufreq are
validated first, and may be limited by hardware or thermal
considerations. Because of this, a read from /proc/cpufreq might 
differ from what was written into it.


When you read /proc/cpufreq for the first time after a CPUFreq driver
has been initialized, you'll see the "default policy" for this
driver. If this does not suit your needs, you can pass a boot
parameter to the cpufreq core. Use the following syntax for this:
   "cpufreq=min_freq:max_freq:policy", i.e. you may not chose a
specific CPU and you need to specify the limits in kHz and not in
per cent.


2.2   /proc/cpufreq interface [2.4]
***********************************

Previsiously (and still available as a config option), CPUFreq used 
a "sysctl" interface which is located in 
	/proc/sys/cpu/0/
	/proc/sys/cpu/1/ ...	(SMP only)

In these directories, you will find three files of importance for
CPUFreq: speed-max, speed-min and speed: 

speed		    shows the current CPU frequency in kHz, 
speed-min	    the minimum supported CPU frequency, and
speed-max	    the maximum supported CPU frequency.


To change the CPU frequency, "echo" the desired CPU frequency (in kHz)
to speed. For example, to set the CPU speed to the lowest/highest
allowed frequency do:

root@notebook:# cat /proc/sys/cpu/0/speed-min > /proc/sys/cpu/0/speed
root@notebook:# cat /proc/sys/cpu/0/speed-max > /proc/sys/cpu/0/speed



3.  CPUFreq core and interfaces
===============================

3.1   General information
*************************

The CPUFreq core code is located in linux/kernel/cpufreq.c. This
cpufreq code offers a standardized interface for the CPUFreq
architecture drivers (those pieces of code that do actual
frequency transitions), as well as to "notifiers". These are device
drivers or other part of the kernel that need to be informed of
policy changes (like thermal modules like ACPI) or of all
frequency changes (like timing code) or even need to force certain
speed limits (like LCD drivers on ARM architecture). Additionally, the
kernel "constant" loops_per_jiffy is updated on frequency changes
here.


3.2   CPUFreq notifiers
***********************

CPUFreq notifiers conform to the standard kernel notifier interface.
See linux/include/linux/notifier.h for details on notifiers.

There are two different CPUFreq notifiers - policy notifiers and
transition notifiers.


3.2.1 CPUFreq policy notifiers
******************************

These are notified when a new policy is intended to be set. Each
CPUFreq policy notifier is called three times for a policy transition:

1.) During CPUFREQ_ADJUST all CPUFreq notifiers may change the limit if
    they see a need for this - may it be thermal considerations or
    hardware limitations.

2.) During CPUFREQ_INCOMPATIBLE only changes may be done in order to avoid
    hardware failure.

3.) And during CPUFREQ_NOTIFY all notifiers are informed of the new policy
   - if two hardware drivers failed to agree on a new policy before this
   stage, the incompatible hardware shall be shut down, and the user
   informed of this.

The phase is specified in the second argument to the notifier.

The third argument, a void *pointer, points to a struct cpufreq_policy
consisting of five values: cpu, min, max, policy and max_cpu_freq. Min 
and max are the lower and upper frequencies (in kHz) of the new
policy, policy the new policy, cpu the number of the affected CPU or
CPUFREQ_ALL_CPUS for all CPUs; and max_cpu_freq the maximum supported
CPU frequency. This value is given for informational purposes only.


3.2.2 CPUFreq transition notifiers
**********************************

These are notified twice when the CPUfreq driver switches the CPU core
frequency and this change has any external implications.

The second argument specifies the phase - CPUFREQ_PRECHANGE or
CPUFREQ_POSTCHANGE.

The third argument is a struct cpufreq_freqs with the following
values:
cpu	- number of the affected CPU or CPUFREQ_ALL_CPUS
old	- old frequency
new	- new frequency


3.3   CPUFreq architecture drivers
**********************************

CPUFreq architecture drivers are the pieces of kernel code that
actually perform CPU frequency transitions. These need to be
initialized separately (separate initcalls), and may be
modularized. They interact with the CPUFreq core in the following way:

cpufreq_register()
------------------
cpufreq_register registers an arch driver to the CPUFreq core. Please
note that only one arch driver may be registered at any time. -EBUSY
is returned when an arch driver is already registered. The argument to
cpufreq_register, struct cpufreq_driver *driver, is described later.

cpufreq_unregister()
--------------------
cpufreq_unregister unregisters an arch driver, e.g. on module
unloading. Please note that there is no check done that this is called
from the driver which actually registered itself to the core, so
please only call this function when you are sure the arch driver got
registered correctly before.

cpufreq_notify_transition()
---------------------------
On "dumb" hardware where only fixed frequency can be set, the driver
must call cpufreq_notify_transition() once before, and once after the
actual transition.

struct cpufreq_driver
---------------------
On initialization, the arch driver is supposed to pass a pointer
to a struct cpufreq_driver *cpufreq_driver consisting of the following
entries:

cpufreq_verify_t verify: This is a pointer to a function with the
	following definition:
	void verify_function (struct cpufreq_policy *policy).
	This function must verify the new policy is within the limits
	supported by the CPU, and at least one supported CPU is within
	this range. It may be useful to use cpufreq.h /
	cpufreq_verify_within_limits for this.

cpufreq_setpolicy_t setpolicy: This is a pointer to a function with
	the following definition:
	void setpolicy_function (struct cpufreq_policy *policy).
	This function must set the CPU to the new policy. If it is a
	"dumb" CPU which only allows fixed frequencies to be set, it
	shall set it to the lowest within the limit for
	CPUFREQ_POLICY_POWERSAVE, and to the highest for
	CPUFREQ_POLICY_PERFORMANCE. Once CONFIG_CPU_FREQ_DYNAMIC is
	implemented, it can use a dynamic method to adjust the speed
	between the lower and upper limit.

struct cpufreq_policy   *policy: This is an array of NR_CPUS struct
	cpufreq_policies, containing the current policies set for these
	CPUs. Note that policy[0].max_cpu_freq must contain the
	absolute maximum CPU frequency supported by _all_ CPUs.

In case the driver is expected to run with the 2.4.-style API
(/proc/sys/cpu/.../), two more values must be passed
#ifdef CONFIG_CPU_FREQ_24_API
	unsigned int            cpu_min_freq;
	unsigned int            cpu_cur_freq[NR_CPUS];
#endif
	with cpu_min_freq being the minimum CPU frequency supported by
	the CPUs; and the entries in cpu_cur_freq reflecting the
	current speed of the appropriate CPU.

Some Requirements to CPUFreq architecture drivers
-------------------------------------------------
* Only call cpufreq_register() when the ability to switch CPU
  frequencies is _verified_ or can't be missing
* cpufreq_unregister() may only be called if cpufreq_register() has
  been successfully(!) called before.
* kfree() the struct cpufreq_driver only after the call to 
  cpufreq_unregister(), unless cpufreq_register() failed.
* Be aware that there is currently no error management in the
  setpolicy() code in the CPUFreq core. So only call yourself a
  cpufreq_driver if you are really a working cpufreq_driver!



4. Mailing list and Links
*************************


Mailing List
------------
There is a CPU frequency changing CVS commit and general list where
you can report bugs, problems or submit patches. To post a message,
send an email to cpufreq@www.linux.org.uk, to subscribe go to
http://www.linux.org.uk/mailman/listinfo/cpufreq. Previous post to the
mailing list are available to subscribers at
http://www.linux.org.uk/mailman/private/cpufreq/.


Links
-----
the FTP archives:
* ftp://ftp.linux.org.uk/pub/linux/cpufreq/

how to access the CVS repository:
* http://cvs.arm.linux.org.uk/

the CPUFreq Mailing list:
* http://www.linux.org.uk/mailman/listinfo/cpufreq

Clock and voltage scaling for the SA-1100:
* http://www.lart.tudelft.nl/projects/scaling

CPUFreq project homepage
* http://www.brodo.de/cpufreq/




#!/bin/sh
#
# start of stop laptop mode, best run by a power management daemon when
# ac gets connected/disconnected from a laptop
#
# FIXME: assumes HZ == 100

# age time, in seconds. should be put into a sysconfig file
MAX_AGE=600

# kernel default dirty buffer age
DEF_AGE=30
DEF_UPDATE=5

if [ ! -w /proc/sys/vm/laptop_mode ]; then
	echo "Kernel is not patched with laptop_mode patch"
	exit 1
fi

case "$1" in
	start)
		AGE=$((100*$MAX_AGE))
		echo -n "Starting laptop mode"
		echo "1" > /proc/sys/vm/laptop_mode
		echo "30 500 0 0 $AGE $AGE 60 20 0" > /proc/sys/vm/bdflush
		echo "."
		;;
	stop)
		U_AGE=$((100*$DEF_UPDATE))
		B_AGE=$((100*$DEF_AGE))
		echo -n "Stopping laptop mode"
		echo "0" > /proc/sys/vm/laptop_mode
		echo "30 500 0 0 $U_AGE $B_AGE 60 20 0" > /proc/sys/vm/bdflush
		echo "."
		;;
	*)
		echo "$0 {start|stop}"
		;;

esac

exit 0




Laptop mode
===========

This small doc describes the 2.4 laptop mode patch.

Last updated 2003-05-25, Jens Axboe <axboe@suse.de>

Introduction
------------

A few properties of the Linux vm makes it virtually impossible to attempt
to spin down the hard drive in a laptop for a longer period of time (more
than a handful of seconds). This means you are lucky if you can even reach
the break even point with regards to power consumption, let alone expect any
decrease.

One problem is the age time of dirty buffers. Linux uses 30 seconds per
default, so if you dirty any data then flusing of that data will commence
at most 30 seconds from then. Another is the journal commit interval of
journalled file systems such as ext3, which is 5 seconds on a stock kernel.
Both of these are tweakable either from proc/sysctl or as mount options
though, and thus partly solvable from user space.

The kernel update daemon (kupdated) also runs at specific intervals, flushing
old dirty data out. Default is every 5 seconds, this too can be tweaked
from sysctl.

So what does the laptop mode patch do? It attempts to fully utilize the
hard drive once it has been spun up, flushing the old dirty data out to
disk. Instead of flushing just the expired data, it will clean everything.
When a read causes the disk to spin up, we kick off this flushing after
a few seconds. This means that once the disk spins down again, everything
is up to date. That allows longer dirty data and journal expire times.

It follows that you have to set long expire times to get long spin downs.
This means you could potentially loose 10 minutes worth of data, if you
set a 10 minute expire count instead of just 30 seconds worth. The biggest
risk here is undoubtedly running out of battery.

Settings
--------

The main knob is /proc/sys/vm/laptop mode. Setting that to 1 switches the
vm (and block layer) to laptop mode. Leaving it to 0 makes the kernel work
like before. When in laptop mode, you also want to extend the intervals
desribed above. See the laptop-mode.sh script for how to do that.

It can happen that the disk still keeps spinning up and you don't quite
know why or what causes it. The laptop mode patch has a little helper for
that as well, /proc/sys/vm/block-dump. When set to 1, it will dump info to
the kernel message buffer about what process caused the io. Be very careful
when playing with this setting, it is advisable to shut down syslog first!

Result
------

Using the laptop-mode.sh script with its default settings, I get the full
10 minutes worth of drive spin down. Provided your work load is cached,
the disk will only spin up every 10 minutes (well actually, 9 minutes and 55
seconds due to the 5 second delay in flushing dirty data after the last read
completes). I can't tell you exactly how much extra battery life you will
gain in laptop mode, it will vary greatly on the laptop and workload in
question. The only way to know for sure is to try it out. Getting 10% extra
battery life is not unrealistic.

Notes
-----

Patch only changes journal expire time for ext3. reiserfs uses a hardwire
value, should be trivial to adapt though (basically just make it call
get_buffer_flushtime() and uses that). I have not looked at other
journalling file systems, I'll happily accept patches to rectify that!

Lines 759-764 Link Here

(-)linux-2.4.22/MAINTAINERS (-1 / +7 lines)
759	L: linux-kernel@vger.kernel.org	759	L: linux-kernel@vger.kernel.org
760	S: Maintained	760	S: Maintained
761		761
		762	HFSPLUS FILESYSTEM
		763	P: Brad Boyer
		764	M: flar@allandria.com
		765	W: http://sourceforge.net/projects/linux-hfsplus/
		766	S: Maintained
		767
762	HGA FRAMEBUFFER DRIVER	768	HGA FRAMEBUFFER DRIVER
763	P: Ferenc Bakonyi	769	P: Ferenc Bakonyi
764	M: fero@drama.obuda.kando.hu	770	M: fero@drama.obuda.kando.hu
Lines 1309-1315 Link Here
1309	NVIDIA (RIVA) FRAMEBUFFER DRIVER	1315	NVIDIA (RIVA) FRAMEBUFFER DRIVER
1310	P: Ani Joshi	1316	P: Ani Joshi
1311	M: ajoshi@kernel.crashing.org	1317	M: ajoshi@kernel.crashing.org
1312	L: linux-nvidia@lists.surfsouth.com	1318	L: linux-fbdev-devel@lists.sourceforge.net
1313	S: Maintained	1319	S: Maintained
1314		1320
1315	OLYMPIC NETWORK DRIVER	1321	OLYMPIC NETWORK DRIVER

Lines 1-7 Link Here

(-)linux-2.4.22/Makefile (-1 / +1 lines)
1	VERSION = 2	1	VERSION = 2
2	PATCHLEVEL = 4	2	PATCHLEVEL = 4
3	SUBLEVEL = 22	3	SUBLEVEL = 22
4	EXTRAVERSION =	4	EXTRAVERSION = -ben2
5		5
6	KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)	6	KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
7		7




Welcome to my PowerMac tree.

In addition to the standard feature set of kernel.org's 2.4.22, this
tree includes small fixes that didn't make it into 2.4.21, including all
of what was present as of 2.4.21-ben3. Some of the major additions are:

 - Laptop mode patch (Jens Axboe). See Documentation/laptop_mode.sh script
 - Andrea Arcangeli's silent-stack-overflow patch
 - CPU Frequency switching support on some laptops
 - Support for UniNorth AGP in the agpgart driver (though it's strongly
   recommended that you use Michel's Danzer DRM module for that to work
   properly)
 - Support for blinking the laptop LED on internal HD activity
   (Jens and me)
 - Improved support for lba48 capable disks (Jens Axboe)
 - Updated rivafb with support for more cards & eMac
 - Updated sungem driver, supports more chips & recent PHYs
 - Updated dmasound driver to support tumbler & snapper
 - Add reporting of OF device path of IDE interfaces in /proc/ide
 - Fixes for CompactFlash cards
 - Fixes to vmlinux.coff oldworld wrapper
 - Better TB sync code for 2 CPU machines from Samuel Rydth


Lines 124-130 Link Here

(-)linux-2.4.22/arch/alpha/mm/fault.c (-1 / +1 lines)
124	goto good_area;	124	goto good_area;
125	if (!(vma->vm_flags & VM_GROWSDOWN))	125	if (!(vma->vm_flags & VM_GROWSDOWN))
126	goto bad_area;	126	goto bad_area;
127	if (expand_stack(vma, address))	127	if (expand_stack(vma, address, NULL))
128	goto bad_area;	128	goto bad_area;
129	/*	129	/*
130	* Ok, we have a good vm_area for this memory access, so	130	* Ok, we have a good vm_area for this memory access, so

Lines 254-260 Link Here

(-)linux-2.4.22/arch/arm/mm/fault-common.c (-1 / +1 lines)
254	goto survive;	254	goto survive;
255		255
256	check_stack:	256	check_stack:
257	if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr))	257	if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr, NULL))
258	goto good_area;	258	goto good_area;
259	out:	259	out:
260	return fault;	260	return fault;

Lines 323-329 Link Here

(-)linux-2.4.22/arch/cris/mm/fault.c (-1 / +1 lines)
323	if (address + PAGE_SIZE < rdusp())	323	if (address + PAGE_SIZE < rdusp())
324	goto bad_area;	324	goto bad_area;
325	}	325	}
326	if (expand_stack(vma, address))	326	if (expand_stack(vma, address, NULL))
327	goto bad_area;	327	goto bad_area;
328		328
329	/*	329	/*




 */
int __verify_write(const void * addr, unsigned long size)
{
	struct vm_area_struct * vma, * prev_vma;
	unsigned long start = (unsigned long) addr;

	if (!size)

check_stack:
	if (!(vma->vm_flags & VM_GROWSDOWN))
		goto bad_area;
	find_vma_prev(current->mm, start, &prev_vma);
	if (expand_stack(vma, start, prev_vma) == 0)
		goto good_area;

bad_area:

{
	struct task_struct *tsk;
	struct mm_struct *mm;
	struct vm_area_struct * vma, * prev_vma;
	unsigned long address;
	unsigned long page;
	unsigned long fixup;

		if (address + 32 < regs->esp)
			goto bad_area;
	}
	find_vma_prev(mm, address, &prev_vma);
	if (expand_stack(vma, address, prev_vma))
		goto bad_area;
/*
 * Ok, we have a good vm_area for this memory access, so

Lines 159-165 Link Here

(-)linux-2.4.22/arch/ia64/mm/fault.c (-1 / +1 lines)
159	if (rgn_index(address) != rgn_index(vma->vm_start)	159	if (rgn_index(address) != rgn_index(vma->vm_start)
160	\|\| rgn_offset(address) >= RGN_MAP_LIMIT)	160	\|\| rgn_offset(address) >= RGN_MAP_LIMIT)
161	goto bad_area;	161	goto bad_area;
162	if (expand_stack(vma, address))	162	if (expand_stack(vma, address, NULL))
163	goto bad_area;	163	goto bad_area;
164	} else {	164	} else {
165	vma = prev_vma;	165	vma = prev_vma;

Lines 120-126 Link Here

(-)linux-2.4.22/arch/m68k/mm/fault.c (-1 / +1 lines)
120	if (address + 256 < rdusp())	120	if (address + 256 < rdusp())
121	goto map_err;	121	goto map_err;
122	}	122	}
123	if (expand_stack(vma, address))	123	if (expand_stack(vma, address, NULL))
124	goto map_err;	124	goto map_err;
125		125
126	/*	126	/*

Lines 114-120 Link Here

(-)linux-2.4.22/arch/mips/mm/fault.c (-1 / +1 lines)
114	goto good_area;	114	goto good_area;
115	if (!(vma->vm_flags & VM_GROWSDOWN))	115	if (!(vma->vm_flags & VM_GROWSDOWN))
116	goto bad_area;	116	goto bad_area;
117	if (expand_stack(vma, address))	117	if (expand_stack(vma, address, NULL))
118	goto bad_area;	118	goto bad_area;
119	/*	119	/*
120	* Ok, we have a good vm_area for this memory access, so	120	* Ok, we have a good vm_area for this memory access, so

Lines 137-143 Link Here

(-)linux-2.4.22/arch/mips64/mm/fault.c (-1 / +1 lines)
137	goto good_area;	137	goto good_area;
138	if (!(vma->vm_flags & VM_GROWSDOWN))	138	if (!(vma->vm_flags & VM_GROWSDOWN))
139	goto bad_area;	139	goto bad_area;
140	if (expand_stack(vma, address))	140	if (expand_stack(vma, address, NULL))
141	goto bad_area;	141	goto bad_area;
142	/*	142	/*
143	* Ok, we have a good vm_area for this memory access, so	143	* Ok, we have a good vm_area for this memory access, so




extern char _start, _end;

extern char *claim(unsigned, unsigned, unsigned);
extern int map(unsigned, unsigned, unsigned);
extern char image_data[], initrd_data[];
extern int initrd_len, image_len;
extern int getprop(void *, const char *, void *, int);

char *begin_avail, *end_avail;
char *avail_high;

#define RAM_START	0
#define RAM_END		(RAM_START + 0x800000)	/* only 8M mapped with BATs */

#define PROG_START	RAM_START
#define PROG_SIZE	0x00400000

#define SCRATCH_SIZE	(128 << 10)

static char heap[SCRATCH_SIZE];

//static unsigned long ram_start = 0;
//static unsigned long ram_end = 0x800000;
//static unsigned long prog_start = 0;
//static unsigned long prog_size = 0x380000;

static unsigned long ram_start = 0;
static unsigned long ram_end = 0x1000000;
static unsigned long prog_start = 0x800000;
static unsigned long prog_size = 0x800000;
typedef void (*kernel_start_t)(int, int, void *);

void boot(int a1, int a2, void *prom)

    unsigned initrd_start, initrd_size;

    printf("coffboot starting: loaded at 0x%p\n", &_start);
    setup_bats(ram_start);

    initrd_size = (char *)(&__ramdisk_end) - (char *)(&__ramdisk_begin);
    if (initrd_size) {
	initrd_start = (ram_end - initrd_size) & ~0xFFF;
	a1 = initrd_start;
	a2 = initrd_size;
	claim(initrd_start, ram_end - initrd_start, 0);
	printf("initial ramdisk moving 0x%x <- 0x%p (%x bytes)\n\r",
	       initrd_start, (char *)(&__ramdisk_begin), initrd_size);
	memcpy((char *)initrd_start, (char *)(&__ramdisk_begin), initrd_size);
	prog_size = initrd_start - prog_start;
    } else
	a2 = 0xdeadbeef;

    im = (char *)(&__image_begin);
    len = (char *)(&__image_end) - (char *)(&__image_begin);
    /* claim 4MB starting at 0 */
    claim(prog_start, prog_size, 0);
    map(prog_start, prog_start, prog_size);
    dst = (void *) prog_start;
    if (im[0] == 0x1f && im[1] == 0x8b) {
	/* set up scratch space */
	begin_avail = avail_high = avail_ram = heap;
	end_avail = heap + sizeof(heap);
	printf("heap at 0x%p\n", avail_ram);
	printf("gunzipping (0x%p <- 0x%p:0x%p)...", dst, im, im+len);
	gunzip(dst, prog_size, im, &len);
	printf("done %u bytes\n", len);
	printf("%u bytes of heap consumed, max in use %u\n",
	       avail_high - begin_avail, heap_max);


    flush_cache(dst, len);
    make_bi_recs(((unsigned long) dst + len), "coffboot", _MACH_Pmac,
		    (prog_start + prog_size));

    sa = (unsigned long)prog_start;
    printf("start address = 0x%x\n", sa);

    (*(kernel_start_t)sa)(a1, a2, prom);

Lines 9-15 Link Here

(-)linux-2.4.22/arch/ppc/boot/pmac/misc.S (-1 / +11 lines)
9	.text	9	.text
10		10
11	/*	11	/*
12	* Use the BAT3 registers to map the 1st 8MB of RAM to	12	* Use the BAT2 & 3 registers to map the 1st 16MB of RAM to
13	* the address given as the 1st argument.	13	* the address given as the 1st argument.
14	*/	14	*/
15	.globl setup_bats	15	.globl setup_bats
Lines 22-27 Link Here
22	mtibatl 3,0 /* invalidate BAT first */	22	mtibatl 3,0 /* invalidate BAT first */
23	ori 3,3,4 /* set up BAT registers for 601 */	23	ori 3,3,4 /* set up BAT registers for 601 */
24	li 4,0x7f	24	li 4,0x7f
		25	mtibatu 2,3
		26	mtibatl 2,4
		27	oris 3,3,0x80
		28	oris 4,4,0x80
25	mtibatu 3,3	29	mtibatu 3,3
26	mtibatl 3,4	30	mtibatl 3,4
27	b 5f	31	b 5f
Lines 29-34 Link Here
29	mtibatu 3,0	33	mtibatu 3,0
30	ori 3,3,0xff /* set up BAT registers for 604 */	34	ori 3,3,0xff /* set up BAT registers for 604 */
31	li 4,2	35	li 4,2
		36	mtdbatl 2,4
		37	mtdbatu 2,3
		38	mtibatl 2,4
		39	mtibatu 2,3
		40	oris 3,3,0x80
		41	oris 4,4,0x80
32	mtdbatl 3,4	42	mtdbatl 3,4
33	mtdbatu 3,3	43	mtdbatu 3,3
34	mtibatl 3,4	44	mtibatl 3,4

Lines 11-22 Link Here

(-)linux-2.4.22/arch/ppc/boot/pmac/start.c (-2 / +40 lines)
11	extern int strlen(const char *s);	11	extern int strlen(const char *s);
12	extern void boot(int a1, int a2, void *prom);	12	extern void boot(int a1, int a2, void *prom);
13		13
14	int (prom)(void args);	14	int (prom)(void );
15		15
16	void *chosen_handle;	16	void *chosen_handle;
17	void *stdin;	17	void *stdin;
18	void *stdout;	18	void *stdout;
19	void *stderr;	19	void *stderr;
		20	void *prom_mmu;
20		21
21	void exit(void);	22	void exit(void);
22	void finddevice(const char name);	23	void finddevice(const char name);
Lines 35-40 Link Here
35	stderr = stdout;	36	stderr = stdout;
36	if (getprop(chosen_handle, "stdin", &stdin, sizeof(stdin)) != 4)	37	if (getprop(chosen_handle, "stdin", &stdin, sizeof(stdin)) != 4)
37	exit();	38	exit();
		39	if (getprop(chosen_handle, "mmu", &prom_mmu, sizeof(prom_mmu)) != 4)
		40	exit();
38		41
39	boot(a1, a2, promptr);	42	boot(a1, a2, promptr);
40	for (;;)	43	for (;;)
Lines 195-200 Link Here
195	}	198	}
196		199
197	int	200	int
		201	map(unsigned int phys, unsigned int virt, unsigned int size)
		202	{
		203	struct prom_args {
		204	char *service;
		205	int nargs;
		206	int nret;
		207	char *method;
		208	void *mmu_ihandle;
		209	int misc;
		210	unsigned int phys;
		211	unsigned int virt;
		212	unsigned int size;
		213	int ret0;
		214	int ret1;
		215	} args;
		216
		217	if (prom_mmu == 0) {
		218	printk("map() called, no MMU found\n");
		219	return -1;
		220	}
		221	args.service = "call-method";
		222	args.nargs = 6;
		223	args.nret = 2;
		224	args.method = "map";
		225	args.mmu_ihandle = prom_mmu;
		226	args.misc = -1;
		227	args.phys = phys;
		228	args.virt = virt;
		229	args.size = size;
		230	(*prom)(&args);
		231
		232	return (int)args.ret0;
		233	}
		234
		235	int
198	getprop(void phandle, const char name, void *buf, int buflen)	236	getprop(void phandle, const char name, void *buf, int buflen)
199	{	237	{
200	struct prom_args {	238	struct prom_args {
Lines 330-336 Link Here
330	}	368	}
331		369
332	int	370	int
333	printf(char *fmt, ...)	371	printf(const char *fmt, ...)
334	{	372	{
335	va_list args;	373	va_list args;
336	int n;	374	int n;




  define_bool CONFIG_PPC_STD_MMU y
fi

bool 'CPU Frequency scaling' CONFIG_CPU_FREQ
if [ "$CONFIG_CPU_FREQ" = "y" ]; then
   bool '  /proc/sys/cpu/ interface (2.4.)' CONFIG_CPU_FREQ_24_API
   if [ "$CONFIG_CPU_FREQ_24_API" = "n" ]; then
       define_bool CONFIG_CPU_FREQ_26_API y
   fi
   if [ "$CONFIG_ADB_PMU" = "y" ]; then
       bool "  Support for Apple PowerBooks" CONFIG_CPU_FREQ_PMAC
   fi
fi

if [ "$CONFIG_8260" = "y" ]; then
  define_bool CONFIG_SERIAL_CONSOLE y
  bool 'Support for EST8260' CONFIG_EST8260




#
# Automatically generated by make menuconfig: don't edit
#
# CONFIG_UID16 is not set
# CONFIG_RWSEM_GENERIC_SPINLOCK is not set

# CONFIG_8xx is not set
# CONFIG_8260 is not set
CONFIG_PPC_STD_MMU=y
# CONFIG_CPU_FREQ is not set
CONFIG_ALL_PPC=y
# CONFIG_APUS is not set
# CONFIG_SPRUCE is not set

# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set

#
#  
#
# CONFIG_IPX is not set
CONFIG_ATALK=m


# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y

#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y

CONFIG_BLK_DEV_IDEFLOPPY=y
CONFIG_BLK_DEV_IDESCSI=y
# CONFIG_IDE_TASK_IOCTL is not set

#
# IDE chipset support/bugfixes
#
# CONFIG_BLK_DEV_CMD640 is not set
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
# CONFIG_BLK_DEV_ISAPNP is not set

# Joysticks
#
# CONFIG_INPUT_GAMEPORT is not set

#
# Input core support is needed for gameports
#

#
# Input core support is needed for joysticks
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMI_PANIC_EVENT is not set




#
# Automatically generated by make menuconfig: don't edit
#
# CONFIG_UID16 is not set
# CONFIG_RWSEM_GENERIC_SPINLOCK is not set

CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_8260 is not set
CONFIG_PPC_STD_MMU=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_24_API is not set
CONFIG_CPU_FREQ_26_API=y
CONFIG_CPU_FREQ_PMAC=y
CONFIG_ALL_PPC=y
# CONFIG_APUS is not set
# CONFIG_SPRUCE is not set
# CONFIG_LOPEC is not set
# CONFIG_PPLUS is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_SMP is not set
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_TAU_INT is not set
# CONFIG_TAU_AVERAGE is not set
CONFIG_PPC_ISATIMER=y

#
# General setup
#
CONFIG_HIGHMEM=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_SBUS is not set

# Parallel port support
#
# CONFIG_PARPORT is not set
# CONFIG_GEN_RTC is not set
CONFIG_PPC_RTC=y
CONFIG_PPC601_SYNC_FIX=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_PPC_RTAS is not set
# CONFIG_PREP_RESIDUAL is not set
# CONFIG_PROC_PREPRESIDUAL is not set
CONFIG_PPCBUG_NVRAM=y

#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set

#
CONFIG_IP_NF_CONNTRACK=m
CONFIG_IP_NF_FTP=m
# CONFIG_IP_NF_AMANDA is not set
# CONFIG_IP_NF_TFTP is not set
CONFIG_IP_NF_IRC=m
CONFIG_IP_NF_QUEUE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_LIMIT=m
CONFIG_IP_NF_MATCH_MAC=m

CONFIG_IP_NF_MATCH_MARK=m
CONFIG_IP_NF_MATCH_MULTIPORT=m
CONFIG_IP_NF_MATCH_TOS=m
# CONFIG_IP_NF_MATCH_RECENT is not set
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_DSCP=m
CONFIG_IP_NF_MATCH_AH_ESP=m

CONFIG_IP_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_NAT_AMANDA=m
# CONFIG_IP_NF_NAT_LOCAL is not set
CONFIG_IP_NF_NAT_SNMP_BASIC=m
CONFIG_IP_NF_NAT_IRC=m
CONFIG_IP_NF_NAT_FTP=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_TOS=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_DSCP=m
CONFIG_IP_NF_TARGET_MARK=m
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_IP_NF_TARGET_TCPMSS=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
# CONFIG_IP_NF_ARP_MANGLE is not set
CONFIG_IP_NF_COMPAT_IPCHAINS=m
CONFIG_IP_NF_NAT_NEEDED=y
# CONFIG_IP_NF_COMPAT_IPFWADM is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
CONFIG_ATM_CLIP_NO_ICMP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
# CONFIG_VLAN_8021Q is not set

#
#  
#
# CONFIG_IPX is not set
CONFIG_ATALK=m


# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y

#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y

# CONFIG_BLK_DEV_IDETAPE is not set
CONFIG_BLK_DEV_IDEFLOPPY=y
CONFIG_BLK_DEV_IDESCSI=y
CONFIG_IDE_TASK_IOCTL=y

#
# IDE chipset support/bugfixes
#
# CONFIG_BLK_DEV_CMD640 is not set
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
# CONFIG_BLK_DEV_ISAPNP is not set

CONFIG_IDEDMA_PCI_AUTO=y
# CONFIG_IDEDMA_ONLYDISK is not set
CONFIG_BLK_DEV_IDEDMA=y
CONFIG_IDEDMA_PCI_WIP=y
# CONFIG_BLK_DEV_ADMA100 is not set
CONFIG_BLK_DEV_AEC62XX=y
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_WDC_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set

# CONFIG_BLK_DEV_PIIX is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_OPTI621 is not set
CONFIG_BLK_DEV_PDC202XX_OLD=y
CONFIG_PDC202XX_BURST=y
CONFIG_BLK_DEV_PDC202XX_NEW=y
CONFIG_PDC202XX_FORCE=y
# CONFIG_BLK_DEV_RZ1000 is not set
# CONFIG_BLK_DEV_SC1200 is not set
# CONFIG_BLK_DEV_SVWKS is not set

# CONFIG_BLK_DEV_VIA82CXXX is not set
CONFIG_BLK_DEV_SL82C105=y
CONFIG_BLK_DEV_IDE_PMAC=y
CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
CONFIG_BLK_DEV_IDEDMA_PMAC=y
CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO=y
CONFIG_PMU_HD_BLINK=y
CONFIG_BLK_DEV_IDEDMA=y
CONFIG_BLK_DEV_IDEPCI=y
# CONFIG_IDE_CHIPSETS is not set

# SCSI support
#
CONFIG_SCSI=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=y

CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_SR_EXTRA_DEVS=2
CONFIG_CHR_DEV_SG=y

#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
CONFIG_SCSI_CONSTANTS=y

# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AACRAID is not set
CONFIG_SCSI_AIC7XXX=y
CONFIG_AIC7XXX_CMDS_PER_DEVICE=253
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
# CONFIG_AIC7XXX_PROBE_EISA_VL is not set

CONFIG_AIC7XXX_DEBUG_MASK=0
# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
# CONFIG_SCSI_AIC79XX is not set
CONFIG_SCSI_AIC7XXX_OLD=m
# CONFIG_AIC7XXX_OLD_TCQ_ON_BY_DEFAULT is not set
CONFIG_AIC7XXX_OLD_CMDS_PER_DEVICE=8
CONFIG_AIC7XXX_OLD_PROC_STATS=y
# CONFIG_SCSI_DPT_I2O is not set
CONFIG_SCSI_ADVANSYS=m
# CONFIG_SCSI_IN2000 is not set

# CONFIG_SCSI_DEBUG is not set
CONFIG_SCSI_MESH=y
CONFIG_SCSI_MESH_SYNC_RATE=5
CONFIG_SCSI_MESH_RESET_DELAY_MS=4000
CONFIG_SCSI_MAC53C94=y

#

# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
CONFIG_IEEE1394=m

#
# Device Drivers
#

#
#   Texas Instruments PCILynx requires I2C bit-banging
#
CONFIG_IEEE1394_OHCI1394=m

#
# Protocol Drivers
#
CONFIG_IEEE1394_VIDEO1394=m
CONFIG_IEEE1394_SBP2=m
# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
CONFIG_IEEE1394_ETH1394=m
CONFIG_IEEE1394_DV1394=m
CONFIG_IEEE1394_RAWIO=m
# CONFIG_IEEE1394_CMP is not set
# CONFIG_IEEE1394_VERBOSEDEBUG is not set
CONFIG_IEEE1394_OUI_DB=y

#
# Network device support

# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
# CONFIG_ETHERTAP is not set

#

# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_APRICOT is not set
# CONFIG_B44 is not set
# CONFIG_CS89x0 is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set

# CONFIG_SUNDANCE is not set
# CONFIG_SUNDANCE_MMIO is not set
# CONFIG_TLAN is not set
# CONFIG_TC35815 is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_RHINE_MMIO is not set
# CONFIG_WINBOND_840 is not set

CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=m
# CONFIG_PPPOE is not set
# CONFIG_PPPOATM is not set
# CONFIG_SLIP is not set

#

CONFIG_APPLE_AIRPORT=m
# CONFIG_PLX_HERMES is not set
CONFIG_PCI_HERMES=m
# CONFIG_TMD_HERMES is not set
#
# Wireless Pcmcia cards support
#
CONFIG_PCMCIA_HERMES=m
# CONFIG_AIRO_CS is not set
CONFIG_NET_WIRELESS=y

# CONFIG_AIRONET4500_CS is not set

#
# ATM drivers
#
# CONFIG_ATM_TCP is not set
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_FIRESTREAM is not set
# CONFIG_ATM_ZATM is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_AMBASSADOR is not set
# CONFIG_ATM_HORIZON is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E_MAYBE is not set
# CONFIG_ATM_HE is not set

#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set

# IrDA (infrared) support
#
CONFIG_IRDA=m

#
# IrDA protocols
#
CONFIG_IRLAN=m
CONFIG_IRNET=m
CONFIG_IRCOMM=m
CONFIG_IRDA_ULTRA=y

#
# IrDA options
#
CONFIG_IRDA_CACHE_LAST_LSAP=y
CONFIG_IRDA_FAST_RR=y
# CONFIG_IRDA_DEBUG is not set

#
# Infrared-port device drivers
#

#
# SIR device drivers
#
CONFIG_IRTTY_SIR=m
CONFIG_IRPORT_SIR=m

#
# Dongle support
#
# CONFIG_DONGLE is not set

#
# FIR device drivers
#
# CONFIG_USB_IRDA is not set
# CONFIG_NSC_FIR is not set
# CONFIG_WINBOND_FIR is not set

#
# ISDN subsystem
#
CONFIG_ISDN=m
CONFIG_ISDN_BOOL=y
CONFIG_ISDN_PPP=y
# CONFIG_IPPP_FILTER is not set
CONFIG_ISDN_PPP_VJ=y
CONFIG_ISDN_MPP=y
CONFIG_ISDN_PPP_BSDCOMP=m
# CONFIG_ISDN_AUDIO is not set

#
# ISDN feature submodules
#
# CONFIG_ISDN_DRV_LOOP is not set
# CONFIG_ISDN_DIVERSION is not set

#
# Passive ISDN cards
#
CONFIG_ISDN_DRV_HISAX=m
CONFIG_ISDN_HISAX=y
# CONFIG_HISAX_EURO is not set
# CONFIG_HISAX_1TR6 is not set
# CONFIG_HISAX_NI1 is not set
CONFIG_HISAX_MAX_CARDS=8
# CONFIG_HISAX_TELESPCI is not set
# CONFIG_HISAX_S0BOX is not set
# CONFIG_HISAX_FRITZPCI is not set
# CONFIG_HISAX_AVM_A1_PCMCIA is not set
# CONFIG_HISAX_ELSA is not set
# CONFIG_HISAX_DIEHLDIVA is not set
# CONFIG_HISAX_SEDLBAUER is not set
# CONFIG_HISAX_NETJET is not set
# CONFIG_HISAX_NETJET_U is not set
# CONFIG_HISAX_NICCY is not set
# CONFIG_HISAX_BKM_A4T is not set
# CONFIG_HISAX_SCT_QUADRO is not set
CONFIG_HISAX_GAZEL=y
# CONFIG_HISAX_HFC_PCI is not set
# CONFIG_HISAX_W6692 is not set
# CONFIG_HISAX_HFC_SX is not set
# CONFIG_HISAX_ENTERNOW_PCI is not set
# CONFIG_HISAX_DEBUG is not set
# CONFIG_HISAX_SEDLBAUER_CS is not set
# CONFIG_HISAX_ELSA_CS is not set
# CONFIG_HISAX_AVM_A1_CS is not set
CONFIG_HISAX_ST5481=m
# CONFIG_HISAX_FRITZ_PCIPNP is not set
# CONFIG_USB_AUERISDN is not set

#
# Active ISDN cards
#
# CONFIG_ISDN_DRV_ICN is not set
# CONFIG_ISDN_DRV_PCBIT is not set
# CONFIG_ISDN_DRV_SC is not set
# CONFIG_ISDN_DRV_ACT2000 is not set
# CONFIG_ISDN_DRV_EICON is not set
# CONFIG_ISDN_DRV_TPAM is not set
# CONFIG_ISDN_CAPI is not set
# CONFIG_HYSDN is not set
# CONFIG_HYSDN_CAPI is not set

#
# Old CD-ROM drivers (not SCSI, not IDE)

#
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_FB_RIVA=y
# CONFIG_FB_CLGEN is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_PM3 is not set

CONFIG_FB_IMSTT=y
# CONFIG_FB_S3TRIO is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_MATROX is not set
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
# CONFIG_FB_MATROX_G450 is not set
CONFIG_FB_MATROX_G100A=y
CONFIG_FB_MATROX_G100=y
# CONFIG_FB_MATROX_I2C is not set
# CONFIG_FB_MATROX_MAVEN is not set
CONFIG_FB_MATROX_PROC=y
# CONFIG_FB_MATROX_MULTIHEAD is not set
CONFIG_FB_ATY=y
CONFIG_FB_ATY_GX=y
CONFIG_FB_ATY_CT=y

CONFIG_PMAC_BACKLIGHT=y
CONFIG_MAC_FLOPPY=y
CONFIG_MAC_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
CONFIG_ADB=y
CONFIG_ADB_MACIO=y
CONFIG_INPUT_ADBHID=y
# CONFIG_MAC_ADBKEYCODES is not set
CONFIG_MAC_EMUMOUSEBTN=y
CONFIG_MAC_HID=y
# CONFIG_ANSLCD is not set

# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_BRIQ_PANEL is not set

#
# I2C support
#
CONFIG_I2C=y
# CONFIG_I2C_ALGOBIT is not set
# CONFIG_I2C_ALGOPCF is not set
CONFIG_I2C_KEYWEST=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PROC=y

#
# Mice

# CONFIG_INPUT_EMU10K1 is not set
# CONFIG_INPUT_SERIO is not set
# CONFIG_INPUT_SERPORT is not set

#
# Joysticks
#
# CONFIG_INPUT_ANALOG is not set
# CONFIG_INPUT_A3D is not set
# CONFIG_INPUT_ADI is not set

# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
CONFIG_AGP=m
# CONFIG_AGP_INTEL is not set
# CONFIG_AGP_I810 is not set
# CONFIG_AGP_VIA is not set
# CONFIG_AGP_AMD is not set
# CONFIG_AGP_AMD_8151 is not set
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_ALI is not set
# CONFIG_AGP_SWORKS is not set
CONFIG_AGP_UNINORTH=y
# CONFIG_DRM is not set

#
# PCMCIA character devices
#
CONFIG_PCMCIA_SERIAL_CS=m
# CONFIG_SYNCLINK_CS is not set

#
# Multimedia devices
#
CONFIG_VIDEO_DEV=m

#
# Video For Linux
#
# CONFIG_VIDEO_PROC_FS is not set
# CONFIG_I2C_PARPORT is not set
# CONFIG_VIDEO_BT848 is not set
# CONFIG_VIDEO_PMS is not set
CONFIG_VIDEO_PLANB=m
# CONFIG_VIDEO_CPIA is not set
# CONFIG_VIDEO_SAA5249 is not set
# CONFIG_TUNER_3036 is not set
# CONFIG_VIDEO_STRADIS is not set
# CONFIG_VIDEO_ZORAN is not set
# CONFIG_VIDEO_ZORAN_BUZ is not set
# CONFIG_VIDEO_ZORAN_DC10 is not set
# CONFIG_VIDEO_ZORAN_LML33 is not set
# CONFIG_VIDEO_ZR36120 is not set
# CONFIG_VIDEO_MEYE is not set

#
# Radio Adapters
#
# CONFIG_RADIO_GEMTEK_PCI is not set
# CONFIG_RADIO_MAXIRADIO is not set
# CONFIG_RADIO_MAESTRO is not set
# CONFIG_RADIO_MIROPCM20 is not set

#
# File systems
#
# CONFIG_QUOTA is not set
# CONFIG_QFMT_V2 is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set

# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BEFS_DEBUG is not set
# CONFIG_BFS_FS is not set

# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y

# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_ROOT_NFS is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set

# Native Language Support
#
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set

# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=m

#
# Sound

CONFIG_SOUND=m
CONFIG_DMASOUND_PMAC=m
CONFIG_DMASOUND=m
CONFIG_I2C=m
CONFIG_I2C_KEYWEST=m
# CONFIG_SOUND_ALI5455 is not set
# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set

#
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_BANDWIDTH is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
CONFIG_USB_OHCI=y
CONFIG_USB_AUDIO=m
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_MIDI is not set
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_DPCM=y
CONFIG_USB_STORAGE_HP8200e=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m

#
# USB Human Interface Devices (HID)
#
CONFIG_USB_HID=y
CONFIG_USB_HIDINPUT=y
CONFIG_USB_HIDDEV=y
# CONFIG_USB_AIPTEK is not set
# CONFIG_USB_WACOM is not set
# CONFIG_USB_KBTAB is not set
# CONFIG_USB_POWERMATE is not set

#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
CONFIG_USB_SCANNER=m
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
# CONFIG_USB_IBMCAM is not set
# CONFIG_USB_KONICAWC is not set
CONFIG_USB_OV511=m
CONFIG_USB_PWC=m
# CONFIG_USB_SE401 is not set
# CONFIG_USB_STV680 is not set
# CONFIG_USB_VICAM is not set
# CONFIG_USB_DSBR is not set
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_AX8817X is not set
CONFIG_USB_CDCETHER=m
# CONFIG_USB_USBNET is not set

#
# USB port drivers
#
# CONFIG_USB_USS720 is not set

#

# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set

# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
# CONFIG_USB_SERIAL_OMNINET is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_TIGL is not set
# CONFIG_USB_BRLVGER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_SPEEDTOUCH is not set

#
# Bluetooth support

# CONFIG_BLUEZ is not set

#
# Cryptographic options
#
# CONFIG_CRYPTO is not set

#
# Library routines
#
# CONFIG_CRC32 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y


# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_WAITQ is not set
# CONFIG_KGDB is not set
# CONFIG_XMON is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_MORE_COMPILE_OPTIONS is not set
CONFIG_BOOTX_TEXT=y

Lines 45-51 Link Here

(-)linux-2.4.22/arch/ppc/kernel/Makefile (-1 / +1 lines)
45	obj-$(CONFIG_PCI) += pci-dma.o	45	obj-$(CONFIG_PCI) += pci-dma.o
46	obj-$(CONFIG_KGDB) += ppc-stub.o	46	obj-$(CONFIG_KGDB) += ppc-stub.o
47	obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o	47	obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o
48	obj-$(CONFIG_SMP) += smp.o	48	obj-$(CONFIG_SMP) += smp.o smp-tbsync.o
49	obj-$(CONFIG_TAU) += temp.o	49	obj-$(CONFIG_TAU) += temp.o
50	ifeq ($(CONFIG_SERIAL)$(CONFIG_GEN550),yy)	50	ifeq ($(CONFIG_SERIAL)$(CONFIG_GEN550),yy)
51	obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o	51	obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o




static unsigned char vga_font[cmapsz];

int boot_text_mapped;
int force_printk_to_btext;

boot_infos_t disp_bi;

extern char *klimit;

#define BTEXT
#define BTDATA
 * chrp only uses it during early boot.
 */
#ifdef CONFIG_XMON
#define BTEXT	__pmac
#define BTDATA	__pmacdata
#else
#define BTEXT	__init
#define BTDATA	__initdata
#endif /* CONFIG_XMON */

/*
 * This is called only when we are booted via BootX.

Lines 258-263 Link Here

(-)linux-2.4.22/arch/ppc/kernel/entry.S (+6 lines)
258	addi r1,r1,INT_FRAME_SIZE	258	addi r1,r1,INT_FRAME_SIZE
259	blr	259	blr
260		260
		261	.globl syscall_direct_return
		262	syscall_direct_return:
		263	addi r1,r3,-STACK_FRAME_OVERHEAD
		264	/* XXX should check syscall tracing here */
		265	b ret_from_except
		266
261	.globl ret_from_fork	267	.globl ret_from_fork
262	ret_from_fork:	268	ret_from_fork:
263	bl schedule_tail	269	bl schedule_tail




#endif

/* Machine check */
BEGIN_FTR_SECTION
	DSSALL
	sync
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data access exception. */

	/* enable use of AltiVec after return */
	oris	r23,r23,MSR_VEC@h
	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
	li	r4,1
	li	r20,THREAD_VSCR
	stw	r4,THREAD_USED_VR(r5)
	LVX(vr0,r20,r5)
	MTVSCR(vr0)
	REST_32VR(0,r20,r5)

Lines 1-4 Link Here

(-)linux-2.4.22/arch/ppc/kernel/irq.c (-1 / +28 lines)
1	/*	1	/*
2	* arch/ppc/kernel/irq.c	2	* arch/ppc/kernel/irq.c
3	*	3	*
4	* Derived from arch/i386/kernel/irq.c	4	* Derived from arch/i386/kernel/irq.c
Lines 75-80 Link Here
75	unsigned long ppc_lost_interrupts[NR_MASK_WORDS];	75	unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
76	atomic_t ppc_n_lost_interrupts;	76	atomic_t ppc_n_lost_interrupts;
77		77
		78	#ifdef CONFIG_DEBUG_SPINLOCK
		79	int debug_long_irqlock;
		80	#endif /* CONFIG_DEBUG_SPINLOCK */
		81
78	/* nasty hack for shared irq's since we need to do kmalloc calls but	82	/* nasty hack for shared irq's since we need to do kmalloc calls but
79	* can't very early in the boot when we need to do a request irq.	83	* can't very early in the boot when we need to do a request irq.
80	* this needs to be removed.	84	* this needs to be removed.
Lines 578-583 Link Here
578	unsigned long *stack;	582	unsigned long *stack;
579	int cpu = smp_processor_id();	583	int cpu = smp_processor_id();
580		584
		585	#ifdef CONFIG_XMON
		586	xmon_printf("\n%s, CPU %d:\n", str, cpu);
		587	xmon_printf("irq: %d [%d %d]\n",
		588	atomic_read(&global_irq_count),
		589	local_irq_count(0),
		590	local_irq_count(1));
		591	xmon_printf("bh: %d [%d %d]\n",
		592	atomic_read(&global_bh_count),
		593	local_bh_count(0),
		594	local_bh_count(1));
		595	stack = (unsigned long *) &str;
		596	for (i = 40; i ; i--) {
		597	unsigned long x = *++stack;
		598	if (x > (unsigned long) &init_task_union && x < (unsigned long) &vsprintf) {
		599	xmon_printf("<[%08lx]> ", x);
		600	}
		601	}
		602	#endif /* CONFIG_XMON */
581	printk("\n%s, CPU %d:\n", str, cpu);	603	printk("\n%s, CPU %d:\n", str, cpu);
582	printk("irq: %d [%d %d]\n",	604	printk("irq: %d [%d %d]\n",
583	atomic_read(&global_irq_count),	605	atomic_read(&global_irq_count),
Lines 662-667 Link Here
662	*/	684	*/
663	void synchronize_bh(void)	685	void synchronize_bh(void)
664	{	686	{
		687	smp_mb();
665	if (atomic_read(&global_bh_count) && !in_interrupt())	688	if (atomic_read(&global_bh_count) && !in_interrupt())
666	wait_on_bh();	689	wait_on_bh();
667	}	690	}
Lines 675-680 Link Here
675	*/	698	*/
676	void synchronize_irq(void)	699	void synchronize_irq(void)
677	{	700	{
		701	smp_mb();
678	if (atomic_read(&global_irq_count)) {	702	if (atomic_read(&global_irq_count)) {
679	/* Stupid approach */	703	/* Stupid approach */
680	cli();	704	cli();
Lines 694-699 Link Here
694	do {	718	do {
695	do {	719	do {
696	if (loops-- == 0) {	720	if (loops-- == 0) {
		721	#ifdef CONFIG_XMON
		722	xmon_printf("get_irqlock(%d) waiting, global_irq_holder=%d\n", cpu, global_irq_holder);
		723	#endif
697	printk("get_irqlock(%d) waiting, global_irq_holder=%d\n", cpu, global_irq_holder);	724	printk("get_irqlock(%d) waiting, global_irq_holder=%d\n", cpu, global_irq_holder);
698	#ifdef CONFIG_XMON	725	#ifdef CONFIG_XMON
699	xmon(0);	726	xmon(0);

Lines 43-48 Link Here

(-)linux-2.4.22/arch/ppc/kernel/m8xx_setup.c (+1 lines)
43	#include <asm/machdep.h>	43	#include <asm/machdep.h>
44	#include <asm/bootinfo.h>	44	#include <asm/bootinfo.h>
45	#include <asm/time.h>	45	#include <asm/time.h>
		46	#include <asm/i8259.h>
46		47
47	#include "ppc8xx_pic.h"	48	#include "ppc8xx_pic.h"
48		49




	mr	r4,r24
	bctr

#ifdef CONFIG_CPU_FREQ_PMAC

/* This gets called by via-pmu.c to switch the PLL selection
 * on 750fx CPU.
 */
_GLOBAL(low_choose_750fx_pll)
	/* Clear MSR:EE */
	mfmsr	r7
	rlwinm	r0,r7,0,17,15
	mtmsr	r0

	/* If switching to PLL1, disable HID0:BTIC */
	cmpli	cr0,r3,0
	beq	1f
	mfspr	r5,HID0
	rlwinm	r5,r5,0,27,25
	sync
	mtspr	HID0,r5
	isync
	sync
	
1:
	/* Calc new HID1 value */
	mfspr	r4,SPRN_HID1	/* Build a HID1:PS bit from parameter */
	rlwinm	r5,r3,16,15,15	/* Clear out HID1:PS from value read */
	rlwinm	r4,r4,0,16,14	/* Could have I used rlwimi here ? */
	or	r4,r4,r5
	mtspr	SPRN_HID1,r4

	/* Store new HID1 image */
	lwz	r6,PROCESSOR(r2)
	slwi	r6,r6,2
	addis	r6,r6,nap_save_hid1@ha
	stw	r4,nap_save_hid1@l(r6)

	/* If switching to PLL0, enable HID0:BTIC */
	cmpli	cr0,r3,0
	bne	1f
	mfspr	r5,HID0
	ori	r5,r5,HID0_BTIC
	sync
	mtspr	HID0,r5
	isync
	sync
	
1:	
	/* Return */		
	mtmsr	r7
	blr

#endif /* CONFIG_CPU_FREQ_PMAC */


/* void __save_flags_ptr(unsigned long *flags) */
_GLOBAL(__save_flags_ptr)
	mfmsr	r4

	.long sys_ni_syscall 	/*	reserved for sys_io_getevents */
	.long sys_ni_syscall 	/* 230	reserved for sys_io_submit */
	.long sys_ni_syscall 	/*	reserved for sys_io_cancel */
	.long sys_ni_syscall	/*	reserved for sys_set_tid_address */
	.long sys_ni_syscall	/*	reserved for sys_fadvise64 */
	.long sys_ni_syscall	/*	reserved for sys_exit_group */
	.long sys_ni_syscall	/* 235	reserved for sys_lookup_dcookie */
	.long sys_ni_syscall	/*	reserved for sys_epoll_create */
	.long sys_ni_syscall	/*	reserved for sys_epoll_ctl */
	.long sys_ni_syscall	/*	reserved for sys_epoll_wait */
	.long sys_ni_syscall	/*	reserved for sys_remap_file_pages */
	.long sys_ni_syscall	/* 240	reserved for sys_timer_create */
	.long sys_ni_syscall	/*	reserved for sys_timer_settime */
	.long sys_ni_syscall	/*	reserved for sys_timer_gettime */
	.long sys_ni_syscall	/*	reserved for sys_timer_getoverrun */
	.long sys_ni_syscall	/*	reserved for sys_timer_delete */
	.long sys_ni_syscall	/* 245	reserved for sys_clock_settime */
	.long sys_ni_syscall	/*	reserved for sys_clock_gettime */
	.long sys_ni_syscall	/*	reserved for sys_clock_getres */
	.long sys_ni_syscall	/*	reserved for sys_clock_nanosleep */
	.long sys_swapcontext

	.rept NR_syscalls-(.-sys_call_table)/4
		.long sys_ni_syscall

Lines 56-61 Link Here

(-)linux-2.4.22/arch/ppc/kernel/mk_defs.c (+1 lines)
56	DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0]));	56	DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0]));
57	DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));	57	DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
58	DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr));	58	DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr));
		59	DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
59	#endif /* CONFIG_ALTIVEC */	60	#endif /* CONFIG_ALTIVEC */
60	#ifdef CONFIG_4xx	61	#ifdef CONFIG_4xx
61	DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));	62	DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));

Lines 870-875 Link Here

(-)linux-2.4.22/arch/ppc/kernel/open_pic.c (+17 lines)
870	static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];	870	static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
871	static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];	871	static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
872		872
		873	static void openpic_cached_enable_irq(u_int irq)
		874	{
		875	check_arg_irq(irq);
		876	save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
		877	}
		878
		879	static void openpic_cached_disable_irq(u_int irq)
		880	{
		881	check_arg_irq(irq);
		882	save_irq_src_vp[irq - open_pic_irq_offset] \|= OPENPIC_MASK;
		883	}
873	void __pmac	884	void __pmac
874	openpic_sleep_save_intrs(void)	885	openpic_sleep_save_intrs(void)
875	{	886	{
Lines 878-883 Link Here
878		889
879	spin_lock_irqsave(&openpic_setup_lock, flags);	890	spin_lock_irqsave(&openpic_setup_lock, flags);
880		891
		892	open_pic.enable = openpic_cached_enable_irq;
		893	open_pic.disable = openpic_cached_disable_irq;
		894
881	for (i=0; i<NumProcessors; i++) {	895	for (i=0; i<NumProcessors; i++) {
882	save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);	896	save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
883	openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,	897	openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
Lines 921-926 Link Here
921	openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,	935	openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
922	save_cpu_task_pri[i]);	936	save_cpu_task_pri[i]);
923		937
		938	open_pic.enable = openpic_enable_irq;
		939	open_pic.disable = openpic_disable_irq;
		940
924	spin_unlock_irqrestore(&openpic_setup_lock, flags);	941	spin_unlock_irqrestore(&openpic_setup_lock, flags);
925	}	942	}
926	#endif /* CONFIG_PMAC_PBOOK */	943	#endif /* CONFIG_PMAC_PBOOK */

Lines 1-5 Link Here

(-)linux-2.4.22/arch/ppc/kernel/pci.c (-5 / +18 lines)
1	/*	1	/*
2	* Common pmac/prep/chrp pci routines. -- Cort	2	* Common PCI code for PPC architecture
3	*/	3	*/
4		4
5	#include <linux/config.h>	5	#include <linux/config.h>
Lines 22-28 Link Here
22	#include <asm/irq.h>	22	#include <asm/irq.h>
23	#include <asm/uaccess.h>	23	#include <asm/uaccess.h>
24		24
25	#undef DEBUG	25	#define DEBUG
26		26
27	#ifdef DEBUG	27	#ifdef DEBUG
28	#define DBG(x...) printk(x)	28	#define DBG(x...) printk(x)
Lines 116-121 Link Here
116	struct pci_controller* hose = dev->sysdata;	116	struct pci_controller* hose = dev->sysdata;
117	unsigned long io_offset;	117	unsigned long io_offset;
118		118
		119	if (dev->vendor == PCI_VENDOR_ID_APPLE && dev->device == PCI_DEVICE_ID_APPLE_KEYLARGO) {
		120	printk("trying to reloc keylargo !! skipping\n");
		121	return;
		122	}
119	new = res->start;	123	new = res->start;
120	res->flags &= ~IORESOURCE_UNSET;	124	res->flags &= ~IORESOURCE_UNSET;
121	if (hose && res->flags & IORESOURCE_IO) {	125	if (hose && res->flags & IORESOURCE_IO) {
Lines 217-223 Link Here
217	}	221	}
218	if (dev->device == PCI_DEVICE_ID_TI_1210 \|\|	222	if (dev->device == PCI_DEVICE_ID_TI_1210 \|\|
219	dev->device == PCI_DEVICE_ID_TI_1211 \|\|	223	dev->device == PCI_DEVICE_ID_TI_1211 \|\|
220	dev->device == PCI_DEVICE_ID_TI_1410) {	224	dev->device == PCI_DEVICE_ID_TI_1410 \|\|
		225	dev->device == PCI_DEVICE_ID_TI_1510) {
221	u8 val;	226	u8 val;
222	/* 0x8c == TI122X_IRQMUX, 2 says to route the INTA	227	/* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
223	signal out the MFUNC0 pin */	228	signal out the MFUNC0 pin */
Lines 563-570 Link Here
563	{	568	{
564	struct resource pr, r = &dev->resource[idx];	569	struct resource pr, r = &dev->resource[idx];
565		570
566	DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",	571	DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx), vd: %04x, dev: %04x\n",
567	dev->slot_name, idx, r->start, r->end, r->flags);	572	dev->slot_name, idx, r->start, r->end, r->flags,
		573	dev->vendor, dev->device);
568	pr = pci_find_parent_resource(dev, r);	574	pr = pci_find_parent_resource(dev, r);
569	if (!pr \|\| request_resource(pr, r) < 0) {	575	if (!pr \|\| request_resource(pr, r) < 0) {
570	printk(KERN_ERR "PCI: Cannot allocate resource region %d"	576	printk(KERN_ERR "PCI: Cannot allocate resource region %d"
Lines 1029-1034 Link Here
1029	}	1035	}
1030	ranges += np;	1036	ranges += np;
1031	}	1037	}
		1038	DBG("hose %s, pci_mem_offset: %08lx, start0: %08lx\n",
		1039	dev->name, hose->pci_mem_offset, hose->mem_resources[0].start);
		1040	DBG(" io_base_virt: %p, io_base_phys: %08lx, isa_mem_base: %08lx\n",
		1041	hose->io_base_virt, hose->io_base_phys, isa_mem_base);
1032	}	1042	}
1033		1043
1034	/* We create the "pci-OF-bus-map" property now so it appears in the	1044	/* We create the "pci-OF-bus-map" property now so it appears in the
Lines 1341-1346 Link Here
1341	return PCI_SLOT(dev->devfn);	1351	return PCI_SLOT(dev->devfn);
1342	}	1352	}
1343		1353
		1354	/* Where does that come from ? Doesn't seem to be correct for us, but we
		1355	* don't use it anyway so ... -BenH.
		1356	*/
1344	void __init	1357	void __init
1345	pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)	1358	pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
1346	{	1359	{




#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>
#include <linux/ide.h>

#include <asm/page.h>

extern int pmac_newworld;
extern int sys_sigreturn(struct pt_regs *regs);

extern long long __ashrdi3(long long, int);
extern long long __ashldi3(long long, int);
extern long long __lshrdi3(long long, int);

int abs(int);

extern unsigned char __res[];

EXPORT_SYMBOL(strcmp);
EXPORT_SYMBOL(strncmp);
EXPORT_SYMBOL(strcasecmp);
EXPORT_SYMBOL(__div64_32);

/* EXPORT_SYMBOL(csum_partial); already in net/netsyms.c */
EXPORT_SYMBOL(csum_partial_copy_generic);

EXPORT_SYMBOL(flush_icache_user_range);
EXPORT_SYMBOL(flush_icache_page);
EXPORT_SYMBOL(flush_dcache_page);
EXPORT_SYMBOL(local_flush_tlb_page);
EXPORT_SYMBOL(xchg_u32);
#ifdef CONFIG_ALTIVEC
EXPORT_SYMBOL(last_task_used_altivec);

EXPORT_SYMBOL_NOVERS(memscan);
EXPORT_SYMBOL_NOVERS(memcmp);
EXPORT_SYMBOL_NOVERS(memchr);
EXPORT_SYMBOL_NOVERS(__div64_32);

EXPORT_SYMBOL(abs);


EXPORT_SYMBOL(get_wchan);
EXPORT_SYMBOL(console_drivers);
#ifdef CONFIG_XMON
extern void xmon_printf(const char *fmt, ...);
EXPORT_SYMBOL(xmon);
EXPORT_SYMBOL(xmon_printf);
#endif

EXPORT_SYMBOL(ret_from_intercept);
EXPORT_SYMBOL(cur_cpu_spec);
#if defined(CONFIG_ALL_PPC)
extern int map_page(unsigned long va, unsigned long pa, int flags);

EXPORT_SYMBOL(map_page);
EXPORT_SYMBOL(get_vm_area);
extern unsigned long agp_special_page;
EXPORT_SYMBOL_NOVERS(agp_special_page);
EXPORT_SYMBOL(ioremap_bot);
EXPORT_SYMBOL(local_flush_tlb_all);
#endif /* defined(CONFIG_ALL_PPC) */


Lines 417-422 Link Here

(-)linux-2.4.22/arch/ppc/kernel/process.c (-3 / +9 lines)
417	memset(current->thread.vr, 0, sizeof(current->thread.vr));	417	memset(current->thread.vr, 0, sizeof(current->thread.vr));
418	memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));	418	memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
419	current->thread.vrsave = 0;	419	current->thread.vrsave = 0;
		420	current->thread.used_vr = 0;
420	#endif /* CONFIG_ALTIVEC */	421	#endif /* CONFIG_ALTIVEC */
421	}	422	}
422		423
Lines 506-519 Link Here
506	if (sp == NULL)	507	if (sp == NULL)
507	asm("mr %0,1" : "=r" (sp));	508	asm("mr %0,1" : "=r" (sp));
508	printk("Call backtrace: ");	509	printk("Call backtrace: ");
		510	if (sp == NULL)
		511	sp = (unsigned long *)_get_SP();
509	while (sp) {	512	while (sp) {
510	if (__get_user( i, &sp[1] ))	513	if (__get_user(sp, (unsigned long **)sp))
		514	break;
		515	if (sp == NULL)
		516	break;
		517	if (__get_user(i, &sp[1]))
511	break;	518	break;
512	if (cnt++ % 7 == 0)	519	if (cnt++ % 7 == 0)
513	printk("\n");	520	printk("\n");
514	printk("%08lX ", i);	521	printk("%08lX ", i);
515	if (cnt > 32) break;	522	if (cnt > 32)
516	if (__get_user(sp, (unsigned long **)sp))
517	break;	523	break;
518	}	524	}
519	printk("\n");	525	printk("\n");




	struct task_struct *tsk = current;
	DECLARE_WAITQUEUE(wait, tsk);

	__set_task_state(tsk, TASK_UNINTERRUPTIBLE);
	add_wait_queue_exclusive(&sem->wait, &wait);
	smp_wmb();

	/*
	 * Try to get the semaphore.  If the count is > 0, then we've

	 */
	while (__sem_update_count(sem, -1) <= 0) {
		schedule();
		set_task_state(tsk, TASK_UNINTERRUPTIBLE);
	}
	remove_wait_queue(&sem->wait, &wait);
	__set_task_state(tsk, TASK_RUNNING);

	/*
	 * If there are any more sleepers, wake one of them up so

	struct task_struct *tsk = current;
	DECLARE_WAITQUEUE(wait, tsk);

	__set_task_state(tsk, TASK_INTERRUPTIBLE);
	add_wait_queue_exclusive(&sem->wait, &wait);
	smp_wmb();

	while (__sem_update_count(sem, -1) <= 0) {
		if (signal_pending(current)) {

			break;
		}
		schedule();
		set_task_state(tsk, TASK_INTERRUPTIBLE);
	}
	tsk->state = TASK_RUNNING;
	remove_wait_queue(&sem->wait, &wait);
	__set_task_state(tsk, TASK_RUNNING);
	
	wake_up(&sem->wait);
	return retval;
}




struct ide_machdep_calls ppc_ide_md;
char *sysmap;
unsigned long sysmap_size;
int no_nap;

/* Used with the BI_MEMSIZE bootinfo parameter to store the memory
   size value reported by the boot loader. */

		return 0;
	pvr = cpu_data[i].pvr;
	lpj = cpu_data[i].loops_per_jiffy;
	seq_printf(m, "processor\t: %u\n", i);
#else
	pvr = mfspr(PVR);
	lpj = loops_per_jiffy;

	      unsigned long r6, unsigned long r7)
{
#ifdef CONFIG_BOOTX_TEXT
	extern int force_printk_to_btext;
	if (boot_text_mapped) {
		btext_clearscreen();
		btext_welcome();

	}
	cmd_line[sizeof(cmd_line) - 1] = 0;

	/* Debug stuff, do not merge ! */
#ifdef CONFIG_ADB_PMU
	if (strstr(cmd_line, "fake_sleep")) {
		extern int __fake_sleep;
		__fake_sleep = 1;
	}
#endif /* CONFIG_ADB_PMU */	
#ifdef CONFIG_ADB
	if (strstr(cmd_line, "adb_sync")) {
		extern int __adb_probe_sync;
		__adb_probe_sync = 1;
	}
#endif /* CONFIG_ADB */	
	if (strstr(cmd_line, "nol3") && cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR)
		_set_L3CR(0);
	if (strstr(cmd_line, "nonap"))
		cur_cpu_spec[0]->cpu_features &= ~CPU_FTR_CAN_NAP;
#ifdef CONFIG_BOOTX_TEXT
	if (strstr(cmd_line, "printkbtext"))
		force_printk_to_btext = 1;
#endif
	switch (_machine) {
	case _MACH_Pmac:
		pmac_init(r3, r4, r5, r6, r7);





#define GP_REGS_SIZE	MIN(sizeof(elf_gregset_t), sizeof(struct pt_regs))

extern void syscall_direct_return(struct pt_regs *regs);
 * These are the flags in the MSR that the user is allowed to change
 * by modifying the saved value of the MSR on the stack.  SE and BE
 * should not be in this list since gdb may want to change these.  I.e,
 * you should be able to step out of a signal handler to see what
 * instruction executes next after the signal handler completes.
 * Alternately, if you stepped into a signal handler, you should be
 * able to continue 'til the next breakpoint from within the signal
 * handler, even if the handler returns.
 */
#define MSR_USERCHANGE	(MSR_FE0 | MSR_FE1)

int do_signal(sigset_t *oldset, struct pt_regs *regs);


			 * do_signal() has set R3 to the signal number (the
			 * first argument of the signal handler), so don't
			 * overwrite that with EINTR !
			 * In the other cases, do_signal() doesn't touch 
			 * R3, so it's still set to -EINTR (see above).
			 */
			return regs->gpr[3];



int
sys_sigaltstack(const stack_t *uss, stack_t *uoss, int r5, int r6,
		int r7, int r8, struct pt_regs *regs)
{
	struct pt_regs *regs = (struct pt_regs *) &uss;
	return do_sigaltstack(uss, uoss, regs->gpr[1]);
}

int 
sys_sigaction(int sig, const struct old_sigaction *act,
	      struct old_sigaction *oact)
{

 * When we have signals to deliver, we set up on the
 * user stack, going down from the original stack pointer:
 *	a sigregs struct
 *	a sigcontext struct
 *	a gap of __SIGNAL_FRAMESIZE bytes
 *
 * Each of these things must be a multiple of 16 bytes in size.
 *
 */
struct sigregs {
	struct mcontext	mctx;		/* all the register values */
	double		fp_regs[ELF_NFPREG];
	unsigned long	tramp[2];
	/* Programs using the rs6000/xcoff abi can save up to 19 gp regs
	   and 18 fp regs below sp before decrementing it. */
	int		abigap[56];
};

/* We use the mc_pad field for the signal return trampoline. */
#define tramp	mc_pad
	unsigned long	_unused[2];
	struct siginfo *pinfo;
	void *puc;
	struct siginfo info;
	struct ucontext uc;
};


/*
 *  When we have rt signals to deliver, we set up on the
 *  user stack, going down from the original stack pointer:
 *	one rt_sigframe struct (siginfo + ucontext + ABI gap)
 *	a gap of __SIGNAL_FRAMESIZE+16 bytes
 *  (the +16 is to get the siginfo and ucontext in the same
 *  positions as in older kernels).
 *
 *  Each of these things must be a multiple of 16 bytes in size.
 *
 */
struct rt_sigframe
{
	struct siginfo info;
	struct ucontext uc;
	/* Programs using the rs6000/xcoff abi can save up to 19 gp regs
	   and 18 fp regs below sp before decrementing it. */
	int		abigap[56];
};
	stack_t st;
	unsigned long prevsp;

/*
 * Save the current user registers on the user stack.
 * We only save the altivec registers if the process has used
 * altivec instructions at some point.
 */
static int
save_user_regs(struct pt_regs *regs, struct mcontext *frame, int sigret, int mctxsize)
{
	if (mctxsize && mctxsize < sizeof(struct mcontext))
		return 1;

	/* save general and floating-point registers */
	if (regs->msr & MSR_FP)
		giveup_fpu(current);
	if (__copy_to_user(&frame->mc_gregs, regs, GP_REGS_SIZE)
	    || __copy_to_user(&frame->mc_fregs, current->thread.fpr,
			      ELF_NFPREG * sizeof(double)))
		return 1;

	current->thread.fpscr = 0;	/* turn off all fp exceptions */

#ifdef CONFIG_ALTIVEC
	/* save altivec registers */
	if (current->thread.used_vr) {
		if (regs->msr & MSR_VEC)
			giveup_altivec(current);
		if (__copy_to_user(&frame->mc_vregs, current->thread.vr,
				   ELF_NVRREG * sizeof(vector128)))
			return 1;
		/* set MSR_VEC in the saved MSR value to indicate that
		   frame->mc_vregs contains valid data */
		if (__put_user(regs->msr | MSR_VEC, &frame->mc_gregs[PT_MSR]))
			return 1;
	}
	/* else assert((regs->msr & MSR_VEC) == 0) */

	/* We always copy to/from vrsave, it's 0 if we don't have or don't
	 * use altivec. Since VSCR only contains 32 bits saved in the least
	 * significant bits of a vector, we "cheat" and stuff VRSAVE in the
	 * most significant bits of that same vector. --BenH
	 */
	if (__put_user(current->thread.vrsave, (u32 *)&frame->mc_vregs[32]))
		return 1;
#endif /* CONFIG_ALTIVEC */

	if (sigret) {
		/* Set up the sigreturn trampoline: li r0,sigret; sc */
		if (__put_user(0x38000000UL + sigret, &frame->tramp[0])
		    || __put_user(0x44000002UL, &frame->tramp[1]))
			return 1;
		flush_icache_range((unsigned long) &frame->tramp[0],
				   (unsigned long) &frame->tramp[2]);
		get_user(regs->gpr[5], (unsigned long *)&rt_sf->puc);
		regs->gpr[6] = (unsigned long) rt_sf;

		regs->link = (unsigned long) &sr->tramp;
		regs->nip = sigctx.handler;
		if (get_user(prevsp, &sr->gp_regs[PT_R1])
		    || put_user(prevsp, (unsigned long *) regs->gpr[1]))
			goto badframe;
		current->thread.fpscr = 0;
	}
	return ret;

	return 0;
	do_exit(SIGSEGV);
}

/*
 * Restore the current user register values from the user stack,
 * (except for MSR).
 */
static int
restore_user_regs(struct pt_regs *regs, struct mcontext *sr, int mctxsize)
{
#ifdef CONFIG_ALTIVEC
	unsigned long msr;
#endif

	if (mctxsize && mctxsize < sizeof(struct mcontext))
		return 1;

	/* copy up to but not including MSR */
	if (__copy_from_user(regs, &sr->mc_gregs, PT_MSR * sizeof(elf_greg_t)))
		return 1;
	/* copy from orig_r3 (the word after the MSR) up to the end */
	if (__copy_from_user(&regs->orig_gpr3, &sr->mc_gregs[PT_ORIG_R3],
			     GP_REGS_SIZE - PT_ORIG_R3 * sizeof(elf_greg_t)))
		return 1;

	/* force the process to reload the FP registers from
	   current->thread when it next does FP instructions */
	regs->msr &= ~MSR_FP;
	if (__copy_from_user(current->thread.fpr, &sr->mc_fregs,
			     sizeof(sr->mc_fregs)))
		return 1;

#ifdef CONFIG_ALTIVEC
	/* force the process to reload the altivec registers from
	   current->thread when it next does altivec instructions */
	regs->msr &= ~MSR_VEC;
	if (!__get_user(msr, &sr->mc_gregs[PT_MSR]) && (msr & MSR_VEC) != 0) {
		/* restore altivec registers from the stack */
		if (__copy_from_user(current->thread.vr, &sr->mc_vregs,
				     sizeof(sr->mc_vregs)))
			return 1;
	} else if (current->thread.used_vr)
		memset(&current->thread.vr, 0, sizeof(current->thread.vr));

	/* Always get VRSAVE back */
	if (__get_user(current->thread.vrsave, (u32 *)&sr->mc_vregs[32]))
		return 1;
#endif /* CONFIG_ALTIVEC */

	return 0;
}

/*
 * Restore the user process's signal mask
 */
static void
restore_sigmask(sigset_t *set)
	       signed long newsp)
{
	sigdelsetmask(set, ~_BLOCKABLE);
	spin_lock_irq(&current->sigmask_lock);
	current->blocked = *set;
	recalc_sigpending(current);
	spin_unlock_irq(&current->sigmask_lock);
}

/*
 * Set up a signal frame for a "real-time" signal handler
 * (one which gets siginfo).
 */
static void
handle_rt_signal(unsigned long sig, struct k_sigaction *ka,
		 siginfo_t *info, sigset_t *oldset, struct pt_regs * regs,
		 unsigned long newsp)
{
	struct rt_sigframe *rt_sf;
	struct mcontext *frame;
	unsigned long origsp = newsp;

	/* Set up Signal Frame */
	/* Put a Real Time Context onto stack */
	newsp -= sizeof(*rt_sf);
	rt_sf = (struct rt_sigframe *) newsp;

	/* create a stack frame for the caller of the handler */
	newsp -= __SIGNAL_FRAMESIZE + 16;

	if (verify_area(VERIFY_WRITE, (void *) newsp, origsp - newsp))
		goto badframe;

	/* Put the siginfo & fill in most of the ucontext */
	if (__copy_to_user(&rt_sf->info, info, sizeof(*info))
	    || __put_user(0, &rt_sf->uc.uc_flags)
	    || __put_user(0, &rt_sf->uc.uc_link)
	    || __put_user(current->sas_ss_sp, &rt_sf->uc.uc_stack.ss_sp)
	    || __put_user(sas_ss_flags(regs->gpr[1]), 
			  &rt_sf->uc.uc_stack.ss_flags)
	    || __put_user(current->sas_ss_size, &rt_sf->uc.uc_stack.ss_size)
	    || __put_user(&rt_sf->uc.uc_mcontext, &rt_sf->uc.uc_regs)
	    || __copy_to_user(&rt_sf->uc.uc_oldsigmask, oldset, sizeof(*oldset))
	    || __copy_to_user(&rt_sf->uc.uc_sigmask, oldset, sizeof(*oldset)))
		goto badframe;
	flush_icache_range((unsigned long) &frame->tramp[0],
			   (unsigned long) &frame->tramp[2]);
	current->thread.fpscr = 0;	/* turn off all fp exceptions */

	/* Save user registers on the stack */
	frame = &rt_sf->uc.uc_mcontext;
	if (save_user_regs(regs, frame, 0x6666, 0))
	newsp -= __SIGNAL_FRAMESIZE;
	if (put_user(regs->gpr[1], (unsigned long *)newsp)
	    || get_user(regs->nip, &rt_sf->uc.uc_mcontext.handler)
	    || get_user(regs->gpr[3], &rt_sf->uc.uc_mcontext.signal)
	    || get_user(regs->gpr[4], (unsigned long *)&rt_sf->pinfo)
	    || get_user(regs->gpr[5], (unsigned long *)&rt_sf->puc))
		goto badframe;

	if (put_user(regs->gpr[1], (unsigned long *)newsp))
		goto badframe;
	regs->gpr[1] = newsp;
	regs->gpr[3] = sig;
	regs->gpr[4] = (unsigned long) &rt_sf->info;
	regs->gpr[5] = (unsigned long) &rt_sf->uc;
	regs->gpr[6] = (unsigned long) rt_sf;
	regs->nip = (unsigned long) ka->sa.sa_handler;
	regs->link = (unsigned long) frame->tramp;

	return;

badframe:
#if DEBUG_SIG
	printk("badframe in handle_rt_signal, regs=%p frame=%p newsp=%lx\n",
	       regs, frame, newsp);
#endif
	do_exit(SIGSEGV);
}

static int do_setcontext(struct ucontext *ucp, struct pt_regs *regs, int mctxsize)
 * Do a signal return; undo the signal stack.
 */
int sys_sigreturn(struct pt_regs *regs)
{
	struct sigcontext_struct *sc, sigctx;
	struct sigregs *sr;
	int ret;
	elf_gregset_t saved_regs;  /* an array of ELF_NGREG unsigned longs */
	sigset_t set;
	unsigned long prevsp;

	if (__copy_from_user(&set, &ucp->uc_sigmask, sizeof(set)))
		return -EFAULT;
	restore_sigmask(&set);

	if (restore_user_regs(regs, &ucp->uc_mcontext, mctxsize))
		return -EFAULT;
	set.sig[1] = sigctx._unused[3];
#endif
	sigdelsetmask(&set, ~_BLOCKABLE);
	spin_lock_irq(&current->sigmask_lock);
	current->blocked = set;
	recalc_sigpending(current);
	spin_unlock_irq(&current->sigmask_lock);
	if (regs->msr & MSR_FP )
		giveup_fpu(current);

	return 0;
}

int sys_swapcontext(struct ucontext *old_ctx, struct ucontext *new_ctx,
		    int mctxtsize, int r6, int r7, int r8, struct pt_regs *regs)
{
	unsigned char tmp;

	if (old_ctx != NULL) {
		if (verify_area(VERIFY_WRITE, old_ctx, sizeof(*old_ctx))
		    || save_user_regs(regs, &old_ctx->uc_mcontext, 0, mctxtsize)
		    || __copy_to_user(&old_ctx->uc_sigmask,
				      &current->blocked, sizeof(sigset_t))
		    /* the next 2 things aren't strictly necessary */
		    || __copy_to_user(&old_ctx->uc_oldsigmask,
				      &current->blocked, sizeof(sigset_t))
		    || __put_user(&old_ctx->uc_mcontext, &old_ctx->uc_regs))
			return -EFAULT;
		/* More signals to go */
		regs->gpr[1] = (unsigned long)sc - __SIGNAL_FRAMESIZE;
		if (copy_from_user(&sigctx, sc, sizeof(sigctx)))
			goto badframe;
		sr = (struct sigregs *) sigctx.regs;
		regs->gpr[3] = ret = sigctx.signal;
		regs->gpr[4] = (unsigned long) sc;
		regs->link = (unsigned long) &sr->tramp;
		regs->nip = sigctx.handler;

		if (get_user(prevsp, &sr->gp_regs[PT_R1])
		    || put_user(prevsp, (unsigned long *) regs->gpr[1]))
			goto badframe;
		current->thread.fpscr = 0;
	}
	if (new_ctx == NULL)
		return 0;
	if (verify_area(VERIFY_READ, new_ctx, sizeof(*new_ctx))
	    || __get_user(tmp, (u8 *) new_ctx)
	    || __get_user(tmp, (u8 *) (new_ctx + 1) - 1))
		return -EFAULT;

	/*
	 * If we get a fault copying the context into the kernel's
	 * image of the user's registers, we can't just return -EFAULT
	 * because the user's registers will be corrupted.  For instance
	 * the NIP value may have been updated but not some of the
	 * other registers.  Given that we have done the verify_area
	 * and successfully read the first and last bytes of the region
	 * above, this should only happen in an out-of-memory situation
	 * or if another thread unmaps the region containing the context.
	 * We kill the task with a SIGSEGV in this situation.
	 */
	if (do_setcontext(new_ctx, regs, mctxtsize))
		do_exit(SIGSEGV);
	syscall_direct_return(regs);
	/* doesn't actually return back to here */
	return 0;
}

int sys_rt_sigreturn(struct pt_regs *regs)
 * Set up a signal frame.
 */
static void
setup_frame(struct pt_regs *regs, struct sigregs *frame,
	    unsigned long newsp)
{
	struct rt_sigframe *rt_sf;
	stack_t st;

	rt_sf = (struct rt_sigframe *)(regs->gpr[1] + __SIGNAL_FRAMESIZE + 16);
	if (verify_area(VERIFY_READ, rt_sf, sizeof(struct rt_sigframe)))
		goto bad;
	if (do_setcontext(&rt_sf->uc, regs, 0))
		goto bad;

	/*
	 * It's not clear whether or why it is desirable to save the
	 * sigaltstack setting on signal delivery and restore it on
	 * signal return.  But other architectures do this and we have
	 * always done it up until now so it is probably better not to
	 * change it.  -- paulus
	 */
	if (__copy_from_user(&st, &rt_sf->uc.uc_stack, sizeof(st)))
		goto bad;
	do_sigaltstack(&st, NULL, regs->gpr[1]);

	return regs->result;
	if (put_user(regs->gpr[1], (unsigned long *)newsp)
	    || get_user(regs->nip, &sc->handler)
	    || get_user(regs->gpr[3], &sc->signal))
		goto badframe;
	regs->gpr[1] = newsp;
	regs->gpr[4] = (unsigned long) sc;
	regs->link = (unsigned long) frame->tramp;

 bad:

badframe:
#if DEBUG_SIG
	printk("badframe in setup_frame, regs=%p frame=%p newsp=%lx\n",
	       regs, frame, newsp);
#endif
	do_exit(SIGSEGV);
}


static void
handle_signal(unsigned long sig, struct k_sigaction *ka,
	      siginfo_t *info, sigset_t *oldset, struct pt_regs * regs,
	      unsigned long newsp)
{
	struct sigcontext *sc;
	struct sigregs *frame;
	unsigned long origsp = newsp;
	if (regs->trap == 0x0C00 /* System Call! */
	    && ((int)regs->result == -ERESTARTNOHAND ||
		((int)regs->result == -ERESTARTSYS &&
		 !(ka->sa.sa_flags & SA_RESTART))))
		regs->result = -EINTR;

	/* Set up Signal Frame */
	newsp -= sizeof(struct sigregs);
	frame = (struct sigregs *) newsp;

	/* Put a sigcontext on the stack */
	newsp -= sizeof(*sc);
	sc = (struct sigcontext *) newsp;

	/* create a stack frame for the caller of the handler */
	newsp -= __SIGNAL_FRAMESIZE;

	if (verify_area(VERIFY_WRITE, (void *) newsp, origsp - newsp))
		goto badframe;

#if _NSIG != 64
#error "Please adjust handle_signal()"
		    || __put_user(current->sas_ss_sp, &rt_sf->uc.uc_stack.ss_sp)
		    || __put_user(sas_ss_flags(regs->gpr[1]),
				  &rt_sf->uc.uc_stack.ss_flags)
		    || __put_user(current->sas_ss_size, &rt_sf->uc.uc_stack.ss_size)
		    || __copy_to_user(&rt_sf->uc.uc_sigmask, oldset, sizeof(*oldset))
		    /* mcontext.regs points to preamble register frame */
		    || __put_user((struct pt_regs *)frame, &rt_sf->uc.uc_mcontext.regs)
		    || __put_user(sig, &rt_sf->uc.uc_mcontext.signal))
			goto badframe;
	} else {
		/* Put another sigcontext on the stack */
		*newspp -= sizeof(*sc);
		sc = (struct sigcontext_struct *) *newspp;
		if (verify_area(VERIFY_WRITE, sc, sizeof(*sc)))
			goto badframe;

		if (__put_user((unsigned long) ka->sa.sa_handler, &sc->handler)
		    || __put_user(oldset->sig[0], &sc->oldmask)
#if _NSIG_WORDS > 1
		    || __put_user(oldset->sig[1], &sc->_unused[3])
#endif
	if (__put_user((unsigned long) ka->sa.sa_handler, &sc->handler)
	    || __put_user(oldset->sig[0], &sc->oldmask)
	    || __put_user(oldset->sig[1], &sc->_unused[3])
	    || __put_user((struct pt_regs *)frame, &sc->regs)
	    || __put_user(sig, &sc->signal))
		goto badframe;

	if (save_user_regs(regs, &frame->mctx, 0x7777, 0))
		goto badframe;

	if (put_user(regs->gpr[1], (unsigned long *)newsp))
		goto badframe;
	regs->gpr[1] = newsp;
	regs->gpr[3] = sig;
	regs->gpr[4] = (unsigned long) sc;
	regs->nip = (unsigned long) ka->sa.sa_handler;
	regs->link = (unsigned long) frame->mctx.tramp;

	if (!(ka->sa.sa_flags & SA_NODEFER)) {
		spin_lock_irq(&current->sigmask_lock);
		sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
		sigaddset(&current->blocked,sig);
		recalc_sigpending(current);
		spin_unlock_irq(&current->sigmask_lock);
	}
	return;

badframe:

}

/*
 * Do a signal return; undo the signal stack.
 * want to handle. Thus you cannot kill init even with a SIGKILL even by
 * mistake.
 */
int sys_sigreturn(struct pt_regs *regs)
{
	struct sigcontext *sc, sigctx;
	struct mcontext *sr;
	int ret;
	sigset_t set;

	sc = (struct sigcontext *)(regs->gpr[1] + __SIGNAL_FRAMESIZE);
	if (copy_from_user(&sigctx, sc, sizeof(sigctx)))
		goto badframe;

	set.sig[0] = sigctx.oldmask;
	set.sig[1] = sigctx._unused[3];
	restore_sigmask(&set);

	sr = (struct mcontext *) sigctx.regs;
	if (verify_area(VERIFY_READ, sr, sizeof(*sr))
	    || restore_user_regs(regs, sr, 0))
		goto badframe;

	ret = regs->result;

	return ret;

badframe:
	do_exit(SIGSEGV);
}	

static int get_signal_to_deliver(struct siginfo *infop, struct pt_regs *regs)
{
	struct k_sigaction *ka;
	int signr;

	for (;;) {
		spin_lock_irq(&current->sigmask_lock);
		signr = dequeue_signal(&current->blocked, infop);
		spin_unlock_irq(&current->sigmask_lock);

		if (!signr)
			return 0;

		if ((current->ptrace & PT_PTRACED) && signr != SIGKILL) {
			/* Let the debugger run.  */

				continue;

			/* Update the siginfo structure.  Is this good?  */
			if (signr != infop->si_signo) {
				infop->si_signo = signr;
				infop->si_errno = 0;
				infop->si_code = SI_USER;
				infop->si_pid = current->p_pptr->pid;
				infop->si_uid = current->p_pptr->uid;
			}

			/* If the (new) signal is now blocked, requeue it.  */
			if (sigismember(&current->blocked, signr)) {
				send_sig_info(signr, infop, current);
				continue;
			}
		}

				/* FALLTHRU */

			default:
				sig_exit(signr, exit_code, infop);
				/* NOTREACHED */
			}
		}
		return signr;
	}
}

/*
 * Note that 'init' is a special process: it doesn't get signals it doesn't
 * want to handle. Thus you cannot kill init even with a SIGKILL even by
 * mistake.
 */
int do_signal(sigset_t *oldset, struct pt_regs *regs)
{
	siginfo_t info;
	struct k_sigaction *ka;
	unsigned long frame, newsp;
	int signr;

	if (!oldset)
		oldset = &current->blocked;

	newsp = frame = 0;

	signr = get_signal_to_deliver(&info, regs);

	ka = (signr == 0)? NULL: &current->sig->action[signr-1];

	if (regs->trap == 0xc00) {		/* system call */
		switch ((int) regs->result) {
		case -ERESTARTSYS:
			if (signr == 0 || (ka->sa.sa_flags & SA_RESTART))
				goto retry;
			/* fall through */
		case -ERESTARTNOHAND:
			if (signr > 0) {
				/* make the system call return an EINTR */
				regs->result = -EINTR;
				break;
			}
			/* fall through */
		case -ERESTARTNOINTR:
		retry:
			/* Back up & retry system call */
			regs->gpr[3] = regs->orig_gpr3;
			regs->nip -= 4;
			regs->result = 0;
			break;
		}
	}

	if (signr == 0)
		return 0;		/* no signals delivered */

	if ((ka->sa.sa_flags & SA_ONSTACK) && current->sas_ss_size
	    && !on_sig_stack(regs->gpr[1]))
		newsp = current->sas_ss_sp + current->sas_ss_size;
	else
		newsp = regs->gpr[1];
	newsp &= ~0xfUL;

	/* Whee!  Actually deliver the signal.  */
	if (ka->sa.sa_flags & SA_SIGINFO)
		handle_rt_signal(signr, ka, &info, oldset, regs, newsp);
	else
		handle_signal(signr, ka, &info, oldset, regs, newsp);

	if (ka->sa.sa_flags & SA_ONESHOT)
		ka->sa.sa_handler = SIG_DFL;

	if (!(ka->sa.sa_flags & SA_NODEFER)) {
		spin_lock_irq(&current->sigmask_lock);
		sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
		sigaddset(&current->blocked, signr);
		recalc_sigpending(current);
		spin_unlock_irq(&current->sigmask_lock);
	}

	return 1;
}





/*
 * Smp timebase synchronization for ppc.
 *
 * Copyright (C) 2003 Samuel Rydh (samuel@ibrium.se)
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/unistd.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/time.h>

#define NUM_ITER		300

enum {
	kExit=0, kSetAndTest, kTest
};

static struct {
	volatile int		tbu;
	volatile int		tbl;
	volatile int		mark;
	volatile int		cmd;
	volatile int		handshake;
	int			filler[3];

	volatile int		ack;
	int			filler2[7];

	volatile int		race_result;
} *tbsync;

static volatile int		running;

static void __devinit
enter_contest( int mark, int add )
{
	while( (int)(get_tbl() - mark) < 0 )
		tbsync->race_result = add;
}

void __devinit
smp_generic_take_timebase( void )
{
	int cmd, tbl, tbu;

	local_irq_disable();
	while( !running )
		;
	rmb();

	for( ;; ) {
		tbsync->ack = 1;
		while( !tbsync->handshake )
			;
		rmb();

		cmd = tbsync->cmd;
		tbl = tbsync->tbl;
		tbu = tbsync->tbu;
		tbsync->ack = 0;
		if( cmd == kExit )
			return;

		if( cmd == kSetAndTest ) {
			while( tbsync->handshake )
				;
			asm volatile ("mttbl %0" :: "r" (tbl) );
			asm volatile ("mttbu %0" :: "r" (tbu) );
		} else {
			while( tbsync->handshake )
				;
		}
		enter_contest( tbsync->mark, -1 );
	}
	local_irq_enable();
}

static int __devinit
start_contest( int cmd, int offset, int num )
{
	int i, tbu, tbl, mark, score=0;

	tbsync->cmd = cmd;

	local_irq_disable();
	for( i=-3; i<num; ) {
		tbl = get_tbl() + 400;
		tbsync->tbu = tbu = get_tbu();
		tbsync->tbl = tbl + offset;
		tbsync->mark = mark = tbl + 400;

		wmb();

		tbsync->handshake = 1;
		while( tbsync->ack )
			;

		while( (int)(get_tbl() - tbl) <= 0 )
			;
		tbsync->handshake = 0;
		enter_contest( mark, 1 );

		while( !tbsync->ack )
			;

		if( tbsync->tbu != get_tbu() || ((tbsync->tbl ^ get_tbl()) & 0x80000000) )
			continue;
		if( i++ > 0 )
			score += tbsync->race_result;
	}
	local_irq_enable();
	return score;
}

void __devinit
smp_generic_give_timebase( void )
{
	int i, score, score2, old, min=0, max=5000, offset=1000;

	printk("Synchronizing timebase\n");

	/* if this fails then this kernel won't work anyway... */
	tbsync = kmalloc( sizeof(*tbsync), GFP_KERNEL );
	memset( tbsync, 0, sizeof(*tbsync) );
	mb();
	running = 1;

	while( !tbsync->ack )
		;

	/* binary search */
	for( old=-1 ; old != offset ; offset=(min+max)/2 ) {
		score = start_contest( kSetAndTest, offset, NUM_ITER );

		printk("score %d, offset %d\n", score, offset );

		if( score > 0 )
			max = offset;
		else
			min = offset;
		old = offset;
	}
	score = start_contest( kSetAndTest, min, NUM_ITER );
	score2 = start_contest( kSetAndTest, max, NUM_ITER );

	printk( "Min %d (score %d), Max %d (score %d)\n", min, score, max, score2 );
	score = abs( score );
	score2 = abs( score2 );
	offset = (score < score2) ? min : max;

	/* guard against inaccurate mttb */
	for( i=0; i<10; i++ ) {
		start_contest( kSetAndTest, offset, NUM_ITER/10 );

		if( (score2=start_contest(kTest, offset, NUM_ITER)) < 0 )
			score2 = -score2;
		if( score2 <= score || score2 < 20 )
			break;
	}
	printk("Final offset: %d (%d/%d)\n", offset, score2, NUM_ITER );

	/* exiting */
	tbsync->cmd = kExit;
	wmb();
	tbsync->handshake = 1;
	while( tbsync->ack )
		;
	tbsync->handshake = 0;
	kfree( tbsync );
	tbsync = NULL;
	running = 0;

	/* all done */
	smp_tb_synchronized = 1;
}

Lines 55-68 Link Here

(-)linux-2.4.22/arch/ppc/kernel/smp.c (-91 / +16 lines)
55	/* all cpu mappings are 1-1 -- Cort */	55	/* all cpu mappings are 1-1 -- Cort */
56	volatile unsigned long cpu_callin_map[NR_CPUS];	56	volatile unsigned long cpu_callin_map[NR_CPUS];
57		57
58	#define TB_SYNC_PASSES 4
59	volatile unsigned long __initdata tb_sync_flag = 0;
60	volatile unsigned long __initdata tb_offset = 0;
61
62	int start_secondary(void *);	58	int start_secondary(void *);
63	extern int cpu_idle(void *unused);	59	extern int cpu_idle(void *unused);
64	void smp_call_function_interrupt(void);	60	void smp_call_function_interrupt(void);
65		61
		62	extern void smp_generic_take_timebase(void);
		63	extern void smp_generic_give_timebase(void);
		64
66	/* Low level assembly function used to backup CPU 0 state */	65	/* Low level assembly function used to backup CPU 0 state */
67	extern void __save_cpu_setup(void);	66	extern void __save_cpu_setup(void);
68		67
Lines 230-235 Link Here
230	timeout = 1000000;	229	timeout = 1000000;
231	while (atomic_read(&data.started) != cpus) {	230	while (atomic_read(&data.started) != cpus) {
232	if (--timeout == 0) {	231	if (--timeout == 0) {
		232	#ifdef CONFIG_XMON
		233	xmon_printf("smp_call_function on cpu %d: other cpus not responding (%d)\n",
		234	smp_processor_id(), atomic_read(&data.started));
		235	#endif
233	printk("smp_call_function on cpu %d: other cpus not responding (%d)\n",	236	printk("smp_call_function on cpu %d: other cpus not responding (%d)\n",
234	smp_processor_id(), atomic_read(&data.started));	237	smp_processor_id(), atomic_read(&data.started));
235	goto out;	238	goto out;
Lines 242-247 Link Here
242	timeout = 1000000;	245	timeout = 1000000;
243	while (atomic_read(&data.finished) != cpus) {	246	while (atomic_read(&data.finished) != cpus) {
244	if (--timeout == 0) {	247	if (--timeout == 0) {
		248	#ifdef CONFIG_XMON
		249	xmon_printf("smp_call_function on cpu %d: other cpus not finishing (%d/%d)\n",
		250	smp_processor_id(), atomic_read(&data.finished), atomic_read(&data.started));
		251	#endif
245	printk("smp_call_function on cpu %d: other cpus not finishing (%d/%d)\n",	252	printk("smp_call_function on cpu %d: other cpus not finishing (%d/%d)\n",
246	smp_processor_id(), atomic_read(&data.finished), atomic_read(&data.started));	253	smp_processor_id(), atomic_read(&data.finished), atomic_read(&data.started));
247	goto out;	254	goto out;
Lines 399-479 Link Here
399	smp_tb_synchronized = 1;	406	smp_tb_synchronized = 1;
400	}	407	}
401		408
402	void __init smp_software_tb_sync(int cpu)
403	{
404	#define PASSES 4 /* 4 passes.. */
405	int pass;
406	int i, j;
407
408	/* stop - start will be the number of timebase ticks it takes for cpu0
409	* to send a message to all others and the first reponse to show up.
410	*
411	* ASSUMPTION: this time is similiar for all cpus
412	* ASSUMPTION: the time to send a one-way message is ping/2
413	*/
414	register unsigned long start = 0;
415	register unsigned long stop = 0;
416	register unsigned long temp = 0;
417
418	set_tb(0, 0);
419
420	/* multiple passes to get in l1 cache.. */
421	for (pass = 2; pass < 2+PASSES; pass++){
422	if (cpu == 0){
423	mb();
424	for (i = j = 1; i < smp_num_cpus; i++, j++){
425	/* skip stuck cpus */
426	while (!cpu_callin_map[j])
427	++j;
428	while (cpu_callin_map[j] != pass)
429	barrier();
430	}
431	mb();
432	tb_sync_flag = pass;
433	start = get_tbl(); /* start timing */
434	while (tb_sync_flag)
435	mb();
436	stop = get_tbl(); /* end timing */
437	/* theoretically, the divisor should be 2, but
438	* I get better results on my dual mtx. someone
439	* please report results on other smp machines..
440	*/
441	tb_offset = (stop-start)/4;
442	mb();
443	tb_sync_flag = pass;
444	udelay(10);
445	mb();
446	tb_sync_flag = 0;
447	mb();
448	set_tb(0,0);
449	mb();
450	} else {
451	cpu_callin_map[cpu] = pass;
452	mb();
453	while (!tb_sync_flag)
454	mb(); /* wait for cpu0 */
455	mb();
456	tb_sync_flag = 0; /* send response for timing */
457	mb();
458	while (!tb_sync_flag)
459	mb();
460	temp = tb_offset; /* make sure offset is loaded */
461	while (tb_sync_flag)
462	mb();
463	set_tb(0,temp); /* now, set the timebase */
464	mb();
465	}
466	}
467	if (cpu == 0) {
468	smp_tb_synchronized = 1;
469	printk("smp_software_tb_sync: %d passes, final offset: %ld\n",
470	PASSES, tb_offset);
471	}
472	/* so time.c doesn't get confused */
473	set_dec(tb_ticks_per_jiffy);
474	last_jiffy_stamp(cpu) = 0;
475	}
476
477	void __init smp_commence(void)	409	void __init smp_commence(void)
478	{	410	{
479	/*	411	/*
Lines 486-504 Link Here
486	/* if the smp_ops->setup_cpu function has not already synched the	418	/* if the smp_ops->setup_cpu function has not already synched the
487	* timebases with a nicer hardware-based method, do so now	419	* timebases with a nicer hardware-based method, do so now
488	*	420	*
489	* I am open to suggestions for improvements to this method	421	* New version backported from Samuel Rydth 2.6 version, unlike 2.6
490	* -- Troy <hozer@drgw.net>	422	* version works only for 2 CPUs (easy hack)
491	*
492	* NOTE: if you are debugging, set smp_tb_synchronized for now
493	* since if this code runs pretty early and needs all cpus that
494	* reported in in smp_callin_map to be working
495	*
496	* NOTE2: this code doesn't seem to work on > 2 cpus. -- paulus/BenH
497	*/	423	*/
498	if (!smp_tb_synchronized && smp_num_cpus == 2) {	424	if (!smp_tb_synchronized && smp_num_cpus == 2) {
499	unsigned long flags;	425	unsigned long flags;
500	__save_and_cli(flags);	426	__save_and_cli(flags);
501	smp_software_tb_sync(0);	427	smp_generic_give_timebase();
502	__restore_flags(flags);	428	__restore_flags(flags);
503	}	429	}
504	}	430	}
Lines 518-526 Link Here
518	barrier();	444	barrier();
519		445
520	/* see smp_commence for more info */	446	/* see smp_commence for more info */
521	if (!smp_tb_synchronized && smp_num_cpus == 2) {	447	if (!smp_tb_synchronized && smp_num_cpus == 2)
522	smp_software_tb_sync(cpu);	448	smp_generic_take_timebase();
523	}
524	__sti();	449	__sti();
525	}	450	}
526		451

Lines 85-98 Link Here

(-)linux-2.4.22/arch/ppc/kernel/traps.c (-3 / +16 lines)
85		85
86	void die(const char * str, struct pt_regs * fp, long err)	86	void die(const char * str, struct pt_regs * fp, long err)
87	{	87	{
		88	#ifdef CONFIG_BOOTX_TEXT
		89	extern int force_printk_to_btext;
		90	#endif
88	console_verbose();	91	console_verbose();
89	spin_lock_irq(&die_lock);	92	spin_lock_irq(&die_lock);
		93	#ifdef CONFIG_BOOTX_TEXT
		94	force_printk_to_btext = 1;
		95	#endif
90	#ifdef CONFIG_PMAC_BACKLIGHT	96	#ifdef CONFIG_PMAC_BACKLIGHT
91	set_backlight_enable(1);	97	if (_machine == _MACH_Pmac) {
92	set_backlight_level(BACKLIGHT_MAX);	98	set_backlight_enable(1);
93	#endif	99	set_backlight_level(BACKLIGHT_MAX);
		100	}
		101	#endif
94	printk("Oops: %s, sig: %ld\n", str, err);	102	printk("Oops: %s, sig: %ld\n", str, err);
95	show_regs(fp);	103	show_regs(fp);
		104	#ifdef CONFIG_BOOTX_TEXT
		105	force_printk_to_btext = 0;
		106	#endif
96	spin_unlock_irq(&die_lock);	107	spin_unlock_irq(&die_lock);
97	/* do_exit() should take care of panic'ing from an interrupt	108	/* do_exit() should take care of panic'ing from an interrupt
98	* context so we don't handle it here	109	* context so we don't handle it here
Lines 153-161 Link Here
153		164
154	--nip;	165	--nip;
155	rb = (*nip >> 11) & 0x1f;	166	rb = (*nip >> 11) & 0x1f;
		167	#if 0
156	printk(KERN_DEBUG "%s bad port %lx at %p\n",	168	printk(KERN_DEBUG "%s bad port %lx at %p\n",
157	(*nip & 0x100)? "OUT to": "IN from",	169	(*nip & 0x100)? "OUT to": "IN from",
158	regs->gpr[rb] - _IO_BASE, nip);	170	regs->gpr[rb] - _IO_BASE, nip);
		171	#endif
159	regs->nip = fixup;	172	regs->nip = fixup;
160	return 1;	173	return 1;
161	}	174	}

Lines 15-20 Link Here

(-)linux-2.4.22/arch/ppc/lib/locks.c (+8 lines)
15		15
16	#if SPINLOCK_DEBUG	16	#if SPINLOCK_DEBUG
17		17
		18	/* Route debug output to xmon when possible, there are more chances
		19	* for it to work than the console
		20	*/
		21	#ifdef CONFIG_XMON
		22	extern void xmon_printf(const char* fmt,...);
		23	#define printk xmon_printf
		24	#endif
		25
18	#undef INIT_STUCK	26	#undef INIT_STUCK
19	#define INIT_STUCK 200000000 /0xffffffff/	27	#define INIT_STUCK 200000000 /0xffffffff/
20		28

Lines 96-102 Link Here

(-)linux-2.4.22/arch/ppc/mm/fault.c (-2 / +3 lines)
96	void do_page_fault(struct pt_regs *regs, unsigned long address,	96	void do_page_fault(struct pt_regs *regs, unsigned long address,
97	unsigned long error_code)	97	unsigned long error_code)
98	{	98	{
99	struct vm_area_struct * vma;	99	struct vm_area_struct * vma, * prev_vma;
100	struct mm_struct *mm = current->mm;	100	struct mm_struct *mm = current->mm;
101	siginfo_t info;	101	siginfo_t info;
102	int code = SEGV_MAPERR;	102	int code = SEGV_MAPERR;
Lines 177-183 Link Here
177	&& (!user_mode(regs) \|\| !store_updates_sp(regs)))	177	&& (!user_mode(regs) \|\| !store_updates_sp(regs)))
178	goto bad_area;	178	goto bad_area;
179	}	179	}
180	if (expand_stack(vma, address))	180	vma = find_vma_prev(mm, address, &prev_vma);
		181	if (expand_stack(vma, address, prev_vma))
181	goto bad_area;	182	goto bad_area;
182		183
183	good_area:	184	good_area:




	high_memory = (void *) __va(PPC_MEMSTART + total_lowmem);
	num_physpages = max_mapnr;	/* RAM is assumed contiguous */

	/* Sanity check: did ioremap_bot stomp over vmalloc space ? We keep
	 * a minimal 16Mb guard though if you only have 16Mb left, you'll
	 * probably run into trouble, so we also printk something if you
	 * have less than 64Mb. This is meant to help diagnosing such problems
	 * as debugging it can be really painful. --BenH.
	 */
	if (VMALLOC_END < (VMALLOC_START + 0x01000000UL))
		panic("Argh ! Virtual space exhausted !");
	if (VMALLOC_END < (VMALLOC_START + 0x04000000UL))
		printk(KERN_WARNING "Warning ! Virtual space small !");

	totalram_pages += free_all_bootmem();

#ifdef CONFIG_BLK_DEV_INITRD

Lines 238-244 Link Here

(-)linux-2.4.22/arch/ppc/mm/pgtable.c (-1 / +1 lines)
238		238
239	printk(KERN_INFO "Memory BAT mapping: BAT2=%ldMb, BAT3=%ldMb,"	239	printk(KERN_INFO "Memory BAT mapping: BAT2=%ldMb, BAT3=%ldMb,"
240	" residual: %ldMb\n", __bat2 >> 20, __bat3 >> 20,	240	" residual: %ldMb\n", __bat2 >> 20, __bat3 >> 20,
241	(total_lowmem - (__bat2 - __bat3)) >> 20);	241	(total_memory - (__bat2 - __bat3)) >> 20);
242		242
243	/* On SMP, we limit the lowmem to the area mapped with BATs.	243	/* On SMP, we limit the lowmem to the area mapped with BATs.
244	* We also assume nobody will do SMP with 601s	244	* We also assume nobody will do SMP with 601s

Lines 41-46 Link Here

(-)linux-2.4.22/arch/ppc/platforms/Makefile (+3 lines)
41	prep_time.o prep_setup.o pmac_sleep.o \	41	prep_time.o prep_setup.o pmac_sleep.o \
42	pmac_nvram.o	42	pmac_nvram.o
43	obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o	43	obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
		44	ifeq ($(CONFIG_ALL_PPC),y)
		45	obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
		46	endif
44	obj-$(CONFIG_PPC_RTAS) += error_log.o proc_rtas.o	47	obj-$(CONFIG_PPC_RTAS) += error_log.o proc_rtas.o
45	obj-$(CONFIG_PREP_RESIDUAL) += residual.o	48	obj-$(CONFIG_PREP_RESIDUAL) += residual.o
46	obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o	49	obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o




#include <linux/config.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>
#include <linux/init.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/hardirq.h>
#include <asm/pmac_feature.h>
#include <asm/mmu_context.h>
#include <asm/sections.h>
#include <asm/cputable.h>
#include <asm/time.h>

#undef DEBUG_FREQ

extern void low_choose_750fx_pll(int pll);
extern void low_sleep_handler(void);
extern void openpic_sleep_save_intrs(void);
extern void openpic_sleep_restore_intrs(void);
extern void enable_kernel_altivec(void);
extern void enable_kernel_fp(void);

static unsigned int low_freq;
static unsigned int hi_freq;
static unsigned int cur_freq;
static int cpufreq_uses_pmu;

#define PMAC_CPU_LOW_SPEED	1
#define PMAC_CPU_HIGH_SPEED	0

static inline void
wakeup_decrementer(void)
{
	set_dec(tb_ticks_per_jiffy);
	/* No currently-supported powerbook has a 601,
	 * so use get_tbl, not native
	 */
	last_jiffy_stamp(0) = tb_last_stamp = get_tbl();
}

#ifdef DEBUG_FREQ
static inline void
debug_calc_bogomips(void)
{
	/* This will cause a recalc of bogomips and display the
	 * result. We backup/restore the value to avoid affecting the
	 * core cpufreq framework's own calculation.
	 */
	extern void calibrate_delay(void);

	unsigned long save_lpj = loops_per_jiffy;
	calibrate_delay();
	loops_per_jiffy = save_lpj;
}
#endif

/* Switch CPU speed under 750FX CPU control
 */
static int __pmac
cpu_750fx_cpu_speed(int low_speed)
{
#ifdef DEBUG_FREQ
	printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));	
#endif
	low_choose_750fx_pll(low_speed);
#ifdef DEBUG_FREQ
	printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));	
	debug_calc_bogomips();
#endif

	return 0;
}

/* Switch CPU speed under PMU control
 */
static int __pmac
pmu_set_cpu_speed(unsigned int low_speed)
{
	struct adb_request req;
	unsigned long save_l2cr;
	unsigned long save_l3cr;
	
#ifdef DEBUG_FREQ
	printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));	
#endif
	/* Disable all interrupt sources on openpic */
	openpic_sleep_save_intrs();

	/* Make sure the PMU is idle */
	pmu_suspend();

	/* Make sure the decrementer won't interrupt us */
	asm volatile("mtdec %0" : : "r" (0x7fffffff));
	/* Make sure any pending DEC interrupt occuring while we did
	 * the above didn't re-enable the DEC */
	mb();
	asm volatile("mtdec %0" : : "r" (0x7fffffff));

	/* We can now disable MSR_EE */
	local_irq_disable();

	/* Giveup the FPU & vec */
	enable_kernel_fp();

#ifdef CONFIG_ALTIVEC
	if (cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC)
		enable_kernel_altivec();
#endif /* CONFIG_ALTIVEC */

	/* Save & disable L2 and L3 caches */
	save_l3cr = _get_L3CR();	/* (returns -1 if not available) */
	save_l2cr = _get_L2CR();	/* (returns -1 if not available) */
	if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
		_set_L3CR(save_l3cr & 0x7fffffff);
	if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
		_set_L2CR(save_l2cr & 0x7fffffff);

	/* Send the new speed command. My assumption is that this command
	 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
	 */
	pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
	while (!req.complete)
		pmu_poll();
	
	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);

	low_sleep_handler();
	
	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);

	/* Restore L2 cache */
	if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
 		_set_L2CR(save_l2cr);
	/* Restore L3 cache */
	if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
 		_set_L3CR(save_l3cr);

	/* Restore userland MMU context */
	set_context(current->active_mm->context, current->active_mm->pgd);

	pmu_unlock();
	
#ifdef DEBUG_FREQ
	printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));	
#endif

	/* Restore decrementer */
	wakeup_decrementer();

	/* Restore interrupts */
	openpic_sleep_restore_intrs();

	pmu_resume();

	/* Let interrupts flow again ... */
	local_irq_enable();

#ifdef DEBUG_FREQ
	debug_calc_bogomips();
#endif

	return 0;
}

static int __pmac
do_set_cpu_speed(int speed_mode)
{
	struct cpufreq_freqs    freqs;
	int rc;
	
	freqs.old = cur_freq;
	freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
	freqs.cpu = CPUFREQ_ALL_CPUS;

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	if (cpufreq_uses_pmu)
		rc = pmu_set_cpu_speed(speed_mode);
	else
		rc = cpu_750fx_cpu_speed(speed_mode);
	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	cur_freq = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;

	return rc;
}

static int __pmac
pmac_cpufreq_verify(struct cpufreq_policy *policy)
{
	if (!policy)
		return -EINVAL;
		
	policy->cpu = 0; /* UP only */

	cpufreq_verify_within_limits(policy, low_freq, hi_freq);

	if ((policy->min > low_freq) && 
	    (policy->max < hi_freq))
		policy->max = hi_freq;

	return 0;
}

static int __pmac
pmac_cpufreq_setpolicy(struct cpufreq_policy *policy)
{
	int rc;
	
	if (!policy)
		return -EINVAL;
	if (policy->min > low_freq)
		rc = do_set_cpu_speed(PMAC_CPU_HIGH_SPEED);
	else if (policy->max < hi_freq)
		rc = do_set_cpu_speed(PMAC_CPU_LOW_SPEED);
	else if (policy->policy == CPUFREQ_POLICY_POWERSAVE)
		rc = do_set_cpu_speed(PMAC_CPU_LOW_SPEED);
	else
		rc = do_set_cpu_speed(PMAC_CPU_HIGH_SPEED);

	return rc;
}

unsigned int __pmac
pmac_get_cur_cpufreq(void)
{
	return cur_freq;
}


/* Currently, we support the following machines:
 * 
 *  - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
 *  - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
 *  - iBook2 500 (PMU based, 400Mhz & 500Mhz)
 *  - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
 */
static int __init
pmac_cpufreq_setup(void)
{	
	struct device_node	*cpunode;
	struct cpufreq_driver   *driver;
	u32			*value;
	int			has_freq_ctl = 0;
	int			rc;
	
	memset(&driver, 0, sizeof(driver));

	/* Assume only one CPU */
	cpunode = find_type_devices("cpu");
	if (!cpunode)
		goto out;

	/* Get current cpu clock freq */
	value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
	if (!value)
		goto out;
	cur_freq = (*value) / 1000;

	/* Check for newer machines */
	if (machine_is_compatible("PowerBook3,4") ||
	    machine_is_compatible("PowerBook3,5") ||
	    machine_is_compatible("MacRISC3")) {
		value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
		if (!value)
			goto out;
		low_freq = (*value) / 1000;
		/* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
		 * here */
		if (low_freq < 100000)
			low_freq *= 10;
		
		value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
		if (!value)
			goto out;
		hi_freq = (*value) / 1000;			
		has_freq_ctl = 1;
		cpufreq_uses_pmu = 1;
	}
	/* Else check for iBook2 500 */
	else if (machine_is_compatible("PowerBook4,1")) {
		/* We only know about 500Mhz model */
		if (cur_freq < 450000 || cur_freq > 550000)
			goto out;
		hi_freq = cur_freq;
		low_freq = 400000;
		has_freq_ctl = 1;
		cpufreq_uses_pmu = 1;
	}
	/* Else check for TiPb 500 */
	else if (machine_is_compatible("PowerBook3,2")) {
		/* We only know about 500Mhz model */
		if (cur_freq < 450000 || cur_freq > 550000)
			goto out;
		hi_freq = cur_freq;
		low_freq = 300000;
		has_freq_ctl = 1;
		cpufreq_uses_pmu = 1;
	}
	/* Else check for 750FX */
	else if (PVR_VER(mfspr(PVR)) == 0x7000) {
		if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
			goto out;	
		hi_freq = cur_freq;
		value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
		if (!value)
			goto out;
		low_freq = (*value) / 1000;
		cpufreq_uses_pmu = 0;
		has_freq_ctl = 1;
	}
out:
	if (!has_freq_ctl)
		return -ENODEV;
	
	/* initialization of main "cpufreq" code*/
	driver = kmalloc(sizeof(struct cpufreq_driver) + 
			 NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
	if (!driver)
		return -ENOMEM;

	driver->policy = (struct cpufreq_policy *) (driver + 1);

#ifdef CONFIG_CPU_FREQ_24_API
	driver->cpu_min_freq[0] = low_freq;
	driver->cpu_cur_freq[0] = cur_freq;
#endif

	driver->verify      = &pmac_cpufreq_verify;
	driver->setpolicy   = &pmac_cpufreq_setpolicy;

	driver->policy[0].cpu    = 0;
	driver->policy[0].min    = low_freq;
	driver->policy[0].max    = cur_freq;
	driver->policy[0].max_cpu_freq = hi_freq;
	driver->policy[0].policy = (cur_freq == low_freq) ? 
	    CPUFREQ_POLICY_POWERSAVE : CPUFREQ_POLICY_PERFORMANCE;

	rc = cpufreq_register(driver);
	if (rc)
		kfree(driver);
	return rc;
}

__initcall(pmac_cpufreq_setup);


Lines 50-55 Link Here

(-)linux-2.4.22/arch/ppc/platforms/pmac_setup.c (-1 / +43 lines)
50	#include <linux/seq_file.h>	50	#include <linux/seq_file.h>
51	#include <linux/blkdev.h>	51	#include <linux/blkdev.h>
52	#include <linux/genhd.h>	52	#include <linux/genhd.h>
		53	#include <linux/cpufreq.h>
53		54
54	#include <asm/processor.h>	55	#include <asm/processor.h>
55	#include <asm/sections.h>	56	#include <asm/sections.h>
Lines 150-156 Link Here
150	{	151	{
151	struct device_node *cpu_node;	152	struct device_node *cpu_node;
152	int *fp, s;	153	int *fp, s;
153		154
		155	#ifdef CONFIG_CPU_FREQ_PMAC
		156	extern unsigned int pmac_get_cur_cpufreq(void);
		157	unsigned int freq = pmac_get_cur_cpufreq();
		158	if (freq != 0) {
		159	seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
		160	return 0;
		161	}
		162	#endif /* CONFIG_CPU_FREQ_PMAC */
154	cpu_node = find_type_devices("cpu");	163	cpu_node = find_type_devices("cpu");
155	if (!cpu_node)	164	if (!cpu_node)
156	return 0;	165	return 0;
Lines 197-208 Link Here
197	}	206	}
198	seq_printf(m, "\n");	207	seq_printf(m, "\n");
199	}	208	}
		209	pp = (char *) get_property(np, "scb#", &plen);
		210	if (pp != NULL)
		211	seq_printf(m, "board revision\t: %08x\n", ((int )pp));
200	} else	212	} else
201	seq_printf(m, "PowerMac\n");	213	seq_printf(m, "PowerMac\n");
202		214
203	/* print parsed model */	215	/* print parsed model */
204	seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);	216	seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
205	seq_printf(m, "pmac flags\t: %08x\n", mbflags);	217	seq_printf(m, "pmac flags\t: %08x\n", mbflags);
		218	#if 0
		219	{
		220	extern long nap_return_count;
		221	extern long nap_enter_count;
		222	extern long nap_save_msscr0;
		223	extern long dbg_nap_ret;
		224	seq_printf(m, "nap_return_count: %d\n", nap_return_count);
		225	seq_printf(m, "nap_enter_count\t: %d\n", nap_enter_count);
		226	seq_printf(m, "nap_save_msscr0\t: %x\n", nap_save_msscr0);
		227	seq_printf(m, "dbg_nap_ret\t: %x\n", dbg_nap_ret);
		228	}
		229	#endif
206		230
207	/* find l2 cache info */	231	/* find l2 cache info */
208	np = find_devices("l2-cache");	232	np = find_devices("l2-cache");
Lines 309-314 Link Here
309	sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);	333	sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);
310	ohare_init();	334	ohare_init();
311		335
		336	/* Check & display some CPU config registers for diagnostic */
		337	if (pvr == 0x8000 \|\| pvr == 0x8001) { /* 745x */
		338	printk(KERN_INFO "CPU MSCCR0 : 0x%08x\n", mfspr(SPRN_MSSCR0));
		339	printk(KERN_INFO "CPU HID1 : 0x%08x\n", mfspr(SPRN_HID1));
		340	}
		341	if (pvr == 0x0008 \|\| pvr == 0x7000) /* 750's */
		342	printk(KERN_INFO "CPU HID1 : 0x%08x\n", mfspr(SPRN_HID1));
		343
312	/* Lookup PCI hosts */	344	/* Lookup PCI hosts */
313	pmac_find_bridges();	345	pmac_find_bridges();
314		346
Lines 329-334 Link Here
329	}	361	}
330	}	362	}
331		363
		364	#if 0
		365	printk("MSSCR0: %x\n", mfspr(SPRN_MSSCR0));
		366	#endif
332	if (ppc_override_l2cr)	367	if (ppc_override_l2cr)
333	printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",	368	printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",
334	ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)	369	ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)
Lines 823-828 Link Here
823	#endif /* CONFIG_VT */	858	#endif /* CONFIG_VT */
824	}	859	}
825		860
		861	static int __pmac
		862	pmac_ide_reserved_hwifs(void)
		863	{
		864	return 0;
		865	}
		866
826	void __init	867	void __init
827	pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,	868	pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
828	unsigned long r6, unsigned long r7)	869	unsigned long r6, unsigned long r7)
Lines 864-869 Link Here
864	select_adb_keyboard();	905	select_adb_keyboard();
865		906
866	#if defined(CONFIG_BLK_DEV_IDE) \|\| defined(CONFIG_BLK_DEV_IDE_MODULE)	907	#if defined(CONFIG_BLK_DEV_IDE) \|\| defined(CONFIG_BLK_DEV_IDE_MODULE)
		908	ppc_ide_md.reserved_hwifs = pmac_ide_reserved_hwifs;
867	#ifdef CONFIG_BLK_DEV_IDE_PMAC	909	#ifdef CONFIG_BLK_DEV_IDE_PMAC
868	ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports;	910	ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports;
869	ppc_ide_md.default_io_base = pmac_ide_get_base;	911	ppc_ide_md.default_io_base = pmac_ide_get_base;

Lines 44-50 Link Here

(-)linux-2.4.22/arch/ppc/platforms/pmac_sleep.S (-2 / +2 lines)
44	.text	44	.text
45	.align 5	45	.align 5
46		46
47	#if defined(CONFIG_PMAC_PBOOK)	47	#if defined(CONFIG_PMAC_PBOOK) \|\| defined(CONFIG_CPU_FREQ_PMAC)
48		48
49	/* This gets called by via-pmu.c late during the sleep process.	49	/* This gets called by via-pmu.c late during the sleep process.
50	* The PMU was already send the sleep command and will shut us down	50	* The PMU was already send the sleep command and will shut us down
Lines 372-378 Link Here
372	isync	372	isync
373	rfi	373	rfi
374		374
375	#endif /* defined(CONFIG_PMAC_PBOOK) */	375	#endif /* defined(CONFIG_PMAC_PBOOK) \|\| defined(CONFIG_CPU_FREQ) */
376		376
377	.data	377	.data
378	.balign L1_CACHE_LINE_SIZE	378	.balign L1_CACHE_LINE_SIZE

Lines 12-17 Link Here

(-)linux-2.4.22/arch/ppc/xmon/start.c (-6 / +164 lines)
12	#include <linux/kernel.h>	12	#include <linux/kernel.h>
13	#include <linux/errno.h>	13	#include <linux/errno.h>
14	#include <linux/sysrq.h>	14	#include <linux/sysrq.h>
		15	#include <linux/delay.h>
15	#include <asm/prom.h>	16	#include <asm/prom.h>
16	#include <asm/bootx.h>	17	#include <asm/bootx.h>
17	#include <asm/machdep.h>	18	#include <asm/machdep.h>
Lines 24-39 Link Here
24	#include <asm/bitops.h>	25	#include <asm/bitops.h>
25	#endif	26	#endif
26		27
		28	#define CONFIG_XMON_FW
		29
27	static volatile unsigned char sccc, sccd;	30	static volatile unsigned char sccc, sccd;
28	unsigned int TXRDY, RXRDY, DLAB;	31	unsigned int TXRDY, RXRDY, DLAB;
29	extern void xmon_printf(const char *fmt, ...);	32	extern void xmon_printf(const char *fmt, ...);
30	static int xmon_expect(const char *str, unsigned int timeout);	33	static int xmon_expect(const char *str, unsigned int timeout);
		34	extern char cmd_line[512];
31		35
32	static int use_screen;	36	static int use_screen;
33	static int via_modem;	37	static int via_modem;
34	static int xmon_use_sccb;	38	static int xmon_use_sccb;
35	static struct device_node *channel_node;	39	static struct device_node *channel_node;
36		40
		41	/* There are used when hooked via firewire */
		42	#ifdef CONFIG_XMON_FW
		43	volatile unsigned int xmon_fw_outbuf_size;
		44	volatile unsigned char xmon_fw_outbuf[1024];
		45	volatile unsigned int xmon_fw_oflags;
		46	volatile unsigned int xmon_fw_iflags;
		47	volatile unsigned int xmon_fw_idata;
		48	#define XMON_FW_FLAGS_OUT_ENTERED 0x00000001
		49	#define XMON_FW_FLAGS_OUT_DATA 0x00000002
		50	#define XMON_FW_FLAGS_OUT_ACK 0x00000004
		51	#define XMON_FW_FLAGS_IN_ATTACHED 0x00000001
		52	#define XMON_FW_FLAGS_IN_DATA 0x00000002
		53	#define XMON_FW_FLAGS_IN_ACK 0x00000004
		54	#endif
		55
37	#define TB_SPEED 25000000	56	#define TB_SPEED 25000000
38		57
39	static inline unsigned int readtb(void)	58	static inline unsigned int readtb(void)
Lines 112-118 Link Here
112	volatile unsigned char *base;	131	volatile unsigned char *base;
113		132
114	use_screen = 0;	133	use_screen = 0;
115		134	/* Typically used for firewire debugging */
		135	if (strstr(cmd_line, "xmon_noio"))
		136	return;
116	if (_machine == _MACH_Pmac) {	137	if (_machine == _MACH_Pmac) {
117	struct device_node *np;	138	struct device_node *np;
118	unsigned long addr;	139	unsigned long addr;
Lines 215-234 Link Here
215	DLAB = 0x80;	236	DLAB = 0x80;
216	#endif /* platform */	237	#endif /* platform */
217		238
		239	#ifdef CONFIG_MAGIC_SYSRQ
218	__sysrq_put_key_op('x', &sysrq_xmon_op);	240	__sysrq_put_key_op('x', &sysrq_xmon_op);
		241	#endif
219	}	242	}
220		243
221	static int scc_initialized = 0;	244	static int scc_initialized = 0;
222		245
223	void xmon_init_scc(void);	246	void xmon_init_scc(void);
224	extern void pmu_poll(void);
225	extern void cuda_poll(void);	247	extern void cuda_poll(void);
226		248
227	static inline void do_poll_adb(void)	249	static inline void do_poll_adb(void)
228	{	250	{
229	#ifdef CONFIG_ADB_PMU	251	#ifdef CONFIG_ADB_PMU
230	if (sys_ctrler == SYS_CTRLER_PMU)	252	if (sys_ctrler == SYS_CTRLER_PMU)
231	pmu_poll();	253	pmu_poll_adb();
232	#endif /* CONFIG_ADB_PMU */	254	#endif /* CONFIG_ADB_PMU */
233	#ifdef CONFIG_ADB_CUDA	255	#ifdef CONFIG_ADB_CUDA
234	if (sys_ctrler == SYS_CTRLER_CUDA)	256	if (sys_ctrler == SYS_CTRLER_CUDA)
Lines 236-241 Link Here
236	#endif /* CONFIG_ADB_CUDA */	258	#endif /* CONFIG_ADB_CUDA */
237	}	259	}
238		260
		261	#if 0
		262	static void
		263	bx_printf(const char* fmt, ...)
		264	{
		265	static char dbgbuf[2048];
		266	va_list ap;
		267	int n;
		268
		269	va_start(ap, fmt);
		270	n = vsprintf(dbgbuf, fmt, ap);
		271	va_end(ap);
		272	btext_drawstring(dbgbuf);
		273	}
		274	#endif
		275
		276	#ifdef CONFIG_XMON_FW
		277	static int
		278	xmon_fw_write(void* ptr, int nb)
		279	{
		280	char* p = (char *)ptr;
		281	int c, i;
		282
		283	while (nb && (xmon_fw_iflags & XMON_FW_FLAGS_IN_ATTACHED)) {
		284	c = (nb > 1024) ? 1024 : nb;
		285	memcpy((void *)xmon_fw_outbuf, p, c);
		286	xmon_fw_outbuf_size = c;
		287	wmb();
		288	xmon_fw_oflags \|= XMON_FW_FLAGS_OUT_DATA;
		289	wmb();
		290	for (i=0; i<1000; i++) {
		291	rmb();
		292	if (xmon_fw_iflags & XMON_FW_FLAGS_IN_ACK)
		293	break;
		294	mdelay(1);
		295	}
		296	xmon_fw_oflags &= ~XMON_FW_FLAGS_OUT_DATA;
		297	wmb();
		298	if ((xmon_fw_iflags & XMON_FW_FLAGS_IN_ACK) == 0) {
		299	xmon_fw_iflags = 0;
		300	break;
		301	}
		302	for (i=0; i<1000; i++) {
		303	rmb();
		304	if ((xmon_fw_iflags & XMON_FW_FLAGS_IN_ACK) == 0)
		305	break;
		306	mdelay(1);
		307	}
		308	if ((xmon_fw_iflags & XMON_FW_FLAGS_IN_ACK) != 0) {
		309	xmon_fw_iflags = 0;
		310	break;
		311	}
		312	nb -= c;
		313	p += c;
		314	}
		315	return (xmon_fw_iflags & XMON_FW_FLAGS_IN_ATTACHED) != 0;
		316	}
		317
		318	static int
		319	xmon_fw_read(void* ptr, int nb)
		320	{
		321	int t, on, i;
		322	unsigned int k;
		323	char c[3];
		324	char* p = (char *)ptr;
325
326	while (nb) {
327	t = 0;
328	on = 0;
329	while(xmon_fw_iflags & XMON_FW_FLAGS_IN_ATTACHED) {
330	if (xmon_fw_iflags & XMON_FW_FLAGS_IN_DATA)
331	break;
332	if (--t < 0) {
333	on = 1 - on;
334	c[0] = on? 0xdb: 0x20;
335	c[1] = '\b';
336	if (!xmon_fw_write(c, 2))
337	break;
338	t = 2000000;
339	}
340	rmb();
341	}
342	k = xmon_fw_idata & 0xff;
343	xmon_fw_oflags \|= XMON_FW_FLAGS_OUT_ACK;
344	wmb();
345	for (i=0; i<1000; i++) {
346	rmb();
347	if ((xmon_fw_iflags & XMON_FW_FLAGS_IN_DATA) == 0)
348	break;
349	mdelay(1);
350	}
351	if (xmon_fw_iflags & XMON_FW_FLAGS_IN_DATA) {
352	xmon_fw_iflags = 0;
353	break;
354	}
355	xmon_fw_oflags &= ~XMON_FW_FLAGS_OUT_ACK;
356	wmb();
357	if (on) {
358	c[0] = 0x20; c[1] = '\b';
359	xmon_fw_write(c, 2);
360	}
361	*(p++) = k;
362	nb--;
363	}
364	return (xmon_fw_iflags & XMON_FW_FLAGS_IN_ATTACHED) != 0;
365	}
366
367	#endif /* CONFIG_XMON_FW */
368
239	int	369	int
240	xmon_write(void handle, void ptr, int nb)	370	xmon_write(void handle, void ptr, int nb)
241	{	371	{
Lines 251-259 Link Here
251	if (--lock_wait == 0)	381	if (--lock_wait == 0)
252	break;	382	break;
253	#endif	383	#endif
254		384	#ifdef CONFIG_XMON_FW
		385	if (xmon_fw_write(ptr, nb))
		386	goto out;
		387	#endif /* CONFIG_XMON_FW */
255	#ifdef CONFIG_BOOTX_TEXT	388	#ifdef CONFIG_BOOTX_TEXT
256	if (use_screen) {	389	#ifdef CONFIG_MORE_DEBUG
		390	if (1)
		391	#else
		392	if (use_screen)
		393	#endif
		394	{
257	/* write it on the screen */	395	/* write it on the screen */
258	for (i = 0; i < nb; ++i)	396	for (i = 0; i < nb; ++i)
259	btext_drawchar(*p++);	397	btext_drawchar(*p++);
Lines 262-267 Link Here
262	#endif	400	#endif
263	if (!scc_initialized)	401	if (!scc_initialized)
264	xmon_init_scc();	402	xmon_init_scc();
		403	if (!sccd)
		404	goto out;
		405
265	ct = 0;	406	ct = 0;
266	for (i = 0; i < nb; ++i) {	407	for (i = 0; i < nb; ++i) {
267	while ((*sccc & TXRDY) == 0)	408	while ((*sccc & TXRDY) == 0)
Lines 354-359 Link Here
354	char *p = ptr;	495	char *p = ptr;
355	int i;	496	int i;
356		497
		498	#ifdef CONFIG_XMON_FW
		499	if (xmon_fw_read(ptr, nb))
		500	return nb;
		501	#endif /* CONFIG_XMON_FW */
357	#ifdef CONFIG_BOOTX_TEXT	502	#ifdef CONFIG_BOOTX_TEXT
358	if (use_screen) {	503	if (use_screen) {
359	for (i = 0; i < nb; ++i)	504	for (i = 0; i < nb; ++i)
Lines 363-368 Link Here
363	#endif	508	#endif
364	if (!scc_initialized)	509	if (!scc_initialized)
365	xmon_init_scc();	510	xmon_init_scc();
		511	if (sccd == NULL)
		512	return 0;
366	for (i = 0; i < nb; ++i) {	513	for (i = 0; i < nb; ++i) {
367	while ((*sccc & RXRDY) == 0)	514	while ((*sccc & RXRDY) == 0)
368	do_poll_adb();	515	do_poll_adb();
Lines 385-391 Link Here
385		532
386	static unsigned char scc_inittab[] = {	533	static unsigned char scc_inittab[] = {
387	13, 0, /* set baud rate divisor */	534	13, 0, /* set baud rate divisor */
388	12, 1,	535	// 12, 1,
		536	12, 0,
389	14, 1, /* baud rate gen enable, src=rtxc */	537	14, 1, /* baud rate gen enable, src=rtxc */
390	11, 0x50, /* clocks = br gen */	538	11, 0x50, /* clocks = br gen */
391	5, 0xea, /* tx 8 bits, assert DTR & RTS */	539	5, 0xea, /* tx 8 bits, assert DTR & RTS */
Lines 396-401 Link Here
396	void	544	void
397	xmon_init_scc()	545	xmon_init_scc()
398	{	546	{
		547	if (sccd == NULL && channel_node == NULL)
		548	return;
399	if ( _machine == _MACH_chrp )	549	if ( _machine == _MACH_chrp )
400	{	550	{
401	sccd[3] = 0x83; eieio(); /* LCR = 8N1 + DLAB */	551	sccd[3] = 0x83; eieio(); /* LCR = 8N1 + DLAB */
Lines 634-644 Link Here
634	pmu_suspend();	784	pmu_suspend();
635	}	785	}
636	#endif	786	#endif
		787	#ifdef CONFIG_XMON_FW
		788	xmon_fw_oflags \|= XMON_FW_FLAGS_OUT_ENTERED;
		789	wmb();
		790	#endif /* CONFIG_XMON_FW */
637	}	791	}
638		792
639	void	793	void
640	xmon_leave(void)	794	xmon_leave(void)
641	{	795	{
		796	#ifdef CONFIG_XMON_FW
		797	xmon_fw_oflags &= ~XMON_FW_FLAGS_OUT_ENTERED;
		798	wmb();
		799	#endif /* CONFIG_XMON_FW */
642	#ifdef CONFIG_ADB_PMU	800	#ifdef CONFIG_ADB_PMU
643	if (_machine == _MACH_Pmac) {	801	if (_machine == _MACH_Pmac) {
644	pmu_resume();	802	pmu_resume();




#endif /* CONFIG_SMP */
	remove_bpts();
#ifdef CONFIG_PMAC_BACKLIGHT
	if (_machine == _MACH_Pmac) {
		if( setjmp(bus_error_jmp) == 0 ) {
			debugger_fault_handler = handle_fault;
			sync();
			set_backlight_enable(1);
			set_backlight_level(BACKLIGHT_MAX);
			sync();
		}
		debugger_fault_handler = 0;
	}
	debugger_fault_handler = 0;
#endif	/* CONFIG_PMAC_BACKLIGHT */
	cmd = cmds(excp);
	if (cmd == 's') {

Lines 210-216 Link Here

(-)linux-2.4.22/arch/s390/mm/fault.c (-1 / +1 lines)
210	goto good_area;	210	goto good_area;
211	if (!(vma->vm_flags & VM_GROWSDOWN))	211	if (!(vma->vm_flags & VM_GROWSDOWN))
212	goto bad_area;	212	goto bad_area;
213	if (expand_stack(vma, address))	213	if (expand_stack(vma, address, NULL))
214	goto bad_area;	214	goto bad_area;
215	/*	215	/*
216	* Ok, we have a good vm_area for this memory access, so	216	* Ok, we have a good vm_area for this memory access, so

Lines 210-216 Link Here

(-)linux-2.4.22/arch/s390x/mm/fault.c (-1 / +1 lines)
210	goto good_area;	210	goto good_area;
211	if (!(vma->vm_flags & VM_GROWSDOWN))	211	if (!(vma->vm_flags & VM_GROWSDOWN))
212	goto bad_area;	212	goto bad_area;
213	if (expand_stack(vma, address))	213	if (expand_stack(vma, address, NULL))
214	goto bad_area;	214	goto bad_area;
215	/*	215	/*
216	* Ok, we have a good vm_area for this memory access, so	216	* Ok, we have a good vm_area for this memory access, so

Lines 78-84 Link Here

(-)linux-2.4.22/arch/sh/mm/fault.c (-2 / +2 lines)
78	check_stack:	78	check_stack:
79	if (!(vma->vm_flags & VM_GROWSDOWN))	79	if (!(vma->vm_flags & VM_GROWSDOWN))
80	goto bad_area;	80	goto bad_area;
81	if (expand_stack(vma, start) == 0)	81	if (expand_stack(vma, start, NULL) == 0)
82	goto good_area;	82	goto good_area;
83		83
84	bad_area:	84	bad_area:
Lines 123-129 Link Here
123	goto good_area;	123	goto good_area;
124	if (!(vma->vm_flags & VM_GROWSDOWN))	124	if (!(vma->vm_flags & VM_GROWSDOWN))
125	goto bad_area;	125	goto bad_area;
126	if (expand_stack(vma, address))	126	if (expand_stack(vma, address, NULL))
127	goto bad_area;	127	goto bad_area;
128	/*	128	/*
129	* Ok, we have a good vm_area for this memory access, so	129	* Ok, we have a good vm_area for this memory access, so

Lines 251-257 Link Here

(-)linux-2.4.22/arch/sparc/mm/fault.c (-2 / +2 lines)
251	goto good_area;	251	goto good_area;
252	if(!(vma->vm_flags & VM_GROWSDOWN))	252	if(!(vma->vm_flags & VM_GROWSDOWN))
253	goto bad_area;	253	goto bad_area;
254	if(expand_stack(vma, address))	254	if(expand_stack(vma, address, NULL))
255	goto bad_area;	255	goto bad_area;
256	/*	256	/*
257	* Ok, we have a good vm_area for this memory access, so	257	* Ok, we have a good vm_area for this memory access, so
Lines 498-504 Link Here
498	goto good_area;	498	goto good_area;
499	if(!(vma->vm_flags & VM_GROWSDOWN))	499	if(!(vma->vm_flags & VM_GROWSDOWN))
500	goto bad_area;	500	goto bad_area;
501	if(expand_stack(vma, address))	501	if(expand_stack(vma, address, NULL))
502	goto bad_area;	502	goto bad_area;
503	good_area:	503	good_area:
504	info.si_code = SEGV_ACCERR;	504	info.si_code = SEGV_ACCERR;

Lines 389-395 Link Here

(-)linux-2.4.22/arch/sparc64/mm/fault.c (-1 / +1 lines)
389	goto bad_area;	389	goto bad_area;
390	}	390	}
391	}	391	}
392	if (expand_stack(vma, address))	392	if (expand_stack(vma, address, NULL))
393	goto bad_area;	393	goto bad_area;
394	/*	394	/*
395	* Ok, we have a good vm_area for this memory access, so	395	* Ok, we have a good vm_area for this memory access, so

Lines 121-126 Link Here

(-)linux-2.4.22/drivers/block/ll_rw_blk.c (+33 lines)
121	unsigned long blk_max_low_pfn, blk_max_pfn;	121	unsigned long blk_max_low_pfn, blk_max_pfn;
122	int blk_nohighio = 0;	122	int blk_nohighio = 0;
123		123
		124	int block_dump = 0;
		125
		126	static struct timer_list writeback_timer;
		127
124	static inline int get_max_sectors(kdev_t dev)	128	static inline int get_max_sectors(kdev_t dev)
125	{	129	{
126	if (!max_sectors[MAJOR(dev)])	130	if (!max_sectors[MAJOR(dev)])
Lines 158-163 Link Here
158	return i;	162	return i;
159	}	163	}
160		164
		165	void blk_queue_activity_fn(request_queue_t q, activity_fn fn, void *data)
		166	{
		167	q->activity_fn = fn;
		168	q->activity_data = data;
		169	}
		170
161	/**	171	/**
162	* blk_cleanup_queue: - release a &request_queue_t when it is no longer needed	172	* blk_cleanup_queue: - release a &request_queue_t when it is no longer needed
163	* @q: the request queue to be released	173	* @q: the request queue to be released
Lines 540-545 Link Here
540	q->head_active = 1;	550	q->head_active = 1;
541		551
542	blk_queue_bounce_limit(q, BLK_BOUNCE_HIGH);	552	blk_queue_bounce_limit(q, BLK_BOUNCE_HIGH);
		553	blk_queue_activity_fn(q, NULL, NULL);
543	}	554	}
544		555
545	#define blkdev_free_rq(list) list_entry((list)->next, struct request, queue);	556	#define blkdev_free_rq(list) list_entry((list)->next, struct request, queue);
Lines 855-860 Link Here
855	static inline void add_request(request_queue_t * q, struct request * req,	866	static inline void add_request(request_queue_t * q, struct request * req,
856	struct list_head *insert_here)	867	struct list_head *insert_here)
857	{	868	{
		869	if (q->activity_fn)
		870	q->activity_fn(q->activity_data, req->cmd);
		871
858	drive_stat_acct(req->rq_dev, req->cmd, req->nr_sectors, 1);	872	drive_stat_acct(req->rq_dev, req->cmd, req->nr_sectors, 1);
859		873
860	if (!q->plugged && q->head_active && insert_here == &q->queue_head) {	874	if (!q->plugged && q->head_active && insert_here == &q->queue_head) {
Lines 1302-1307 Link Here
1302	kstat.pgpgin += count;	1316	kstat.pgpgin += count;
1303	break;	1317	break;
1304	}	1318	}
		1319
		1320	if (block_dump)
		1321	printk("%s: %s block %lu/%u on %s\n", current->comm, rw == WRITE ? "WRITE" : "READ", bh->b_rsector, count, kdevname(bh->b_rdev));
1305	}	1322	}
1306		1323
1307	/**	1324	/**
Lines 1413-1418 Link Here
1413	extern int stram_device_init (void);	1430	extern int stram_device_init (void);
1414	#endif	1431	#endif
1415		1432
		1433	static void blk_writeback_timer(unsigned long data)
		1434	{
		1435	wakeup_bdflush();
		1436	wakeup_kupdate();
		1437	}
1416		1438
1417	/**	1439	/**
1418	* end_that_request_first - end I/O on one buffer.	1440	* end_that_request_first - end I/O on one buffer.
Lines 1469-1478 Link Here
1469	return 0;	1491	return 0;
1470	}	1492	}
1471		1493
		1494	extern int laptop_mode;
		1495
1472	void end_that_request_last(struct request *req)	1496	void end_that_request_last(struct request *req)
1473	{	1497	{
1474	struct completion *waiting = req->waiting;	1498	struct completion *waiting = req->waiting;
1475		1499
		1500	/*
		1501	* schedule the writeout of pending dirty data when the disk is idle
		1502	*/
		1503	if (laptop_mode && req->cmd == READ)
		1504	mod_timer(&writeback_timer, jiffies + 5 * HZ);
		1505
1476	req_finished_io(req);	1506	req_finished_io(req);
1477	blkdev_release_request(req);	1507	blkdev_release_request(req);
1478	if (waiting)	1508	if (waiting)
Lines 1500-1505 Link Here
1500	blk_max_low_pfn = max_low_pfn - 1;	1530	blk_max_low_pfn = max_low_pfn - 1;
1501	blk_max_pfn = max_pfn - 1;	1531	blk_max_pfn = max_pfn - 1;
1502		1532
		1533	init_timer(&writeback_timer);
		1534	writeback_timer.function = blk_writeback_timer;
		1535
1503	#ifdef CONFIG_AMIGA_Z2RAM	1536	#ifdef CONFIG_AMIGA_Z2RAM
1504	z2_init();	1537	z2_init();
1505	#endif	1538	#endif

Lines 315-320 Link Here

(-)linux-2.4.22/drivers/char/Config.in (+1 lines)
315	if [ "$CONFIG_IA64" = "y" ]; then	315	if [ "$CONFIG_IA64" = "y" ]; then
316	bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1	316	bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
317	fi	317	fi
		318	dep_bool ' Apple UniNorth support' CONFIG_AGP_UNINORTH $CONFIG_ALL_PPC
318	fi	319	fi
319		320
320	bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM	321	bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM

Lines 52-57 Link Here

(-)linux-2.4.22/drivers/char/agp/agpgart_be.c (-1 / +430 lines)
52	#ifdef CONFIG_AGP_NVIDIA	52	#ifdef CONFIG_AGP_NVIDIA
53	#include <asm/msr.h>	53	#include <asm/msr.h>
54	#endif	54	#endif
		55	#ifdef CONFIG_AGP_UNINORTH
		56	#include <asm/uninorth.h>
		57	#endif
55		58
56	#include <linux/agp_backend.h>	59	#include <linux/agp_backend.h>
57	#include "agp.h"	60	#include "agp.h"
Lines 80-86 Link Here
80	{	83	{
81	#if defined(__i386__) \|\| defined(__x86_64__)	84	#if defined(__i386__) \|\| defined(__x86_64__)
82	asm volatile ("wbinvd":::"memory");	85	asm volatile ("wbinvd":::"memory");
83	#elif defined(__alpha__) \|\| defined(__ia64__) \|\| defined(__sparc__)	86	#elif defined(__alpha__) \|\| defined(__ia64__) \|\| defined(__sparc__) \|\| defined(__powerpc__)
84	/* ??? I wonder if we'll really need to flush caches, or if the	87	/* ??? I wonder if we'll really need to flush caches, or if the
85	core logic can manage to keep the system coherent. The ARM	88	core logic can manage to keep the system coherent. The ARM
86	speaks only of using `cflush' to get things in memory in	89	speaks only of using `cflush' to get things in memory in
Lines 4735-4740 Link Here
4735		4738
4736	#endif /* CONFIG_AGP_HP_ZX1 */	4739	#endif /* CONFIG_AGP_HP_ZX1 */
4737		4740
		4741	#ifdef CONFIG_AGP_UNINORTH
		4742
		4743	static int uninorth_fetch_size(void)
		4744	{
		4745	int i;
		4746	u32 temp;
		4747	aper_size_info_32 *values;
		4748
		4749	pci_read_config_dword(agp_bridge.dev, UNI_N_CFG_GART_BASE, &temp);
		4750	temp &= ~(0xfffff000);
		4751	values = A_SIZE_32(agp_bridge.aperture_sizes);
		4752
		4753	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
		4754	if (temp == values[i].size_value) {
		4755	agp_bridge.previous_size =
		4756	agp_bridge.current_size = (void *) (values + i);
		4757	agp_bridge.aperture_size_idx = i;
		4758	return values[i].size;
		4759	}
		4760	}
		4761
		4762	agp_bridge.previous_size =
		4763	agp_bridge.current_size = (void *) (values + 1);
		4764	agp_bridge.aperture_size_idx = 1;
		4765	return values[1].size;
		4766
		4767	return 0;
		4768	}
		4769
		4770	static void uninorth_tlbflush(agp_memory * mem)
		4771	{
		4772	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4773	UNI_N_CFG_GART_ENABLE \| UNI_N_CFG_GART_INVAL);
		4774	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4775	UNI_N_CFG_GART_ENABLE);
		4776	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4777	UNI_N_CFG_GART_ENABLE \| UNI_N_CFG_GART_2xRESET);
		4778	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4779	UNI_N_CFG_GART_ENABLE);
		4780	}
		4781
		4782	static void uninorth_cleanup(void)
		4783	{
		4784	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4785	UNI_N_CFG_GART_ENABLE \| UNI_N_CFG_GART_INVAL);
		4786	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4787	0);
		4788	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4789	UNI_N_CFG_GART_2xRESET);
		4790	pci_write_config_dword(agp_bridge.dev, UNI_N_CFG_GART_CTRL,
		4791	0);
		4792	}
		4793
		4794	static int uninorth_configure(void)
		4795	{
		4796	aper_size_info_32 *current_size;
		4797
		4798	current_size = A_SIZE_32(agp_bridge.current_size);
		4799
		4800	printk("agp: configuring for size idx: %d\n", current_size->size_value);
		4801
		4802	/* aperture size and gatt addr */
		4803	pci_write_config_dword(agp_bridge.dev,
		4804	UNI_N_CFG_GART_BASE,
4805	(agp_bridge.gatt_bus_addr & 0xfffff000)
4806	\| current_size->size_value);
4807
4808	/* HACK ALERT
4809	* UniNorth seem to be buggy enough not to handle properly when
4810	* the AGP aperture isn't mapped at bus physical address 0
4811	*/
4812	agp_bridge.gart_bus_addr = 0;
4813	pci_write_config_dword(agp_bridge.dev,
4814	UNI_N_CFG_AGP_BASE, agp_bridge.gart_bus_addr);
4815
4816	return 0;
4817	}
4818
4819	static unsigned long uninorth_mask_memory(unsigned long addr, int type)
4820	{
4821	return addr;/* \| agp_bridge.masks[0].mask;*/
4822	}
4823
4824	static int uninorth_insert_memory(agp_memory * mem,
4825	off_t pg_start, int type)
4826	{
4827	int i, j, num_entries;
4828	void *temp;
4829
4830	temp = agp_bridge.current_size;
4831	num_entries = A_SIZE_32(temp)->num_entries;
4832
4833	if (type != 0 \|\| mem->type != 0) {
4834	/* The generic routines know nothing of memory types */
4835	return -EINVAL;
4836	}
4837	if ((pg_start + mem->page_count) > num_entries) {
4838	return -EINVAL;
4839	}
4840	j = pg_start;
4841
4842	while (j < (pg_start + mem->page_count)) {
4843	if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
4844	return -EBUSY;
4845	}
4846	j++;
4847	}
4848
4849	if (mem->is_flushed == FALSE) {
4850	CACHE_FLUSH();
4851	mem->is_flushed = TRUE;
4852	}
4853	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
4854	agp_bridge.gatt_table[j] = cpu_to_le32((mem->memory[i] & 0xfffff000) \| 0x00000001UL);
4855	flush_dcache_range(__va(mem->memory[i]), __va(mem->memory[i])+0x1000);
4856	}
4857	(void)in_le32((volatile u32*)&agp_bridge.gatt_table[pg_start]);
4858	mb();
4859	flush_dcache_range((unsigned long)&agp_bridge.gatt_table[pg_start],
4860	(unsigned long)&agp_bridge.gatt_table[pg_start + mem->page_count]);
4861
4862	agp_bridge.tlb_flush(mem);
4863	return 0;
4864	}
4865
4866	static void uninorth_agp_enable(u32 mode)
4867	{
4868	struct pci_dev *device = NULL;
4869	u32 command, scratch, cap_id;
4870	u8 cap_ptr;
4871
4872	pci_read_config_dword(agp_bridge.dev,
4873	agp_bridge.capndx + 4,
4874	&command);
4875
4876	/*
4877	* PASS1: go throu all devices that claim to be
4878	* AGP devices and collect their data.
4879	*/
4880
4881	while ((device = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8,
4882	device)) != NULL) {
4883	pci_read_config_dword(device, 0x04, &scratch);
4884
4885	if (!(scratch & 0x00100000))
4886	continue;
4887
4888	pci_read_config_byte(device, 0x34, &cap_ptr);
4889
4890	if (cap_ptr != 0x00) {
4891	do {
4892	pci_read_config_dword(device,
4893	cap_ptr, &cap_id);
4894
4895	if ((cap_id & 0xff) != 0x02)
4896	cap_ptr = (cap_id >> 8) & 0xff;
4897	}
4898	while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
4899	}
4900	if (cap_ptr != 0x00) {
4901	/*
4902	* Ok, here we have a AGP device. Disable impossible
4903	* settings, and adjust the readqueue to the minimum.
4904	*/
4905
4906	pci_read_config_dword(device, cap_ptr + 4, &scratch);
4907
4908	/* adjust RQ depth */
4909	command =
4910	((command & ~0xff000000) \|
4911	min_t(u32, (mode & 0xff000000),
4912	min_t(u32, (command & 0xff000000),
4913	(scratch & 0xff000000))));
4914
4915	/* disable SBA if it's not supported */
4916	if (!((command & 0x00000200) &&
4917	(scratch & 0x00000200) &&
4918	(mode & 0x00000200)))
4919	command &= ~0x00000200;
4920
4921	/* disable FW if it's not supported */
4922	if (!((command & 0x00000010) &&
4923	(scratch & 0x00000010) &&
4924	(mode & 0x00000010)))
4925	command &= ~0x00000010;
4926
4927	if (!((command & 4) &&
4928	(scratch & 4) &&
4929	(mode & 4)))
4930	command &= ~0x00000004;
4931
4932	if (!((command & 2) &&
4933	(scratch & 2) &&
4934	(mode & 2)))
4935	command &= ~0x00000002;
4936
4937	if (!((command & 1) &&
4938	(scratch & 1) &&
4939	(mode & 1)))
4940	command &= ~0x00000001;
4941	}
4942	}
4943	/*
4944	* PASS2: Figure out the 4X/2X/1X setting and enable the
4945	* target (our motherboard chipset).
4946	*/
4947
4948	if (command & 4) {
4949	command &= ~3; /* 4X */
4950	}
4951	if (command & 2) {
4952	command &= ~5; /* 2X */
4953	}
4954	if (command & 1) {
4955	command &= ~6; /* 1X */
4956	}
4957	command \|= 0x00000100;
4958
4959	uninorth_tlbflush(NULL);
4960
4961	do {
4962	pci_write_config_dword(agp_bridge.dev,
4963	agp_bridge.capndx + 8,
4964	command);
4965	pci_read_config_dword(agp_bridge.dev,
4966	agp_bridge.capndx + 8,
4967	&scratch);
4968	} while((scratch & 0x100) == 0);
4969
4970	/*
4971	* PASS3: Go throu all AGP devices and update the
4972	* command registers.
4973	*/
4974
4975	while ((device = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8,
4976	device)) != NULL) {
4977	pci_read_config_dword(device, 0x04, &scratch);
4978
4979	if (!(scratch & 0x00100000))
4980	continue;
4981
4982	pci_read_config_byte(device, 0x34, &cap_ptr);
4983
4984	if (cap_ptr != 0x00) {
4985	do {
4986	pci_read_config_dword(device,
4987	cap_ptr, &cap_id);
4988
4989	if ((cap_id & 0xff) != 0x02)
4990	cap_ptr = (cap_id >> 8) & 0xff;
4991	}
4992	while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
4993	}
4994	if (cap_ptr != 0x00)
4995	pci_write_config_dword(device, cap_ptr + 8, command);
4996	}
4997
4998	uninorth_tlbflush(NULL);
4999	}
5000
5001	static int uninorth_create_gatt_table(void)
5002	{
5003	char *table;
5004	char *table_end;
5005	int size;
5006	int page_order;
5007	int num_entries;
5008	int i;
5009	void *temp;
5010	struct page *page;
5011
5012	/* The generic routines can't handle 2 level gatt's */
5013	if (agp_bridge.size_type == LVL2_APER_SIZE) {
5014	return -EINVAL;
5015	}
5016
5017	table = NULL;
5018	i = agp_bridge.aperture_size_idx;
5019	temp = agp_bridge.current_size;
5020	size = page_order = num_entries = 0;
5021
5022	do {
5023	size = A_SIZE_32(temp)->size;
5024	page_order = A_SIZE_32(temp)->page_order;
5025	num_entries = A_SIZE_32(temp)->num_entries;
5026
5027	table = (char *) __get_free_pages(GFP_KERNEL, page_order);
5028
5029	if (table == NULL) {
5030	i++;
5031	agp_bridge.current_size = A_IDX32();
5032	} else {
5033	agp_bridge.aperture_size_idx = i;
5034	}
5035	} while ((table == NULL) &&
5036	(i < agp_bridge.num_aperture_sizes));
5037
5038	if (table == NULL) {
5039	return -ENOMEM;
5040	}
5041	table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
5042
5043	for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
5044	SetPageReserved(page);
5045
5046	agp_bridge.gatt_table_real = (unsigned long *) table;
5047	agp_bridge.gatt_table = (unsigned long *)table;
5048	agp_bridge.gatt_bus_addr = virt_to_phys(table);
5049
5050	for (i = 0; i < num_entries; i++) {
5051	agp_bridge.gatt_table[i] =
5052	(unsigned long) agp_bridge.scratch_page;
5053	}
5054
5055	flush_dcache_range((unsigned long)table, (unsigned long)table_end);
5056
5057	return 0;
5058	}
5059
5060	static int uninorth_free_gatt_table(void)
5061	{
5062	int page_order;
5063	char table, table_end;
5064	void *temp;
5065	struct page *page;
5066
5067	temp = agp_bridge.current_size;
5068	page_order = A_SIZE_32(temp)->page_order;
5069
5070	/* Do not worry about freeing memory, because if this is
5071	* called, then all agp memory is deallocated and removed
5072	* from the table.
5073	*/
5074
5075	table = (char *) agp_bridge.gatt_table_real;
5076	table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
5077
5078	for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
5079	ClearPageReserved(page);
5080
5081	free_pages((unsigned long) agp_bridge.gatt_table_real, page_order);
5082
5083	return 0;
5084	}
5085
5086
5087	/* Setup function */
5088	static gatt_mask uninorth_masks[] =
5089	{
5090	{0x00000000, 0}
5091	};
5092
5093	static aper_size_info_32 uninorth_sizes[7] =
5094	{
5095	#if 0 /* Not sure uninorth supports that high aperture sizes */
5096	{256, 65536, 6, 64},
5097	{128, 32768, 5, 32},
5098	{64, 16384, 4, 16},
5099	#endif
5100	{32, 8192, 3, 8},
5101	{16, 4096, 2, 4},
5102	{8, 2048, 1, 2},
5103	{4, 1024, 0, 1}
5104	};
5105
5106	static int __init uninorth_setup (struct pci_dev *pdev)
5107	{
5108	agp_bridge.masks = uninorth_masks;
5109	agp_bridge.aperture_sizes = (void *)uninorth_sizes;
5110	agp_bridge.size_type = U32_APER_SIZE;
5111	agp_bridge.num_aperture_sizes = 4; //7;
5112	agp_bridge.dev_private_data = NULL;
5113	agp_bridge.needs_scratch_page = FALSE;
5114	agp_bridge.configure = uninorth_configure;
5115	agp_bridge.fetch_size = uninorth_fetch_size;
5116	agp_bridge.cleanup = uninorth_cleanup;
5117	agp_bridge.tlb_flush = uninorth_tlbflush;
5118	agp_bridge.mask_memory = uninorth_mask_memory;
5119	agp_bridge.agp_enable = uninorth_agp_enable;
5120	agp_bridge.cache_flush = global_cache_flush;
5121	agp_bridge.create_gatt_table = uninorth_create_gatt_table;
5122	agp_bridge.free_gatt_table = uninorth_free_gatt_table;
5123	agp_bridge.insert_memory = uninorth_insert_memory;
5124	agp_bridge.remove_memory = agp_generic_remove_memory;
5125	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
5126	agp_bridge.free_by_type = agp_generic_free_by_type;
5127	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
5128	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
5129	agp_bridge.suspend = agp_generic_suspend;
5130	agp_bridge.resume = agp_generic_resume;
5131	agp_bridge.cant_use_aperture = 1;
5132
5133	return 0;
5134
5135	(void) pdev; /* unused */
5136	}
5137
5138	#endif /* CONFIG_AGP_UNINORTH */
5139
4738	/* per-chipset initialization data.	5140	/* per-chipset initialization data.
4739	* note -- all chipsets for a single vendor MUST be grouped together	5141	* note -- all chipsets for a single vendor MUST be grouped together
4740	*/	5142	*/
Lines 5167-5172 Link Here
5167	hp_zx1_setup },	5569	hp_zx1_setup },
5168	#endif	5570	#endif
5169		5571
		5572	#ifdef CONFIG_AGP_UNINORTH
		5573	{ PCI_DEVICE_ID_APPLE_UNI_N_AGP,
		5574	PCI_VENDOR_ID_APPLE,
		5575	APPLE_UNINORTH,
		5576	"Apple",
		5577	"UniNorth",
		5578	uninorth_setup },
		5579	{ PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
		5580	PCI_VENDOR_ID_APPLE,
		5581	APPLE_UNINORTH,
		5582	"Apple",
		5583	"UniNorth/Pangea",
		5584	uninorth_setup },
		5585	{ PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
		5586	PCI_VENDOR_ID_APPLE,
		5587	APPLE_UNINORTH,
		5588	"Apple",
		5589	"UniNorth 1.5",
		5590	uninorth_setup },
		5591	{ PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
		5592	PCI_VENDOR_ID_APPLE,
		5593	APPLE_UNINORTH,
		5594	"Apple",
		5595	"UniNorth 2",
		5596	uninorth_setup },
		5597	#endif /* CONFIG_AGP_UNINORTH */
		5598
5170	{ 0, }, /* dummy final entry, always present */	5599	{ 0, }, /* dummy final entry, always present */
5171	};	5600	};
5172		5601





/* Do not edit this file! It was automatically generated by   */
/*    loadkeys --mktable defkeymap.map > defkeymap.c          */


	0xf308,	0xf309,	0xf30b,	0xf304,	0xf305,	0xf306,	0xf30a,	0xf301,
	0xf302,	0xf303,	0xf300,	0xf310,	0xf206,	0xf200,	0xf03e,	0xf10a,
	0xf10b,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,
	0xf30e,	0xf702,	0xf30d,	0xf01c,	0xf701,	0xf205,	0xf114,	0xf603,
	0xf20b,	0xf601,	0xf602,	0xf117,	0xf600,	0xf20a,	0xf115,	0xf116,
	0xf11a,	0xf10c,	0xf10d,	0xf11b,	0xf11c,	0xf110,	0xf311,	0xf11d,
	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,

	0xf912,	0xf913,	0xf30b,	0xf90e,	0xf90f,	0xf910,	0xf30a,	0xf90b,
	0xf90c,	0xf90d,	0xf90a,	0xf310,	0xf206,	0xf200,	0xf07c,	0xf516,
	0xf517,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,
	0xf30e,	0xf702,	0xf30d,	0xf01c,	0xf701,	0xf205,	0xf114,	0xf603,
	0xf118,	0xf601,	0xf602,	0xf117,	0xf600,	0xf119,	0xf115,	0xf116,
	0xf11a,	0xf10c,	0xf10d,	0xf11b,	0xf11c,	0xf110,	0xf311,	0xf11d,
	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,

	0xf308,	0xf309,	0xf30b,	0xf304,	0xf305,	0xf306,	0xf30a,	0xf301,
	0xf302,	0xf303,	0xf300,	0xf310,	0xf206,	0xf200,	0xf200,	0xf200,
	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,
	0xf30e,	0xf702,	0xf30d,	0xf01c,	0xf701,	0xf205,	0xf114,	0xf603,
	0xf118,	0xf601,	0xf602,	0xf117,	0xf600,	0xf119,	0xf115,	0xf116,
	0xf11a,	0xf10c,	0xf10d,	0xf11b,	0xf11c,	0xf110,	0xf311,	0xf11d,
	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,

	0xf308,	0xf309,	0xf30b,	0xf304,	0xf305,	0xf306,	0xf30a,	0xf301,
	0xf302,	0xf303,	0xf300,	0xf20c,	0xf206,	0xf200,	0xf200,	0xf50a,
	0xf50b,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,
	0xf30e,	0xf702,	0xf30d,	0xf01c,	0xf701,	0xf205,	0xf114,	0xf603,
	0xf118,	0xf601,	0xf602,	0xf117,	0xf600,	0xf119,	0xf115,	0xf20c,
	0xf11a,	0xf10c,	0xf10d,	0xf11b,	0xf11c,	0xf110,	0xf311,	0xf11d,
	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,	0xf200,


unsigned int keymap_count = 7;


/*
 * Philosophy: most people do not define more strings, but they who do
 * often want quite a lot of string space. So, we statically allocate

	'\033', '[', 'P', 0, 
};


char *funcbufptr = func_buf;
int funcbufsize = sizeof(func_buf);
int funcbufleft = 0;          /* space left */

Lines 324-329 Link Here

(-)linux-2.4.22/drivers/char/drm/drmP.h (+12 lines)
324	DRM(ioremapfree)( (map)->handle, (map)->size ); \	324	DRM(ioremapfree)( (map)->handle, (map)->size ); \
325	} while (0)	325	} while (0)
326		326
		327	#define DRM_IOREMAPAGP(map, dev) \
		328	(map)->handle = DRM(ioremap_agp)( (map)->offset, (map)->size, (dev) )
		329
		330	#define DRM_IOREMAPAGPFREE(map) \
		331	do { \
		332	if ( (map)->handle && (map)->size ) \
		333	DRM(ioremap_agp_free)( (map)->handle, (map)->size ); \
		334	} while (0)
		335
327	#define DRM_FIND_MAP(_map, _o) \	336	#define DRM_FIND_MAP(_map, _o) \
328	do { \	337	do { \
329	struct list_head *_list; \	338	struct list_head *_list; \
Lines 758-763 Link Here
758	extern void *DRM(ioremap)(unsigned long offset, unsigned long size);	767	extern void *DRM(ioremap)(unsigned long offset, unsigned long size);
759	extern void DRM(ioremapfree)(void *pt, unsigned long size);	768	extern void DRM(ioremapfree)(void *pt, unsigned long size);
760		769
		770	extern void DRM(ioremap_agp)(unsigned long offset, unsigned long size, drm_device_t dev);
		771	extern void DRM(ioremap_agp_free)(void *pt, unsigned long size);
		772
761	#if __REALLY_HAVE_AGP	773	#if __REALLY_HAVE_AGP
762	extern agp_memory *DRM(alloc_agp)(int pages, u32 type);	774	extern agp_memory *DRM(alloc_agp)(int pages, u32 type);
763	extern int DRM(free_agp)(agp_memory *handle, int pages);	775	extern int DRM(free_agp)(agp_memory *handle, int pages);




	return pt;
}

/* PPC specific routine used by ioremap_agp, to be replaced by some
 * more generic implementation
 */
extern int map_page(unsigned long va, unsigned long pa, int flags);

void *DRM(ioremap_agp)(unsigned long offset, unsigned long size, drm_device_t *dev)
{
	void *pt;
	struct vm_struct *area;
	struct drm_agp_mem *agpmem;
	unsigned int flags = _PAGE_NO_CACHE|_PAGE_KERNEL|_PAGE_PRESENT|_PAGE_RW|_PAGE_DIRTY;
	int err, i;
		
	printk("drm: ioremap_agp, offset: 0x%08lx, size: 0x%08lx\n", offset, size);
	
#if __REALLY_HAVE_AGP
	if (!size) {
		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
			      "Mapping 0 bytes at 0x%08lx\n", offset);
		return NULL;
	}

	if (!dev->agp || !dev->agp->cant_use_aperture)
		return DRM(ioremap)(offset, size);

	/* XXX This has to be changed into something more generic
	 * this implementation is really only valid on PPC
	 */
	area = get_vm_area(size, VM_IOREMAP);
	if (area == 0) {
		spin_lock(&DRM(mem_lock));
		++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count;
		spin_unlock(&DRM(mem_lock));
		printk("->NULL\n");
		return NULL;
	}
	pt = (void *)VMALLOC_VMADDR(area->addr);
	err = 0;
	for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
		unsigned long baddr = offset + i;
		unsigned long index;
		
                /*
                 * It's AGP memory - find the real physical page to map
                 */
                for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) {
                        if (agpmem->bound <= baddr &&
                            agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) 
                                break;
		}
		if (!agpmem) {
			printk("drm: not matching AGP page in ioremap_agp\n");
			err = 1;
			break;
		}
		index = (baddr - agpmem->bound) >> PAGE_SHIFT;
		get_page(virt_to_page(__va(agpmem->memory->memory[index])));
		err = map_page(((unsigned long)pt)+i, agpmem->memory->memory[index], flags);
	}
	if (err) {
		vfree((void *)pt);
		spin_lock(&DRM(mem_lock));
		++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count;
		spin_unlock(&DRM(mem_lock));
		printk("->NULL\n");
		return NULL;
	}
		
	spin_lock(&DRM(mem_lock));
	++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
	DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size;
	spin_unlock(&DRM(mem_lock));
	printk("->pt=0x%p\n", pt);
	return pt;
#else
	return NULL;
#endif
}

void DRM(ioremap_agp_free)(void *pt, unsigned long size)
{
	int alloc_count;
	int free_count;

	if (!pt)
		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
			      "Attempt to free NULL pointer\n");
	else
		vfree(pt);

	spin_lock(&DRM(mem_lock));
	DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size;
	free_count  = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count;
	alloc_count =	DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
	spin_unlock(&DRM(mem_lock));
	if (free_count > alloc_count) {
		DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
			      "Excess frees: %d frees, %d allocs\n",
			      free_count, alloc_count);
	}
}

void DRM(ioremapfree)(void *pt, unsigned long size)
{
	int alloc_count;





	if ( !priv->authenticated ) return -EACCES;

	/* We check for "dma". On Apple's UniNorth, it's valid to have
	 * the AGP mapped at physical address 0
	 * --BenH.
	 */
	if (!VM_OFFSET(vma) && (!dev->agp ||
	    dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE))
		return DRM(mmap_dma)(filp, vma);

				/* A sequential search of a linked list is
				   fine here because: 1) there will only be


	switch (map->type) {
        case _DRM_AGP:
		if (!dev->agp)
			return -ENODEV;
		if (dev->agp->cant_use_aperture) {
	                /*
	                 * On Alpha we can't talk to bus dma address from the
	                 * CPU, so for memory of type DRM_AGP, we'll deal with
	                 * sorting out the real physical pages and mappings
	                 * in nopage()
	                 */
#if defined(__powerpc__)
			pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
#endif
			vma->vm_flags |= VM_IO;
	                vma->vm_ops = &DRM(vm_ops);
	                break;
	        }
                /* fall through to _DRM_FRAME_BUFFER... */        
	case _DRM_FRAME_BUFFER:
	case _DRM_REGISTERS:

Lines 37-42 Link Here

(-)linux-2.4.22/drivers/char/drm/r128_cce.c (-7 / +20 lines)
37		37
38	#define R128_FIFO_DEBUG 0	38	#define R128_FIFO_DEBUG 0
39		39
		40	#if __REALLY_HAVE_AGP && defined(CONFIG_ALL_PPC)
		41	extern unsigned long agp_special_page;
		42	#endif
		43
40		44
41	/* CCE microcode (from ATI) */	45	/* CCE microcode (from ATI) */
42	static u32 r128_cce_microcode[] = {	46	static u32 r128_cce_microcode[] = {
Lines 340-345 Link Here
340	SET_RING_HEAD( &dev_priv->ring, 0 );	344	SET_RING_HEAD( &dev_priv->ring, 0 );
341		345
342	if ( !dev_priv->is_pci ) {	346	if ( !dev_priv->is_pci ) {
		347	#if __REALLY_HAVE_AGP && defined(CONFIG_ALL_PPC)
		348	if (_machine == _MACH_Pmac) {
		349	dev_priv->ring.head = (__volatile__ u32 *) agp_special_page;
		350	SET_RING_HEAD( &dev_priv->ring, 0 );
		351	R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
		352	__pa( dev_priv->ring.head ) );
		353	} else
		354	#endif
343	R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,	355	R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
344	dev_priv->ring_rptr->offset );	356	dev_priv->ring_rptr->offset );
345	} else {	357	} else {
Lines 549-557 Link Here
549	init->sarea_priv_offset);	561	init->sarea_priv_offset);
550		562
551	if ( !dev_priv->is_pci ) {	563	if ( !dev_priv->is_pci ) {
552	DRM_IOREMAP( dev_priv->cce_ring );	564	DRM_IOREMAPAGP( dev_priv->cce_ring, dev );
553	DRM_IOREMAP( dev_priv->ring_rptr );	565	DRM_IOREMAPAGP( dev_priv->ring_rptr, dev );
554	DRM_IOREMAP( dev_priv->buffers );	566	DRM_IOREMAPAGP( dev_priv->buffers, dev );
555	if(!dev_priv->cce_ring->handle \|\|	567	if(!dev_priv->cce_ring->handle \|\|
556	!dev_priv->ring_rptr->handle \|\|	568	!dev_priv->ring_rptr->handle \|\|
557	!dev_priv->buffers->handle) {	569	!dev_priv->buffers->handle) {
Lines 623-632 Link Here
623	drm_r128_private_t *dev_priv = dev->dev_private;	635	drm_r128_private_t *dev_priv = dev->dev_private;
624		636
625	if ( !dev_priv->is_pci ) {	637	if ( !dev_priv->is_pci ) {
626	DRM_IOREMAPFREE( dev_priv->cce_ring );	638	DRM_IOREMAPAGPFREE( dev_priv->cce_ring );
627	DRM_IOREMAPFREE( dev_priv->ring_rptr );	639	DRM_IOREMAPAGPFREE( dev_priv->ring_rptr );
628	DRM_IOREMAPFREE( dev_priv->buffers );	640	DRM_IOREMAPAGPFREE( dev_priv->buffers );
629	} else {	641	}
		642	else {
630	if (!DRM(ati_pcigart_cleanup)( dev,	643	if (!DRM(ati_pcigart_cleanup)( dev,
631	dev_priv->phys_pci_gart,	644	dev_priv->phys_pci_gart,
632	dev_priv->bus_pci_gart ))	645	dev_priv->bus_pci_gart ))

Lines 34-41 Link Here

(-)linux-2.4.22/drivers/char/drm/r128_drv.h (-1 / +15 lines)
34	#ifndef __R128_DRV_H__	34	#ifndef __R128_DRV_H__
35	#define __R128_DRV_H__	35	#define __R128_DRV_H__
36		36
		37	#ifdef __powerpc__
		38	#define GET_RING_HEAD( ring ) in_le32((volatile u32 *)(ring)->head)
		39	#define SET_RING_HEAD( ring, val ) out_le32((volatile u32 *)(ring)->head, (val) )
		40	#else
37	#define GET_RING_HEAD( ring ) le32_to_cpu( *(ring)->head )	41	#define GET_RING_HEAD( ring ) le32_to_cpu( *(ring)->head )
38	#define SET_RING_HEAD( ring, val ) *(ring)->head = cpu_to_le32( val )	42	#define SET_RING_HEAD( ring, val ) *(ring)->head = cpu_to_le32( val )
		43	#endif
39		44
40	typedef struct drm_r128_freelist {	45	typedef struct drm_r128_freelist {
41	unsigned int age;	46	unsigned int age;
Lines 397-402 Link Here
397	wmb(); \	402	wmb(); \
398	R128_DEREF(reg) = val; \	403	R128_DEREF(reg) = val; \
399	} while (0)	404	} while (0)
		405	#elif defined (__powerpc__)
		406	#define R128_READ(reg) in_le32( (volatile u32 *)R128_ADDR( reg ) )
		407	#define R128_WRITE(reg,val) out_le32( (volatile u32 *)R128_ADDR( reg ), (val) )
400	#else	408	#else
401	#define R128_READ(reg) le32_to_cpu( R128_DEREF( reg ) )	409	#define R128_READ(reg) le32_to_cpu( R128_DEREF( reg ) )
402	#define R128_WRITE(reg,val) \	410	#define R128_WRITE(reg,val) \
Lines 418-423 Link Here
418	wmb(); \	426	wmb(); \
419	R128_DEREF8(reg) = val; \	427	R128_DEREF8(reg) = val; \
420	} while (0)	428	} while (0)
		429	#elif defined (__powerpc__)
		430	#define R128_READ8(reg) in_8( (volatile u8 *)R128_ADDR(reg) )
		431	#define R128_WRITE8(reg,val) out_8( (volatile u8 *)R128_ADDR(reg), val )
421	#else	432	#else
422	#define R128_READ8(reg) R128_DEREF8( reg )	433	#define R128_READ8(reg) R128_DEREF8( reg )
423	#define R128_WRITE8(reg,val) do { R128_DEREF8( reg ) = val; } while (0)	434	#define R128_WRITE8(reg,val) do { R128_DEREF8( reg ) = val; } while (0)
Lines 493-500 Link Here
493	* Ring control	504	* Ring control
494	*/	505	*/
495		506
		507	#ifdef __powerpc__
		508	#define r128_flush_write_combine() (void)in_le32(ring)
		509	#else
496	#define r128_flush_write_combine() mb()	510	#define r128_flush_write_combine() mb()
497		511	#endif
498		512
499	#define R128_VERBOSE 0	513	#define R128_VERBOSE 0
500		514

Lines 37-48 Link Here

(-)linux-2.4.22/drivers/char/drm/radeon_cp.c (-11 / +24 lines)
37		37
38	#define RADEON_FIFO_DEBUG 0	38	#define RADEON_FIFO_DEBUG 0
39		39
40	#if defined(__alpha__)	40	#if defined(__alpha__) \|\| defined(__powerpc__)
41	# define PCIGART_ENABLED	41	# define PCIGART_ENABLED
42	#else	42	#else
43	# undef PCIGART_ENABLED	43	# undef PCIGART_ENABLED
44	#endif	44	#endif
45		45
		46	#if __REALLY_HAVE_AGP && defined(CONFIG_ALL_PPC)
		47	extern unsigned long agp_special_page;
		48	#endif
46		49
47	/* CP microcode (from ATI) */	50	/* CP microcode (from ATI) */
48	static u32 radeon_cp_microcode[][2] = {	51	static u32 radeon_cp_microcode[][2] = {
Lines 313-319 Link Here
313	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);	316	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
314	}	317	}
315		318
316	#if RADEON_FIFO_DEBUG	319	#if 1 /* RADEON_FIFO_DEBUG */
317	static void radeon_status( drm_radeon_private_t *dev_priv )	320	static void radeon_status( drm_radeon_private_t *dev_priv )
318	{	321	{
319	printk( "%s:\n", __FUNCTION__ );	322	printk( "%s:\n", __FUNCTION__ );
Lines 400-406 Link Here
400	udelay( 1 );	403	udelay( 1 );
401	}	404	}
402		405
403	#if RADEON_FIFO_DEBUG	406	#if 1 /* RADEON_FIFO_DEBUG */
		407	printk("wait_for_idle timeout\n");
404	DRM_ERROR( "failed!\n" );	408	DRM_ERROR( "failed!\n" );
405	radeon_status( dev_priv );	409	radeon_status( dev_priv );
406	#endif	410	#endif
Lines 611-616 Link Here
611	dev_priv->ring.tail = cur_read_ptr;	615	dev_priv->ring.tail = cur_read_ptr;
612		616
613	if ( !dev_priv->is_pci ) {	617	if ( !dev_priv->is_pci ) {
		618	#if __REALLY_HAVE_AGP && defined(CONFIG_ALL_PPC)
		619	if (_machine == _MACH_Pmac) {
		620	dev_priv->ring.head = (__volatile__ u32 *) agp_special_page;
		621	*dev_priv->ring.head = cur_read_ptr;
		622	RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
		623	__pa( dev_priv->ring.head ) );
		624	} else
		625	#endif
614	RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,	626	RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
615	dev_priv->ring_rptr->offset );	627	dev_priv->ring_rptr->offset );
616	} else {	628	} else {
Lines 835-843 Link Here
835	init->sarea_priv_offset);	847	init->sarea_priv_offset);
836		848
837	if ( !dev_priv->is_pci ) {	849	if ( !dev_priv->is_pci ) {
838	DRM_IOREMAP( dev_priv->cp_ring );	850	DRM_IOREMAPAGP( dev_priv->cp_ring, dev );
839	DRM_IOREMAP( dev_priv->ring_rptr );	851	DRM_IOREMAPAGP( dev_priv->ring_rptr, dev );
840	DRM_IOREMAP( dev_priv->buffers );	852	DRM_IOREMAPAGP( dev_priv->buffers, dev );
841	if(!dev_priv->cp_ring->handle \|\|	853	if(!dev_priv->cp_ring->handle \|\|
842	!dev_priv->ring_rptr->handle \|\|	854	!dev_priv->ring_rptr->handle \|\|
843	!dev_priv->buffers->handle) {	855	!dev_priv->buffers->handle) {
Lines 982-990 Link Here
982	drm_radeon_private_t *dev_priv = dev->dev_private;	994	drm_radeon_private_t *dev_priv = dev->dev_private;
983		995
984	if ( !dev_priv->is_pci ) {	996	if ( !dev_priv->is_pci ) {
985	DRM_IOREMAPFREE( dev_priv->cp_ring );	997	DRM_IOREMAPAGPFREE( dev_priv->cp_ring );
986	DRM_IOREMAPFREE( dev_priv->ring_rptr );	998	DRM_IOREMAPAGPFREE( dev_priv->ring_rptr );
987	DRM_IOREMAPFREE( dev_priv->buffers );	999	DRM_IOREMAPAGPFREE( dev_priv->buffers );
988	} else {	1000	} else {
989	if (!DRM(ati_pcigart_cleanup)( dev,	1001	if (!DRM(ati_pcigart_cleanup)( dev,
990	dev_priv->phys_pci_gart,	1002	dev_priv->phys_pci_gart,
Lines 1351-1364 Link Here
1351	int i;	1363	int i;
1352		1364
1353	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	1365	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1354	radeon_update_ring_snapshot( ring );	1366	radeon_update_ring_snapshot( dev_priv, ring );
1355	if ( ring->space > n )	1367	if ( ring->space > n )
1356	return 0;	1368	return 0;
1357	udelay( 1 );	1369	udelay( 1 );
1358	}	1370	}
1359		1371
1360	/* FIXME: This return value is ignored in the BEGIN_RING macro! */	1372	/* FIXME: This return value is ignored in the BEGIN_RING macro! */
1361	#if RADEON_FIFO_DEBUG	1373	#if 1 /* RADEON_FIFO_DEBUG */
		1374	printk("wait ring timeout\n");
1362	radeon_status( dev_priv );	1375	radeon_status( dev_priv );
1363	DRM_ERROR( "failed!\n" );	1376	DRM_ERROR( "failed!\n" );
1364	#endif	1377	#endif




#ifndef __RADEON_DRV_H__
#define __RADEON_DRV_H__

#if defined(__powerpc__)
#define GET_RING_HEAD(ring)		in_le32((volatile u32 *)(ring)->head)
#define SET_RING_HEAD(ring,val)		out_le32((volatile u32 *)(ring)->head, (val))
#else
#define GET_RING_HEAD(ring)		le32_to_cpu(*(ring)->head)
#define SET_RING_HEAD(ring,val)		*(ring)->head = cpu_to_le32(val)
#endif

typedef struct drm_radeon_freelist {
   	unsigned int age;
   	drm_buf_t *buf;

extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );

static inline void
radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv, drm_radeon_ring_buffer_t *ring );
{
	ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);
	if ( ring->space <= 0 )
		ring->space += ring->size;
}

extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
extern int radeon_do_cleanup_cp( drm_device_t *dev );

	wmb();								\
	RADEON_DEREF(reg) = val;					\
} while (0)
#elif defined(__powerpc__)
#define RADEON_READ(reg)	in_le32((volatile u32 *)RADEON_ADDR(reg))
#define RADEON_WRITE(reg,val)	out_le32((volatile u32 *)RADEON_ADDR(reg), (val))
#else
#define RADEON_READ(reg)	RADEON_DEREF( reg )
#define RADEON_WRITE(reg, val)	do { RADEON_DEREF( reg ) = val; } while (0)

	wmb();								\
	RADEON_DEREF8( reg ) = val;					\
} while (0)
#elif defined(__powerpc__)
#define RADEON_READ8(reg)	in_8((volatile u8 *)RADEON_ADDR(reg))
#define RADEON_WRITE8(reg,val)	out_8((volatile u8 *)RADEON_ADDR(reg), (val))
#else
#define RADEON_READ8(reg)	RADEON_DEREF8( reg )
#define RADEON_WRITE8(reg, val)	do { RADEON_DEREF8( reg ) = val; } while (0)

	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i;	\
	if ( ring->space < ring->high_mark ) {				\
		for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	\
			radeon_update_ring_snapshot( dev_priv, ring );		\
			if ( ring->space >= ring->high_mark )		\
				goto __ring_space_done;			\
			udelay( 1 );					\

 * Ring control
 */

#if defined(__powerpc__)
#define radeon_flush_write_combine()	do { mb(); (void)in_le32(ring); mb(); } while(0)
#else
#define radeon_flush_write_combine()	mb()
#endif

#define RADEON_VERBOSE	0
#define RADEON_DEBUG

#ifdef RADEON_DEBUG
#define RING_LOCALS	int write; unsigned int mask; volatile u32 *ring; int dbg;
#define DEBUG_INIT(n)	dbg = n
#define DEBUG_INC()	do { if (dbg <= 0) printk("Argh 1 ! (%s:%d)\n", __FILE__, __LINE__); \
			     dbg--; } while(0)
#define DEBUG_END()	do { if (dbg != 0) printk("Argh 2/%d ! (%s:%d)\n", dbg, __FILE__, __LINE__); \
			     dbg--; } while(0)
#else
#define RING_LOCALS	int write; unsigned int mask; volatile u32 *ring;
#define DEBUG_INIT()
#define DEBUG_INC()
#define DEBUG_END()
#endif

#define BEGIN_RING( n ) do {						\
	if ( RADEON_VERBOSE ) {						\

	ring = dev_priv->ring.start;					\
	write = dev_priv->ring.tail;					\
	mask = dev_priv->ring.tail_mask;				\
	DEBUG_INIT(n);							\
} while (0)

#define ADVANCE_RING() do {						\

		DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",	\
			  write, dev_priv->ring.tail );			\
	}								\
	DEBUG_END();							\
	radeon_flush_write_combine();					\
	dev_priv->ring.tail = write;					\
	RADEON_WRITE( RADEON_CP_RB_WPTR, write );			\

		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
			   (unsigned int)(x), write );			\
	}								\
	DEBUG_INC();							\
	ring[write++] = cpu_to_le32(x);					\
	write &= mask;							\
} while (0)

#define RADEON_PERFORMANCE_BOXES	0

static inline void
radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv, drm_radeon_ring_buffer_t *ring )
{
//	ring->space = (GET_RING_HEAD(ring) - ring->tail) * sizeof(u32);
	ring->space = (RADEON_READ(0x710) - ring->tail) * sizeof(u32);
	if ( ring->space <= 0 )
		ring->space += ring->size;
}

#endif /* __RADEON_DRV_H__ */




			u32 *data = (u32 *)
				((char *)dev_priv->buffers->handle
				 + buf->offset + start);
			data[dwords++] = cpu_to_le32(RADEON_CP_PACKET2);
		}

		buf_priv->dispatched = 1;

		data = (u32 *)((char *)dev_priv->buffers->handle
			       + buf->offset + start);

		data[0] = cpu_to_le32(CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ));

		data[1] = cpu_to_le32(offset);
		data[2] = cpu_to_le32(RADEON_MAX_VB_VERTS);
		data[3] = cpu_to_le32(format);
		data[4] = cpu_to_le32((prim | RADEON_PRIM_WALK_IND |
			   RADEON_COLOR_ORDER_RGBA |
			   RADEON_VTX_FMT_RADEON_MODE |
			   (count << RADEON_NUM_VERTICES_SHIFT) ));

		if ( count & 0x1 ) {
#ifdef __LITTLE_ENDIAN
			data[dwords-1] &= 0x0000ffff;
#else
			data[dwords-1] &= 0xffff0000;
#endif
		}

		do {

	 */
	buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);

	buffer[0] = cpu_to_le32(CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ));
	buffer[1] = cpu_to_le32((RADEON_GMC_DST_PITCH_OFFSET_CNTL |
		     RADEON_GMC_BRUSH_NONE |
		     (format << 8) |
		     RADEON_GMC_SRC_DATATYPE_COLOR |
		     RADEON_ROP3_S |
		     RADEON_DP_SRC_SOURCE_HOST_DATA |
		     RADEON_GMC_CLR_CMP_CNTL_DIS |
		     RADEON_GMC_WR_MSK_DIS));

	buffer[2] = cpu_to_le32((tex->pitch << 22) | (tex->offset >> 10));
	buffer[3] = cpu_to_le32(0xffffffff);
	buffer[4] = cpu_to_le32(0xffffffff);
	buffer[5] = cpu_to_le32((y << 16) | image->x);
	buffer[6] = cpu_to_le32((height << 16) | image->width);
	buffer[7] = cpu_to_le32(dwords);

	buffer += 8;


Lines 256-261 Link Here

(-)linux-2.4.22/drivers/i2c/i2c-keywest.c (+2 lines)
256	len = 1;	256	len = 1;
257	buffer = &data->byte;	257	buffer = &data->byte;
258	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;	258	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;
		259	//iface->cur_mode \|= KW_I2C_MODE_COMBINED;
259	break;	260	break;
260	case I2C_SMBUS_WORD_DATA:	261	case I2C_SMBUS_WORD_DATA:
261	len = 2;	262	len = 2;
Lines 267-272 Link Here
267	len = data->block[0];	268	len = data->block[0];
268	buffer = &data->block[1];	269	buffer = &data->block[1];
269	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;	270	iface->cur_mode \|= KW_I2C_MODE_STANDARDSUB;
		271	//iface->cur_mode \|= KW_I2C_MODE_COMBINED;
270	break;	272	break;
271	default:	273	default:
272	return -1;	274	return -1;

Lines 86-91 Link Here

(-)linux-2.4.22/drivers/ide/Config.in (+3 lines)
86	dep_bool ' Probe internal Kauai ATA/100 first' CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST $CONFIG_BLK_DEV_IDE_PMAC	86	dep_bool ' Probe internal Kauai ATA/100 first' CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST $CONFIG_BLK_DEV_IDE_PMAC
87	dep_bool ' PowerMac IDE DMA support' CONFIG_BLK_DEV_IDEDMA_PMAC $CONFIG_BLK_DEV_IDE_PMAC	87	dep_bool ' PowerMac IDE DMA support' CONFIG_BLK_DEV_IDEDMA_PMAC $CONFIG_BLK_DEV_IDE_PMAC
88	dep_bool ' Use DMA by default' CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO $CONFIG_BLK_DEV_IDEDMA_PMAC	88	dep_bool ' Use DMA by default' CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO $CONFIG_BLK_DEV_IDEDMA_PMAC
		89	if [ "$CONFIG_ADB_PMU" = "y" ]; then
		90	bool ' Blink laptop LED on activity' CONFIG_PMU_HD_BLINK
		91	fi
89	if [ "$CONFIG_BLK_DEV_IDE_PMAC" = "y" ]; then	92	if [ "$CONFIG_BLK_DEV_IDE_PMAC" = "y" ]; then
90	define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PMAC	93	define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PMAC
91	fi	94	fi

Lines 40-45 Link Here

(-)linux-2.4.22/drivers/ide/arm/rapide.c (+1 lines)
40	}	40	}
41	hw.io_ports[IDE_CONTROL_OFFSET] = port + 0x206;	41	hw.io_ports[IDE_CONTROL_OFFSET] = port + 0x206;
42	hw.irq = ec->irq;	42	hw.irq = ec->irq;
		43	hw.chipset = ide_generic;
43		44
44	return ide_register_hw(&hw, NULL);	45	return ide_register_hw(&hw, NULL);
45	}	46	}

Lines 1161-1173 Link Here

(-)linux-2.4.22/drivers/ide/ide-disk.c (-8 / +19 lines)
1161	{	1161	{
1162	struct hd_driveid *id = drive->id;	1162	struct hd_driveid *id = drive->id;
1163	unsigned long capacity = drive->cyl * drive->head * drive->sect;	1163	unsigned long capacity = drive->cyl * drive->head * drive->sect;
1164	unsigned long set_max = idedisk_read_native_max_address(drive);	1164	unsigned long set_max = 0;
1165	unsigned long long capacity_2 = capacity;	1165	unsigned long long capacity_2 = capacity;
1166	unsigned long long set_max_ext;	1166	unsigned long long set_max_ext;
1167		1167
1168	drive->capacity48 = 0;	1168	drive->capacity48 = 0;
1169	drive->select.b.lba = 0;	1169	drive->select.b.lba = 0;
1170		1170
		1171	/* That stupid compact flash doesn't like the command */
		1172	if (!drive->is_flash)
		1173	set_max = idedisk_read_native_max_address(drive);
		1174
1171	(void) idedisk_supports_host_protected_area(drive);	1175	(void) idedisk_supports_host_protected_area(drive);
1172		1176
1173	if (id->cfs_enable_2 & 0x0400) {	1177	if (id->cfs_enable_2 & 0x0400) {
Lines 1566-1572 Link Here
1566		1570
1567	static int set_lba_addressing (ide_drive_t *drive, int arg)	1571	static int set_lba_addressing (ide_drive_t *drive, int arg)
1568	{	1572	{
1569	return (probe_lba_addressing(drive, arg));	1573	return probe_lba_addressing(drive, arg);
1570	}	1574	}
1571		1575
1572	static void idedisk_add_settings(ide_drive_t *drive)	1576	static void idedisk_add_settings(ide_drive_t *drive)
Lines 1644-1656 Link Here
1644	break;	1648	break;
1645	}	1649	}
1646		1650
1647	#if 1
1648	(void) probe_lba_addressing(drive, 1);	1651	(void) probe_lba_addressing(drive, 1);
1649	#else	1652
1650	/* if using 48-bit addressing bump the request size up */	1653	if (drive->addressing == 1) {
1651	if (probe_lba_addressing(drive, 1))	1654	int max_s = 2048, i, off = drive->select.b.unit << PARTN_BITS;
1652	blk_queue_max_sectors(&drive->queue, 2048);	1655	ide_hwif_t *hwif = HWIF(drive);
1653	#endif	1656
		1657	if (max_s > hwif->rqsize)
		1658	max_s = hwif->rqsize;
		1659
		1660	for (i = 0; i < (1 << PARTN_BITS); i++)
		1661	max_sectors[hwif->major][off + i] = max_s;
		1662
		1663	printk("%s: max request size: %dKiB\n", drive->name, max_s / 2);
		1664	}
1654		1665
1655	/* Extract geometry if we did not already have one for the drive */	1666	/* Extract geometry if we did not already have one for the drive */
1656	if (!drive->cyl \|\| !drive->head \|\| !drive->sect) {	1667	if (!drive->cyl \|\| !drive->head \|\| !drive->sect) {

Lines 972-977 Link Here

(-)linux-2.4.22/drivers/ide/ide-probe.c (-4 / +15 lines)
972	q->queuedata = HWGROUP(drive);	972	q->queuedata = HWGROUP(drive);
973	blk_init_queue(q, do_ide_request);	973	blk_init_queue(q, do_ide_request);
974	blk_queue_throttle_sectors(q, 1);	974	blk_queue_throttle_sectors(q, 1);
		975	/*
		976	* enable led activity for disk drives only
		977	*/
		978	if (drive->media == ide_disk && HWIF(drive)->led_act)
		979	blk_queue_activity_fn(&drive->queue, HWIF(drive)->led_act, drive);
975	}	980	}
976		981
977	#undef __IRQ_HELL_SPIN	982	#undef __IRQ_HELL_SPIN
Lines 1164-1169 Link Here
1164		1169
1165	units = MAX_DRIVES;	1170	units = MAX_DRIVES;
1166		1171
		1172	if (!hwif->rqsize)
		1173	hwif->rqsize = hwif->addressing ? 128 : 65536;
		1174
1167	minors = units * (1<<PARTN_BITS);	1175	minors = units * (1<<PARTN_BITS);
1168	gd = kmalloc(sizeof(struct gendisk), GFP_KERNEL);	1176	gd = kmalloc(sizeof(struct gendisk), GFP_KERNEL);
1169	if (!gd)	1177	if (!gd)
Lines 1193-1203 Link Here
1193	max_sectors[hwif->major] = max_sect;	1201	max_sectors[hwif->major] = max_sect;
1194	max_readahead[hwif->major] = max_ra;	1202	max_readahead[hwif->major] = max_ra;
1195	for (unit = 0; unit < minors; ++unit) {	1203	for (unit = 0; unit < minors; ++unit) {
		1204	int max_s = 128;
		1205
1196	*bs++ = BLOCK_SIZE;	1206	*bs++ = BLOCK_SIZE;
1197	/*	1207
1198	* IDE can do up to 128K per request == 256	1208	if (max_s > hwif->rqsize)
1199	*/	1209	max_s = hwif->rqsize;
1200	*max_sect++ = ((hwif->rqsize) ? hwif->rqsize : 128);	1210
		1211	*max_sect++ = max_s;
1201	*max_ra++ = vm_max_readahead;	1212	*max_ra++ = vm_max_readahead;
1202	}	1213	}
1203		1214




#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/irq.h>
#ifdef CONFIG_PMAC_PBOOK
#include <linux/adb.h>
#include <linux/pmu.h>
#endif
#include "ide_modes.h"
#include "ide-timing.h"


};
#endif /* CONFIG_PMAC_PBOOK */

#ifdef CONFIG_PMU_HD_BLINK

/* Set to 50ms */
#define PMU_HD_BLINK_TIME	(HZ/20)

static struct adb_request pmu_blink_on, pmu_blink_off;
static spinlock_t pmu_blink_lock;
static unsigned long pmu_blink_stoptime;
static int pmu_blink_ledstate;
static struct timer_list pmu_blink_timer;

static void
pmu_hd_blink_timeout(unsigned long data)
{
	unsigned long flags;
	
	spin_lock_irqsave(&pmu_blink_lock, flags);

	/* We may have been triggered again in a racy way, check
	 * that we really want to switch it off
	 */
	if (time_after(pmu_blink_stoptime, jiffies))
		goto done;

	/* Previous req. not complete, try 50ms more */
	if (pmu_blink_off.complete == 0)
		mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
	else if (pmu_blink_ledstate) {
		pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
		pmu_blink_ledstate = 0;
	}
done:
	spin_unlock_irqrestore(&pmu_blink_lock, flags);
}

static void
pmu_hd_kick_blink(void *data, int rw)
{
	unsigned long flags;
	
	pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
	wmb();
	mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
	if (pmu_blink_ledstate == 1)
		return;
	spin_lock_irqsave(&pmu_blink_lock, flags);
	if (pmu_blink_on.complete && !pmu_blink_ledstate) {
		pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
		pmu_blink_ledstate = 1;
	}
	spin_unlock_irqrestore(&pmu_blink_lock, flags);
}

static int
pmu_hd_blink_init(void)
{
	struct device_node *dt;
	const char *model;

	if (pmu_get_model() != PMU_KEYLARGO_BASED)
		return 0;
	
	dt = find_devices("device-tree");
	if (dt == NULL)
		return 0;
	model = (const char *)get_property(dt, "model", NULL);
	if (model == NULL)
		return 0;
	if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
	    strncmp(model, "iBook", strlen("iBook")) != 0)
	    	return 0;
	
	pmu_blink_on.complete = 1;
	pmu_blink_off.complete = 1;
	spin_lock_init(&pmu_blink_lock);
	init_timer(&pmu_blink_timer);
	pmu_blink_timer.function = pmu_hd_blink_timeout;

	return 1;
}

#endif /* CONFIG_PMU_HD_BLINK */

/*
 * N.B. this can't be an initfunc, because the media-bay task can
 * call ide_[un]register at any time.

	ide_hwif_t *hwif = HWIF(drive);
	int result = 1;
	
	disable_irq_nosync(hwif->irq);
	udelay(1);
	SELECT_DRIVE(drive);
	SELECT_MASK(drive, 0);

	unsigned long base, regbase;
	int irq;
	ide_hwif_t *hwif;
#ifdef CONFIG_PMU_HD_BLINK
	int has_blink;
#endif	
	if (_machine != _MACH_Pmac)
		return;

	pp = &atas;
	rp = &removables;
	p = find_devices("ATA");

		p = find_type_devices("ide");
	if (p == NULL)
		p = find_type_devices("ata");

	if (p == NULL)
		return;

#ifdef CONFIG_PMU_HD_BLINK
	has_blink = pmu_hd_blink_init();
#endif /* CONFIG_PMU_HD_BLINK */

	/* Move removable devices such as the media-bay CDROM
	   on the PB3400 to the end of the list. */
	for (; p != NULL; p = nextp) {

			hwif->selectproc = pmac_ide_selectproc;
		hwif->speedproc = pmac_ide_tune_chipset;

#ifdef CONFIG_PMU_HD_BLINK
		if (has_blink)
			hwif->led_act = pmu_hd_kick_blink;
#endif /* CONFIG_PMU_HD_BLINK */

		printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s\n",
			i, model_name[pmif->kind], pmif->aapl_bus_id,
			in_bay ? " (mediabay)" : "");

#ifdef CONFIG_PMAC_PBOOK
	pmu_register_sleep_notifier(&idepmac_sleep_notifier);
#endif /* CONFIG_PMAC_PBOOK */

	mdelay(IDE_WAKEUP_DELAY_MS);
}

#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC




{
	int h;
	ide_hwif_t *hwif;
	int reserved = ide_reserved_hwifs();
	
	/*
	 * Look for a hwif with matching io_base specified using
	 * parameters to ide_setup().

	 */
	if (bootable) {
		for (h = 0; h < MAX_HWIFS; ++h) {
			hwif = ide_hwifs + h;
			if (hwif->chipset == ide_unknown)
				return hwif;	/* pick an unused entry */
		}
	} else {
		for (h = reserved; h < MAX_HWIFS; ++h) {
			hwif = ide_hwifs + h;
			if (hwif->chipset == ide_unknown)
				return hwif;	/* pick an unused entry */
		}
	}
	for (h = 0; h < reserved; ++h) {
		hwif = ide_hwifs + h;
		if (hwif->chipset == ide_unknown)
			return hwif;	/* pick an unused entry */

Lines 35-40 Link Here

(-)linux-2.4.22/drivers/macintosh/Makefile (+2 lines)
35	obj-$(CONFIG_INPUT_ADBHID) += adbhid.o	35	obj-$(CONFIG_INPUT_ADBHID) += adbhid.o
36	obj-$(CONFIG_PPC_RTC) += rtc.o	36	obj-$(CONFIG_PPC_RTC) += rtc.o
37	obj-$(CONFIG_ANSLCD) += ans-lcd.o	37	obj-$(CONFIG_ANSLCD) += ans-lcd.o
		38	#obj-$(CONFIG_I2C) += therm_pismo.o
		39	#obj-$(CONFIG_I2C) += therm_albooks.o
38		40
39	obj-$(CONFIG_ADB_PMU) += via-pmu.o	41	obj-$(CONFIG_ADB_PMU) += via-pmu.o
40	obj-$(CONFIG_ADB_CUDA) += via-cuda.o	42	obj-$(CONFIG_ADB_CUDA) += via-cuda.o

Lines 59-65 Link Here

(-)linux-2.4.22/drivers/macintosh/macserial.c (-11 / +10 lines)
59	};	59	};
60	#endif	60	#endif
61		61
62	#define SUPPORT_SERIAL_DMA	62	#undef SUPPORT_SERIAL_DMA
63	#define MACSERIAL_VERSION "2.0"	63	#define MACSERIAL_VERSION "2.0"
64		64
65	/*	65	/*
Lines 1134-1139 Link Here
1134	*/	1134	*/
1135	static void shutdown(struct mac_serial * info)	1135	static void shutdown(struct mac_serial * info)
1136	{	1136	{
		1137	unsigned long flags;
		1138
1137	OPNDBG("Shutting down serial port %d (irq %d)....\n", info->line,	1139	OPNDBG("Shutting down serial port %d (irq %d)....\n", info->line,
1138	info->irq);	1140	info->irq);
1139		1141
Lines 1142-1147 Link Here
1142	return;	1144	return;
1143	}	1145	}
1144		1146
		1147	save_flags(flags); cli(); /* Disable interrupts */
		1148
1145	if (info->has_dma) {	1149	if (info->has_dma) {
1146	del_timer(&info->poll_dma_timer);	1150	del_timer(&info->poll_dma_timer);
1147	dbdma_reset(info->tx_dma);	1151	dbdma_reset(info->tx_dma);
Lines 1151-1156 Link Here
1151	}	1155	}
1152	disable_irq(info->irq);	1156	disable_irq(info->irq);
1153		1157
		1158	restore_flags(flags);
		1159
1154	info->pendregs[1] = info->curregs[1] = 0;	1160	info->pendregs[1] = info->curregs[1] = 0;
1155	write_zsreg(info->zs_channel, 1, 0); /* no interrupts */	1161	write_zsreg(info->zs_channel, 1, 0); /* no interrupts */
1156		1162
Lines 1980-1985 Link Here
1980	return;	1986	return;
1981	}	1987	}
1982	info->flags \|= ZILOG_CLOSING;	1988	info->flags \|= ZILOG_CLOSING;
		1989	restore_flags(flags);
1983	/*	1990	/*
1984	* Save the termios structure, since this port may have	1991	* Save the termios structure, since this port may have
1985	* separate termios for callout and dialin.	1992	* separate termios for callout and dialin.
Lines 1994-2004 Link Here
1994	*/	2001	*/
1995	OPNDBG("waiting end of Tx... (timeout:%d)\n", info->closing_wait);	2002	OPNDBG("waiting end of Tx... (timeout:%d)\n", info->closing_wait);
1996	tty->closing = 1;	2003	tty->closing = 1;
1997	if (info->closing_wait != ZILOG_CLOSING_WAIT_NONE) {	2004	if (info->closing_wait != ZILOG_CLOSING_WAIT_NONE)
1998	restore_flags(flags);
1999	tty_wait_until_sent(tty, info->closing_wait);	2005	tty_wait_until_sent(tty, info->closing_wait);
2000	save_flags(flags); cli();
2001	}
2002		2006
2003	/*	2007	/*
2004	* At this point we stop accepting input. To do this, we	2008	* At this point we stop accepting input. To do this, we
Lines 2017-2031 Link Here
2017	* has completely drained.	2021	* has completely drained.
2018	*/	2022	*/
2019	OPNDBG("waiting end of Rx...\n");	2023	OPNDBG("waiting end of Rx...\n");
2020	restore_flags(flags);
2021	rs_wait_until_sent(tty, info->timeout);	2024	rs_wait_until_sent(tty, info->timeout);
2022	save_flags(flags); cli();
2023	}	2025	}
2024		2026
2025	shutdown(info);	2027	shutdown(info);
2026	/* restore flags now since shutdown() will have disabled this port's
2027	specific irqs */
2028	restore_flags(flags);
2029		2028
2030	if (tty->driver.flush_buffer)	2029	if (tty->driver.flush_buffer)
2031	tty->driver.flush_buffer(tty);	2030	tty->driver.flush_buffer(tty);
Lines 2880-2886 Link Here
2880	static int __init serial_console_setup(struct console co, char options)	2879	static int __init serial_console_setup(struct console co, char options)
2881	{	2880	{
2882	struct mac_serial *info;	2881	struct mac_serial *info;
2883	int baud = 38400;	2882	int baud = 57600; /38400;/
2884	int bits = 8;	2883	int bits = 8;
2885	int parity = 'n';	2884	int parity = 'n';
2886	int cflag = CREAD \| HUPCL \| CLOCAL;	2885	int cflag = CREAD \| HUPCL \| CLOCAL;




/*
 * Device driver for the i2c thermostat found on some laptops
 *
 * Copyright (C) 2001 Benjamin Herrenschmidt
 * 
 * Actually, there are 2 DS1775R1 on uninorth I2C busses
 */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/sections.h>

#define DEBUG

#define I2C_THERMOSTAT_ADDR	0x49
#define I2C_THERMOSTAT_ADDR2	0x48
#define MAX_THERMOSTATS		4


MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
MODULE_DESCRIPTION("Driver for DS1775 thermostat on Apple laptops");
MODULE_LICENSE("GPL");
EXPORT_NO_SYMBOLS;

struct temp_range
{
	u8	high;	/* Start the fan */
	u8	low;	/* Stop the fan */
};

struct apple_thermal_info {
	u8			id;			/* Implementation ID */
	u8			fan_count;		/* Number of fans */
	u8			thermostat_count;	/* Number of thermostats */
	u8			unused[5];
	struct temp_range	ranges[4];		/* Temperature ranges (may be [])*/
};

struct thermostat {
	struct i2c_client	clt;
	int			th_num;
	// more to come ?
};

static struct apple_thermal_info *thinfo;
static struct thermostat* thermostats[MAX_THERMOSTATS];
static int therm_count;

static int	attach_thermostat(struct i2c_adapter *adapter);
static int	detach_thermostat(struct i2c_client *client);

/* What is this supposed to be ? registered ? I hate
 * magic numbers like that ...
 */
#define I2C_DRIVERID_THERMOSTAT (0xDEAD)

static struct i2c_driver thermostat_driver = {  
	name:		"Apple Thermostat",
	id:		I2C_DRIVERID_THERMOSTAT,
	flags:		I2C_DF_NOTIFY,
	attach_adapter:	&attach_thermostat,
	detach_client:	&detach_thermostat,
	command:	NULL,
	inc_use:	NULL,
	dec_use:	NULL 
};

static int
write_reg(struct thermostat* th, int reg, u8* data, int len)
{
	u8 tmp[5];
	int rc;
	
	if (len > 4)
		return -EINVAL;
	tmp[0] = reg;
	memcpy(&tmp[1], data, len);
	rc = i2c_master_send(&th->clt, (const char *)tmp, len+1);
	if (rc < 0)
		return rc;
	if (rc != (len+1))
		return -ENODEV;
	return 0;
}

static int
read_reg(struct thermostat* th, int reg, u8* data, int len)
{
	u8 reg_addr;
	int rc;

	reg_addr = (u8)reg;
	rc = i2c_master_send(&th->clt, &reg_addr, 1);
	if (rc < 0)
		return rc;
	if (rc != 1)
		return -ENODEV;
	rc = i2c_master_recv(&th->clt, (char *)data, len);
	if (rc < 0)
		return rc;
	if (rc != len)
		return -ENODEV;
	return 0;
}

static int
attach_one_thermostat(struct i2c_adapter *adapter, int addr, int num)
{
	struct thermostat* th;
	int rc;
	u16 t, tlo, thi;
	u8 config;
	
	if (therm_count >= MAX_THERMOSTATS) {
		printk(KERN_WARNING "Skipped thermostat %d (%s:%x), max count reached !\n",
			num, adapter->name, addr);
		return -ENODEV;
	}
	
	th = (struct thermostat *)kmalloc(sizeof(struct thermostat), GFP_KERNEL);
	if (!th)
		return -ENOMEM;
	th->clt.addr = addr;
	th->clt.adapter = adapter;
	th->clt.driver = &thermostat_driver;
	th->clt.flags = 0;
	th->clt.data = (void *)therm_count;
	th->th_num = num;
	strcpy(th->clt.name, "thermostat");

	rc = read_reg(th, 1, &config, 1);
	if (rc < 0) {
		printk(KERN_ERR "Thermostat %d (%s:%x) failed to read config !\n",
			num, adapter->name, addr);
		kfree(th);
		return -ENODEV;
	}
	printk(KERN_INFO "Thermostat %d (%s:%x), config: %02x\n",
		num, adapter->name, addr, config);

	rc = read_reg(th, 0, (u8 *)&t, 2);
	if (rc < 0) {
		printk(KERN_ERR "Thermostat %d (%s:%x) failed to read temp !\n",
			num, adapter->name, addr);
		kfree(th);
		return -ENODEV;
	}
	printk(KERN_INFO "Thermostat %d (%s:%x), temp: %04x (about: %d degree C)\n",
		num, adapter->name, addr, t, t>>8);

	thermostats[therm_count++] = th;

	if (i2c_attach_client(&th->clt)) {
		printk(KERN_ERR "Thermostat %d (%s:%x), failed to attach client !\n",
			num, adapter->name, addr);
		thermostats[--therm_count] = NULL;
		kfree(th);
		return -ENODEV;
	}

	tlo = thi = 0;
	rc = read_reg(th, 2, (u8 *)&tlo, 2);
	if (rc < 0) {
		printk(KERN_WARNING "Thermostat %d (%s:%x) failed to read low threshold !\n",
			num, adapter->name, addr);
	}
	rc = read_reg(th, 3, (u8 *)&thi, 2);
	if (rc < 0) {
		printk(KERN_WARNING "Thermostat %d (%s:%x) failed to read high threshold !\n",
			num, adapter->name, addr);
	}
	printk(KERN_INFO "Thermostat %d (%s:%x), tl: %04x (%d degree C), th: %04x (%d degree C)\n",
		num, adapter->name, addr, tlo, tlo>>8, thi, thi>>8);
	return 0;
}

static int
attach_thermostat(struct i2c_adapter *adapter)
{
	unsigned long bus_no;
	int rc;

	if (strncmp(adapter->name, "uni-n", 5))
		return 0;
	bus_no = simple_strtoul(adapter->name + 6, NULL, 10);	
	rc = attach_one_thermostat(adapter, I2C_THERMOSTAT_ADDR, bus_no);
	if (!rc && thinfo->thermostat_count > 2)
		attach_one_thermostat(adapter, I2C_THERMOSTAT_ADDR2, bus_no+2);

	return rc;
}

static int
detach_thermostat(struct i2c_client *client)
{
	int index = (int)client->data;
	struct thermostat* th;

	if (index >= MAX_THERMOSTATS || !thermostats[index]) {
		printk(KERN_ERR "Invalid client in deatch_thermostat()\n");
		return -ENODEV;
	}
	th = thermostats[index];
	i2c_detach_client(&th->clt);
	thermostats[index] = NULL;
	
	kfree(th);

	return 0;
}

static int __init
thermostat_init(void)
{
	struct device_node* np;

	if (!machine_is_compatible("PowerBook3,1"))
		return -ENODEV;

	np = find_devices("power-mgt");
	if (!np)
		return -ENODEV;
	thinfo = (struct apple_thermal_info *)get_property(np, "thermal-info", NULL);
	if (!thinfo)
		return -ENODEV;
		
#ifdef DEBUG
	printk(KERN_DEBUG " Thermal Infos found :\n");
	printk(KERN_DEBUG "   implementation id : %d\n", thinfo->id);
	printk(KERN_DEBUG "   fan_count         : %d\n", thinfo->fan_count);
	printk(KERN_DEBUG "   thermostat_count  : %d\n", thinfo->thermostat_count);
	printk(KERN_DEBUG "   ranges[0]         : %d,%d\n",
		thinfo->ranges[0].high, thinfo->ranges[0].low);
	printk(KERN_DEBUG "   ranges[1]         : %d,%d\n",
		thinfo->ranges[1].high, thinfo->ranges[1].low);
	printk(KERN_DEBUG "   ranges[2]         : %d,%d\n",
		thinfo->ranges[2].high, thinfo->ranges[2].low);
	printk(KERN_DEBUG "   ranges[3]         : %d,%d\n",
		thinfo->ranges[3].high, thinfo->ranges[3].low);
#endif
	/* Check against titaniums & ibooks.... */
	if (thinfo->id != 1 && thinfo->id != 2) {
		printk(KERN_ERR "thermostat: design id %d unknown !\n", thinfo->id);
		return -ENODEV;
	}
	
	return i2c_add_driver(&thermostat_driver);
}

static void __exit
thermostat_exit(void)
{
	i2c_del_driver(&thermostat_driver);
}

module_init(thermostat_init);
module_exit(thermostat_exit);

Lines 64-69 Link Here

(-)linux-2.4.22/drivers/macintosh/via-pmu.c (-50 / +226 lines)
64	/* How many iterations between battery polls */	64	/* How many iterations between battery polls */
65	#define BATTERY_POLLING_COUNT 2	65	#define BATTERY_POLLING_COUNT 2
66		66
		67	/* Some debugging tools */
		68	#ifdef CONFIG_XMON
		69	//#define LIVE_DEBUG(req) ((req) && (req)->data[0] == 0x7d)
		70	#define LIVE_DEBUG(req) (0)
		71	static int whacky_debug;
		72	#endif /* CONFIG_XMON */
		73
67	static volatile unsigned char *via;	74	static volatile unsigned char *via;
68		75
69	/* VIA registers - spaced 0x200 bytes apart */	76	/* VIA registers - spaced 0x200 bytes apart */
Lines 107-112 Link Here
107	intack,	114	intack,
108	reading,	115	reading,
109	reading_intr,	116	reading_intr,
		117	locked,
110	} pmu_state;	118	} pmu_state;
111		119
112	static volatile enum int_data_state {	120	static volatile enum int_data_state {
Lines 134-139 Link Here
134	static int pmu_has_adb;	142	static int pmu_has_adb;
135	static unsigned char *gpio_reg = NULL;	143	static unsigned char *gpio_reg = NULL;
136	static int gpio_irq = -1;	144	static int gpio_irq = -1;
		145	static int gpio_irq_enabled = -1;
137	static volatile int pmu_suspended = 0;	146	static volatile int pmu_suspended = 0;
138	static spinlock_t pmu_lock;	147	static spinlock_t pmu_lock;
139	static u8 pmu_intr_mask;	148	static u8 pmu_intr_mask;
Lines 144-152 Link Here
144	static int sleep_in_progress;	153	static int sleep_in_progress;
145	static int can_sleep;	154	static int can_sleep;
146	#endif /* CONFIG_PMAC_PBOOK */	155	#endif /* CONFIG_PMAC_PBOOK */
		156	static unsigned int pmu_irq_stats[11];
147		157
148	static struct proc_dir_entry *proc_pmu_root;	158	static struct proc_dir_entry *proc_pmu_root;
149	static struct proc_dir_entry *proc_pmu_info;	159	static struct proc_dir_entry *proc_pmu_info;
		160	static struct proc_dir_entry *proc_pmu_irqstats;
150	static struct proc_dir_entry *proc_pmu_options;	161	static struct proc_dir_entry *proc_pmu_options;
151		162
152	#ifdef CONFIG_PMAC_PBOOK	163	#ifdef CONFIG_PMAC_PBOOK
Lines 185-190 Link Here
185	static void gpio1_interrupt(int irq, void arg, struct pt_regs regs);	196	static void gpio1_interrupt(int irq, void arg, struct pt_regs regs);
186	static int proc_get_info(char page, char *start, off_t off,	197	static int proc_get_info(char page, char *start, off_t off,
187	int count, int eof, void data);	198	int count, int eof, void data);
		199	static int proc_get_irqstats(char page, char *start, off_t off,
		200	int count, int eof, void data);
188	#ifdef CONFIG_PMAC_BACKLIGHT	201	#ifdef CONFIG_PMAC_BACKLIGHT
189	static int pmu_set_backlight_level(int level, void* data);	202	static int pmu_set_backlight_level(int level, void* data);
190	static int pmu_set_backlight_enable(int on, int level, void* data);	203	static int pmu_set_backlight_enable(int on, int level, void* data);
Lines 206-212 Link Here
206	pmu_init,	219	pmu_init,
207	pmu_send_request,	220	pmu_send_request,
208	pmu_adb_autopoll,	221	pmu_adb_autopoll,
209	pmu_poll,	222	pmu_poll_adb,
210	pmu_adb_reset_bus	223	pmu_adb_reset_bus
211	};	224	};
212	#endif /* CONFIG_ADB */	225	#endif /* CONFIG_ADB */
Lines 419-424 Link Here
419	if (pmu_kind == PMU_KEYLARGO_BASED && gpio_irq != -1) {	432	if (pmu_kind == PMU_KEYLARGO_BASED && gpio_irq != -1) {
420	if (request_irq(gpio_irq, gpio1_interrupt, 0, "GPIO1/ADB", (void *)0))	433	if (request_irq(gpio_irq, gpio1_interrupt, 0, "GPIO1/ADB", (void *)0))
421	printk(KERN_ERR "pmu: can't get irq %d (GPIO1)\n", gpio_irq);	434	printk(KERN_ERR "pmu: can't get irq %d (GPIO1)\n", gpio_irq);
		435	gpio_irq_enabled = 1;
422	}	436	}
423		437
424	/* Enable interrupts */	438	/* Enable interrupts */
Lines 466-471 Link Here
466	int i;	480	int i;
467	proc_pmu_info = create_proc_read_entry("info", 0, proc_pmu_root,	481	proc_pmu_info = create_proc_read_entry("info", 0, proc_pmu_root,
468	proc_get_info, NULL);	482	proc_get_info, NULL);
		483	proc_pmu_irqstats = create_proc_read_entry("interrupts", 0, proc_pmu_root,
		484	proc_get_irqstats, NULL);
469	#ifdef CONFIG_PMAC_PBOOK	485	#ifdef CONFIG_PMAC_PBOOK
470	for (i=0; i<pmu_battery_count; i++) {	486	for (i=0; i<pmu_battery_count; i++) {
471	char title[16];	487	char title[16];
Lines 540-547 Link Here
540		556
541	/* Read PMU version */	557	/* Read PMU version */
542	pmu_request(&req, NULL, 1, PMU_GET_VERSION);	558	pmu_request(&req, NULL, 1, PMU_GET_VERSION);
543	while (!req.complete)	559	pmu_wait_complete(&req);
544	pmu_poll();
545	if (req.reply_len > 0)	560	if (req.reply_len > 0)
546	pmu_version = req.reply[0];	561	pmu_version = req.reply[0];
547		562
Lines 745-751 Link Here
745		760
746	#endif /* CONFIG_PMAC_PBOOK */	761	#endif /* CONFIG_PMAC_PBOOK */
747		762
748	static int	763	static int __pmac
749	proc_get_info(char page, char *start, off_t off,	764	proc_get_info(char page, char *start, off_t off,
750	int count, int eof, void data)	765	int count, int eof, void data)
751	{	766	{
Lines 762-769 Link Here
762	return p - page;	777	return p - page;
763	}	778	}
764		779
		780	static int __pmac
		781	proc_get_irqstats(char page, char *start, off_t off,
		782	int count, int eof, void data)
		783	{
		784	int i;
		785	char* p = page;
		786	static const char *irq_names[] = {
		787	"Total CB1 triggered events",
		788	"Total GPIO1 triggered events",
		789	"PC-Card eject button",
		790	"Sound/Brightness button",
		791	"ADB message",
		792	"Battery state change",
		793	"Environment interrupt",
		794	"Tick timer",
		795	"Ghost interrupt (zero len)",
		796	"Empty interrupt (empty mask)",
		797	"Max irqs in a row"
		798	};
		799
		800	for (i=0; i<11; i++) {
		801	p += sprintf(p, " %2u: %10u (%s)\n",
		802	i, pmu_irq_stats[i], irq_names[i]);
		803	}
		804	return p - page;
		805	}
		806
765	#ifdef CONFIG_PMAC_PBOOK	807	#ifdef CONFIG_PMAC_PBOOK
766	static int	808	static int __pmac
767	proc_get_batt(char page, char *start, off_t off,	809	proc_get_batt(char page, char *start, off_t off,
768	int count, int eof, void data)	810	int count, int eof, void data)
769	{	811	{
Lines 788-794 Link Here
788	}	830	}
789	#endif /* CONFIG_PMAC_PBOOK */	831	#endif /* CONFIG_PMAC_PBOOK */
790		832
791	static int	833	static int __pmac
792	proc_read_options(char page, char *start, off_t off,	834	proc_read_options(char page, char *start, off_t off,
793	int count, int eof, void data)	835	int count, int eof, void data)
794	{	836	{
Lines 802-808 Link Here
802	return p - page;	844	return p - page;
803	}	845	}
804		846
805	static int	847	static int __pmac
806	proc_write_options(struct file file, const char buffer,	848	proc_write_options(struct file file, const char buffer,
807	unsigned long count, void *data)	849	unsigned long count, void *data)
808	{	850	{
Lines 843-849 Link Here
843		885
844	#ifdef CONFIG_ADB	886	#ifdef CONFIG_ADB
845	/* Send an ADB command */	887	/* Send an ADB command */
846	static int __openfirmware	888	static int __pmac
847	pmu_send_request(struct adb_request *req, int sync)	889	pmu_send_request(struct adb_request *req, int sync)
848	{	890	{
849	int i, ret;	891	int i, ret;
Lines 923-929 Link Here
923	}	965	}
924		966
925	/* Enable/disable autopolling */	967	/* Enable/disable autopolling */
926	static int __openfirmware	968	static int __pmac
927	pmu_adb_autopoll(int devs)	969	pmu_adb_autopoll(int devs)
928	{	970	{
929	struct adb_request req;	971	struct adb_request req;
Lines 946-952 Link Here
946	}	988	}
947		989
948	/* Reset the ADB bus */	990	/* Reset the ADB bus */
949	static int __openfirmware	991	static int __pmac
950	pmu_adb_reset_bus(void)	992	pmu_adb_reset_bus(void)
951	{	993	{
952	struct adb_request req;	994	struct adb_request req;
Lines 971-978 Link Here
971	printk(KERN_ERR "pmu_adb_reset_bus: pmu_queue_request failed\n");	1013	printk(KERN_ERR "pmu_adb_reset_bus: pmu_queue_request failed\n");
972	return -EIO;	1014	return -EIO;
973	}	1015	}
974	while (!req.complete)	1016	pmu_wait_complete(&req);
975	pmu_poll();
976		1017
977	if (save_autopoll != 0)	1018	if (save_autopoll != 0)
978	pmu_adb_autopoll(save_autopoll);	1019	pmu_adb_autopoll(save_autopoll);
Lines 1008-1014 Link Here
1008	return pmu_queue_request(req);	1049	return pmu_queue_request(req);
1009	}	1050	}
1010		1051
1011	int __openfirmware	1052	int __pmac
1012	pmu_queue_request(struct adb_request *req)	1053	pmu_queue_request(struct adb_request *req)
1013	{	1054	{
1014	unsigned long flags;	1055	unsigned long flags;
Lines 1050-1056 Link Here
1050	static inline void	1091	static inline void
1051	wait_for_ack(void)	1092	wait_for_ack(void)
1052	{	1093	{
1053	/* Sightly increased the delay, I had one occurence of the message	1094	/* Sightly increased the delay, I had one occurrence of the message
1054	* reported	1095	* reported
1055	*/	1096	*/
1056	int timeout = 4000;	1097	int timeout = 4000;
Lines 1100-1107 Link Here
1100	(*done)(req);	1141	(*done)(req);
1101	}	1142	}
1102		1143
1103	static void __openfirmware	1144	static void __pmac
1104	pmu_start()	1145	pmu_start(void)
1105	{	1146	{
1106	struct adb_request *req;	1147	struct adb_request *req;
1107		1148
Lines 1122-1138 Link Here
1122	wait_for_ack();	1163	wait_for_ack();
1123	/* set the shift register to shift out and send a byte */	1164	/* set the shift register to shift out and send a byte */
1124	send_byte(req->data[0]);	1165	send_byte(req->data[0]);
		1166	#ifdef CONFIG_XMON
		1167	if (LIVE_DEBUG(req))
		1168	xmon_printf("R");
		1169	else
		1170	whacky_debug = 0;
		1171	#endif /* CONFIG_XMON */
		1172	}
		1173
		1174	void __openfirmware
		1175	pmu_poll(void)
		1176	{
		1177	if (!via)
		1178	return;
		1179	if (disable_poll)
		1180	return;
		1181	via_pmu_interrupt(0, 0, 0);
1125	}	1182	}
1126		1183
1127	void __openfirmware	1184	void __openfirmware
1128	pmu_poll()	1185	pmu_poll_adb(void)
1129	{	1186	{
1130	if (!via)	1187	if (!via)
1131	return;	1188	return;
1132	if (disable_poll)	1189	if (disable_poll)
1133	return;	1190	return;
1134	/* Kicks ADB read when PMU is suspended */	1191	/* Kicks ADB read when PMU is suspended */
1135	if (pmu_suspended)
1136	adb_int_pending = 1;	1192	adb_int_pending = 1;
1137	do {	1193	do {
1138	via_pmu_interrupt(0, 0, 0);	1194	via_pmu_interrupt(0, 0, 0);
Lines 1140-1145 Link Here
1140	\|\| req_awaiting_reply));	1196	\|\| req_awaiting_reply));
1141	}	1197	}
1142		1198
		1199	void __openfirmware
		1200	pmu_wait_complete(struct adb_request *req)
		1201	{
		1202	if (!via)
		1203	return;
		1204	while((pmu_state != idle && pmu_state != locked) \|\| !req->complete)
		1205	via_pmu_interrupt(0, 0, 0);
		1206	}
		1207
1143	/* This function loops until the PMU is idle and prevents it from	1208	/* This function loops until the PMU is idle and prevents it from
1144	* anwsering to ADB interrupts. pmu_request can still be called.	1209	* anwsering to ADB interrupts. pmu_request can still be called.
1145	* This is done to avoid spurrious shutdowns when we know we'll have	1210	* This is done to avoid spurrious shutdowns when we know we'll have
Lines 1164-1169 Link Here
1164		1229
1165	do {	1230	do {
1166	spin_unlock_irqrestore(&pmu_lock, flags);	1231	spin_unlock_irqrestore(&pmu_lock, flags);
		1232	if (req_awaiting_reply)
		1233	adb_int_pending = 1;
1167	via_pmu_interrupt(0, 0, 0);	1234	via_pmu_interrupt(0, 0, 0);
1168	spin_lock_irqsave(&pmu_lock, flags);	1235	spin_lock_irqsave(&pmu_lock, flags);
1169	if (!adb_int_pending && pmu_state == idle && !req_awaiting_reply) {	1236	if (!adb_int_pending && pmu_state == idle && !req_awaiting_reply) {
Lines 1174-1180 Link Here
1174	pmu_poll();	1241	pmu_poll();
1175	#else /* SUSPEND_USES_PMU */	1242	#else /* SUSPEND_USES_PMU */
1176	if (gpio_irq >= 0)	1243	if (gpio_irq >= 0)
1177	disable_irq(gpio_irq);	1244	disable_irq_nosync(gpio_irq);
1178	out_8(&via[IER], CB1_INT \| IER_CLR);	1245	out_8(&via[IER], CB1_INT \| IER_CLR);
1179	spin_unlock_irqrestore(&pmu_lock, flags);	1246	spin_unlock_irqrestore(&pmu_lock, flags);
1180	#endif /* SUSPEND_USES_PMU */	1247	#endif /* SUSPEND_USES_PMU */
Lines 1213-1231 Link Here
1213	}	1280	}
1214		1281
1215	/* Interrupt data could be the result data from an ADB cmd */	1282	/* Interrupt data could be the result data from an ADB cmd */
1216	static void __openfirmware	1283	static void __pmac
1217	pmu_handle_data(unsigned char data, int len, struct pt_regs regs)	1284	pmu_handle_data(unsigned char data, int len, struct pt_regs regs)
1218	{	1285	{
		1286	unsigned char ints, pirq;
		1287	int i = 0;
		1288
1219	asleep = 0;	1289	asleep = 0;
1220	if (drop_interrupts \|\| len < 1) {	1290	if (drop_interrupts \|\| len < 1) {
1221	adb_int_pending = 0;	1291	adb_int_pending = 0;
		1292	pmu_irq_stats[8]++;
1222	return;	1293	return;
1223	}	1294	}
		1295
		1296	/* Get PMU interrupt mask */
		1297	ints = data[0];
		1298
		1299	/* Record zero interrupts for stats */
		1300	if (ints == 0)
		1301	pmu_irq_stats[9]++;
		1302
		1303	/* Hack to deal with ADB autopoll flag */
		1304	if (ints & PMU_INT_ADB)
		1305	ints &= ~(PMU_INT_ADB_AUTO \| PMU_INT_AUTO_SRQ_POLL);
		1306
		1307	next:
		1308
		1309	if (ints == 0) {
		1310	if (i > pmu_irq_stats[10])
		1311	pmu_irq_stats[10] = i;
		1312	return;
		1313	}
		1314
		1315	for (pirq = 0; pirq < 8; pirq++)
		1316	if (ints & (1 << pirq))
		1317	break;
		1318	pmu_irq_stats[pirq]++;
		1319	i++;
		1320	ints &= ~(1 << pirq);
		1321
1224	/* Note: for some reason, we get an interrupt with len=1,	1322	/* Note: for some reason, we get an interrupt with len=1,
1225	* data[0]==0 after each normal ADB interrupt, at least	1323	* data[0]==0 after each normal ADB interrupt, at least
1226	* on the Pismo. Still investigating... --BenH	1324	* on the Pismo. Still investigating... --BenH
1227	*/	1325	*/
1228	if (data[0] & PMU_INT_ADB) {	1326	if ((1 << pirq) & PMU_INT_ADB) {
1229	if ((data[0] & PMU_INT_ADB_AUTO) == 0) {	1327	if ((data[0] & PMU_INT_ADB_AUTO) == 0) {
1230	struct adb_request *req = req_awaiting_reply;	1328	struct adb_request *req = req_awaiting_reply;
1231	if (req == 0) {	1329	if (req == 0) {
Lines 1263-1294 Link Here
1263	adb_input(data+1, len-1, regs, 1);	1361	adb_input(data+1, len-1, regs, 1);
1264	#endif /* CONFIG_ADB */	1362	#endif /* CONFIG_ADB */
1265	}	1363	}
1266	} else {	1364	}
1267	/* Sound/brightness button pressed */	1365	/* Sound/brightness button pressed */
1268	if ((data[0] & PMU_INT_SNDBRT) && len == 3) {	1366	else if ((1 << pirq) & PMU_INT_SNDBRT) {
1269	#ifdef CONFIG_PMAC_BACKLIGHT	1367	#ifdef CONFIG_PMAC_BACKLIGHT
		1368	if (len == 3)
1270	#ifdef CONFIG_INPUT_ADBHID	1369	#ifdef CONFIG_INPUT_ADBHID
1271	if (!disable_kernel_backlight)	1370	if (!disable_kernel_backlight)
1272	#endif /* CONFIG_INPUT_ADBHID */	1371	#endif /* CONFIG_INPUT_ADBHID */
1273	set_backlight_level(data[1] >> 4);	1372	set_backlight_level(data[1] >> 4);
1274	#endif /* CONFIG_PMAC_BACKLIGHT */	1373	#endif /* CONFIG_PMAC_BACKLIGHT */
1275	}	1374	}
		1375	/* Tick interrupt */
		1376	else if ((1 << pirq) & PMU_INT_TICK) {
1276	#ifdef CONFIG_PMAC_PBOOK	1377	#ifdef CONFIG_PMAC_PBOOK
1277	/* Environement or tick interrupt, query batteries */	1378	/* Environement or tick interrupt, query batteries */
1278	if (pmu_battery_count && (data[0] & PMU_INT_TICK)) {	1379	if (pmu_battery_count) {
1279	if ((--query_batt_timer) == 0) {	1380	if ((--query_batt_timer) == 0) {
1280	query_battery_state();	1381	query_battery_state();
1281	query_batt_timer = BATTERY_POLLING_COUNT;	1382	query_batt_timer = BATTERY_POLLING_COUNT;
1282	}	1383	}
1283	} else if (pmu_battery_count && (data[0] & PMU_INT_ENVIRONMENT))	1384	}
		1385	}
		1386	else if ((1 << pirq) & PMU_INT_ENVIRONMENT) {
		1387	if (pmu_battery_count)
1284	query_battery_state();	1388	query_battery_state();
1285	if (data[0])
1286	pmu_pass_intr(data, len);	1389	pmu_pass_intr(data, len);
		1390	} else {
		1391	pmu_pass_intr(data, len);
1287	#endif /* CONFIG_PMAC_PBOOK */	1392	#endif /* CONFIG_PMAC_PBOOK */
1288	}	1393	}
		1394	goto next;
1289	}	1395	}
1290		1396
1291	static struct adb_request* __openfirmware	1397	static struct adb_request* __pmac
1292	pmu_sr_intr(struct pt_regs *regs)	1398	pmu_sr_intr(struct pt_regs *regs)
1293	{	1399	{
1294	struct adb_request *req;	1400	struct adb_request *req;
Lines 1315-1331 Link Here
1315	case sending:	1421	case sending:
1316	req = current_req;	1422	req = current_req;
1317	if (data_len < 0) {	1423	if (data_len < 0) {
		1424	#ifdef CONFIG_XMON
		1425	if (LIVE_DEBUG(req))
		1426	xmon_printf("s");
		1427	#endif /* CONFIG_XMON */
1318	data_len = req->nbytes - 1;	1428	data_len = req->nbytes - 1;
1319	send_byte(data_len);	1429	send_byte(data_len);
1320	break;	1430	break;
1321	}	1431	}
1322	if (data_index <= data_len) {	1432	if (data_index <= data_len) {
		1433	#ifdef CONFIG_XMON
		1434	if (LIVE_DEBUG(req))
		1435	xmon_printf("S");
		1436	#endif /* CONFIG_XMON */
1323	send_byte(req->data[data_index++]);	1437	send_byte(req->data[data_index++]);
1324	break;	1438	break;
1325	}	1439	}
1326	req->sent = 1;	1440	req->sent = 1;
1327	data_len = pmu_data_len[req->data[0]][1];	1441	data_len = pmu_data_len[req->data[0]][1];
1328	if (data_len == 0) {	1442	if (data_len == 0) {
		1443	#ifdef CONFIG_XMON
		1444	if (LIVE_DEBUG(req))
		1445	xmon_printf("D");
		1446	#endif /* CONFIG_XMON */
1329	pmu_state = idle;	1447	pmu_state = idle;
1330	current_req = req->next;	1448	current_req = req->next;
1331	if (req->reply_expected)	1449	if (req->reply_expected)
Lines 1333-1338 Link Here
1333	else	1451	else
1334	return req;	1452	return req;
1335	} else {	1453	} else {
		1454	#ifdef CONFIG_XMON
		1455	if (LIVE_DEBUG(req))
		1456	xmon_printf("-");
		1457	#endif /* CONFIG_XMON */
1336	pmu_state = reading;	1458	pmu_state = reading;
1337	data_index = 0;	1459	data_index = 0;
1338	reply_ptr = req->reply + req->reply_len;	1460	reply_ptr = req->reply + req->reply_len;
Lines 1346-1360 Link Here
1346	pmu_state = reading_intr;	1468	pmu_state = reading_intr;
1347	reply_ptr = interrupt_data[int_data_last];	1469	reply_ptr = interrupt_data[int_data_last];
1348	recv_byte();	1470	recv_byte();
		1471	if (gpio_irq >= 0 && !gpio_irq_enabled) {
		1472	enable_irq(gpio_irq);
		1473	gpio_irq_enabled = 1;
		1474	}
1349	break;	1475	break;
1350		1476
1351	case reading:	1477	case reading:
1352	case reading_intr:	1478	case reading_intr:
1353	if (data_len == -1) {	1479	if (data_len == -1) {
		1480	#ifdef CONFIG_XMON
		1481	if (LIVE_DEBUG(current_req))
		1482	xmon_printf("r");
		1483	#endif /* CONFIG_XMON */
1354	data_len = bite;	1484	data_len = bite;
1355	if (bite > 32)	1485	if (bite > 32)
1356	printk(KERN_ERR "PMU: bad reply len %d\n", bite);	1486	printk(KERN_ERR "PMU: bad reply len %d\n", bite);
1357	} else if (data_index < 32) {	1487	} else if (data_index < 32) {
		1488	#ifdef CONFIG_XMON
		1489	if (LIVE_DEBUG(current_req))
		1490	xmon_printf("R");
		1491	#endif /* CONFIG_XMON */
1358	reply_ptr[data_index++] = bite;	1492	reply_ptr[data_index++] = bite;
1359	}	1493	}
1360	if (data_index < data_len) {	1494	if (data_index < data_len) {
Lines 1362-1375 Link Here
1362	break;	1496	break;
1363	}	1497	}
1364		1498
		1499	#ifdef CONFIG_XMON
		1500	if (LIVE_DEBUG(current_req)) {
		1501	whacky_debug = 1;
		1502	xmon_printf("D");
		1503	}
		1504	#endif /* CONFIG_XMON */
1365	if (pmu_state == reading_intr) {	1505	if (pmu_state == reading_intr) {
1366	pmu_state = idle;	1506	pmu_state = idle;
1367	int_data_state[int_data_last] = int_data_ready;	1507	int_data_state[int_data_last] = int_data_ready;
1368	interrupt_data_len[int_data_last] = data_len;	1508	interrupt_data_len[int_data_last] = data_len;
1369	} else {	1509	} else {
1370	req = current_req;	1510	req = current_req;
		1511	/*
		1512	* For PMU sleep and freq change requests, we lock the
		1513	* PMU until it's explicitely unlocked. This avoids any
		1514	* spurrious event polling getting in
		1515	*/
1371	current_req = req->next;	1516	current_req = req->next;
1372	req->reply_len += data_index;	1517	req->reply_len += data_index;
		1518	if (req->data[0] == PMU_SLEEP \|\| req->data[0] == PMU_CPU_SPEED)
		1519	pmu_state = locked;
		1520	else
1373	pmu_state = idle;	1521	pmu_state = idle;
1374	return req;	1522	return req;
1375	}	1523	}
Lines 1399-1404 Link Here
1399	intr = in_8(&via[IFR]) & (SR_INT \| CB1_INT);	1547	intr = in_8(&via[IFR]) & (SR_INT \| CB1_INT);
1400	if (intr == 0)	1548	if (intr == 0)
1401	break;	1549	break;
		1550	#ifdef CONFIG_XMON
		1551	if (whacky_debug)
		1552	xmon_printf("\|%02x\|", intr);
		1553	#endif /* CONFIG_XMON */
1402	if (++nloop > 1000) {	1554	if (++nloop > 1000) {
1403	printk(KERN_DEBUG "PMU: stuck in intr loop, "	1555	printk(KERN_DEBUG "PMU: stuck in intr loop, "
1404	"intr=%x, ier=%x pmu_state=%d\n",	1556	"intr=%x, ier=%x pmu_state=%d\n",
Lines 1406-1413 Link Here
1406	break;	1558	break;
1407	}	1559	}
1408	out_8(&via[IFR], intr);	1560	out_8(&via[IFR], intr);
1409	if (intr & CB1_INT)	1561	if (intr & CB1_INT) {
1410	adb_int_pending = 1;	1562	adb_int_pending = 1;
		1563	pmu_irq_stats[0]++;
		1564	}
1411	if (intr & SR_INT) {	1565	if (intr & SR_INT) {
1412	req = pmu_sr_intr(regs);	1566	req = pmu_sr_intr(regs);
1413	if (req)	1567	if (req)
Lines 1418-1423 Link Here
1418	recheck:	1572	recheck:
1419	if (pmu_state == idle) {	1573	if (pmu_state == idle) {
1420	if (adb_int_pending) {	1574	if (adb_int_pending) {
		1575	#ifdef CONFIG_XMON
		1576	if (whacky_debug)
		1577	xmon_printf("!A!");
		1578	#endif /* CONFIG_XMON */
1421	if (int_data_state[0] == int_data_empty)	1579	if (int_data_state[0] == int_data_empty)
1422	int_data_last = 0;	1580	int_data_last = 0;
1423	else if (int_data_state[1] == int_data_empty)	1581	else if (int_data_state[1] == int_data_empty)
Lines 1432-1442 Link Here
1432	wait_for_ack();	1590	wait_for_ack();
1433	send_byte(PMU_INT_ACK);	1591	send_byte(PMU_INT_ACK);
1434	adb_int_pending = 0;	1592	adb_int_pending = 0;
1435	no_free_slot:
1436	;
1437	} else if (current_req)	1593	} else if (current_req)
1438	pmu_start();	1594	pmu_start();
1439	}	1595	}
		1596	no_free_slot:
1440	/* Mark the oldest buffer for flushing */	1597	/* Mark the oldest buffer for flushing */
1441	if (int_data_state[!int_data_last] == int_data_ready) {	1598	if (int_data_state[!int_data_last] == int_data_ready) {
1442	int_data_state[!int_data_last] = int_data_flush;	1599	int_data_state[!int_data_last] = int_data_flush;
Lines 1465-1481 Link Here
1465	}	1622	}
1466	}	1623	}
1467		1624
		1625	void __pmac
		1626	pmu_unlock(void)
		1627	{
		1628	unsigned long flags;
		1629
		1630	spin_lock_irqsave(&pmu_lock, flags);
		1631	if (pmu_state == locked)
		1632	pmu_state = idle;
		1633	adb_int_pending = 1;
		1634	spin_unlock_irqrestore(&pmu_lock, flags);
		1635	}
		1636
		1637
1468	static void __openfirmware	1638	static void __openfirmware
1469	gpio1_interrupt(int irq, void arg, struct pt_regs regs)	1639	gpio1_interrupt(int irq, void arg, struct pt_regs regs)
1470	{	1640	{
		1641	unsigned long flags;
		1642
1471	if ((in_8(gpio_reg + 0x9) & 0x02) == 0) {	1643	if ((in_8(gpio_reg + 0x9) & 0x02) == 0) {
		1644	spin_lock_irqsave(&pmu_lock, flags);
		1645	if (gpio_irq_enabled > 0) {
		1646	disable_irq_nosync(gpio_irq);
		1647	gpio_irq_enabled = 0;
		1648	}
		1649	pmu_irq_stats[1]++;
1472	adb_int_pending = 1;	1650	adb_int_pending = 1;
		1651	spin_unlock_irqrestore(&pmu_lock, flags);
1473	via_pmu_interrupt(0, 0, 0);	1652	via_pmu_interrupt(0, 0, 0);
1474	}	1653	}
1475	}	1654	}
1476		1655
1477	#ifdef CONFIG_PMAC_BACKLIGHT	1656	#ifdef CONFIG_PMAC_BACKLIGHT
1478	static int backlight_to_bright[] = {	1657	static int backlight_to_bright[] __pmacdata = {
1479	0x7f, 0x46, 0x42, 0x3e, 0x3a, 0x36, 0x32, 0x2e,	1658	0x7f, 0x46, 0x42, 0x3e, 0x3a, 0x36, 0x32, 0x2e,
1480	0x2a, 0x26, 0x22, 0x1e, 0x1a, 0x16, 0x12, 0x0e	1659	0x2a, 0x26, 0x22, 0x1e, 0x1a, 0x16, 0x12, 0x0e
1481	};	1660	};
Lines 1491-1503 Link Here
1491	if (on) {	1670	if (on) {
1492	pmu_request(&req, NULL, 2, PMU_BACKLIGHT_BRIGHT,	1671	pmu_request(&req, NULL, 2, PMU_BACKLIGHT_BRIGHT,
1493	backlight_to_bright[level]);	1672	backlight_to_bright[level]);
1494	while (!req.complete)	1673	pmu_wait_complete(&req);
1495	pmu_poll();
1496	}	1674	}
1497	pmu_request(&req, NULL, 2, PMU_POWER_CTRL,	1675	pmu_request(&req, NULL, 2, PMU_POWER_CTRL,
1498	PMU_POW_BACKLIGHT \| (on ? PMU_POW_ON : PMU_POW_OFF));	1676	PMU_POW_BACKLIGHT \| (on ? PMU_POW_ON : PMU_POW_OFF));
1499	while (!req.complete)	1677	pmu_wait_complete(&req);
1500	pmu_poll();
1501		1678
1502	return 0;	1679	return 0;
1503	}	1680	}
Lines 1521-1527 Link Here
1521	}	1698	}
1522	#endif /* CONFIG_PMAC_BACKLIGHT */	1699	#endif /* CONFIG_PMAC_BACKLIGHT */
1523		1700
1524	void __openfirmware	1701	void __pmac
1525	pmu_enable_irled(int on)	1702	pmu_enable_irled(int on)
1526	{	1703	{
1527	struct adb_request req;	1704	struct adb_request req;
Lines 1533-1543 Link Here
1533		1710
1534	pmu_request(&req, NULL, 2, PMU_POWER_CTRL, PMU_POW_IRLED \|	1711	pmu_request(&req, NULL, 2, PMU_POWER_CTRL, PMU_POW_IRLED \|
1535	(on ? PMU_POW_ON : PMU_POW_OFF));	1712	(on ? PMU_POW_ON : PMU_POW_OFF));
1536	while (!req.complete)	1713	pmu_wait_complete(&req);
1537	pmu_poll();
1538	}	1714	}
1539		1715
1540	void __openfirmware	1716	void __pmac
1541	pmu_restart(void)	1717	pmu_restart(void)
1542	{	1718	{
1543	struct adb_request req;	1719	struct adb_request req;
Lines 1554-1566 Link Here
1554	}	1730	}
1555		1731
1556	pmu_request(&req, NULL, 1, PMU_RESET);	1732	pmu_request(&req, NULL, 1, PMU_RESET);
1557	while(!req.complete \|\| (pmu_state != idle))	1733	pmu_wait_complete(&req);
1558	pmu_poll();
1559	for (;;)	1734	for (;;)
1560	;	1735	;
1561	}	1736	}
1562		1737
1563	void __openfirmware	1738	void __pmac
1564	pmu_shutdown(void)	1739	pmu_shutdown(void)
1565	{	1740	{
1566	struct adb_request req;	1741	struct adb_request req;
Lines 1572-1585 Link Here
1572	if (pmu_kind != PMU_KEYLARGO_BASED) {	1747	if (pmu_kind != PMU_KEYLARGO_BASED) {
1573	pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, PMU_INT_ADB \|	1748	pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, PMU_INT_ADB \|
1574	PMU_INT_TICK );	1749	PMU_INT_TICK );
1575	while(!req.complete)	1750	pmu_wait_complete(&req);
1576	pmu_poll();
1577	}	1751	}
1578		1752
1579	pmu_request(&req, NULL, 5, PMU_SHUTDOWN,	1753	pmu_request(&req, NULL, 5, PMU_SHUTDOWN,
1580	'M', 'A', 'T', 'T');	1754	'M', 'A', 'T', 'T');
1581	while(!req.complete \|\| (pmu_state != idle))	1755	pmu_wait_complete(&req);
1582	pmu_poll();
1583	for (;;)	1756	for (;;)
1584	;	1757	;
1585	}	1758	}
Lines 2245-2250 Link Here
2245	set_context(current->active_mm->context, current->active_mm->pgd);	2418	set_context(current->active_mm->context, current->active_mm->pgd);
2246		2419
2247	/* Power things up */	2420	/* Power things up */
		2421	pmu_unlock();
2248	pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, 0xfc);	2422	pmu_request(&req, NULL, 2, PMU_SET_INTR_MASK, 0xfc);
2249	while (!req.complete)	2423	while (!req.complete)
2250	pmu_poll();	2424	pmu_poll();
Lines 2410-2415 Link Here
2410	//pbook_pci_restore();	2584	//pbook_pci_restore();
2411		2585
2412	#ifdef DEBUG_SLEEP	2586	#ifdef DEBUG_SLEEP
		2587	pmu_unlock();
2413	pmu_blink(2);	2588	pmu_blink(2);
2414	#endif	2589	#endif
2415	/* Restore L2 cache */	2590	/* Restore L2 cache */
Lines 2423-2428 Link Here
2423	set_context(current->active_mm->context, current->active_mm->pgd);	2598	set_context(current->active_mm->context, current->active_mm->pgd);
2424		2599
2425	/* Tell PMU we are ready */	2600	/* Tell PMU we are ready */
		2601	pmu_unlock();
2426	pmu_request(&req, NULL, 2, PMU_SYSTEM_READY, 2);	2602	pmu_request(&req, NULL, 2, PMU_SYSTEM_READY, 2);
2427	while (!req.complete)	2603	while (!req.complete)
2428	pmu_poll();	2604	pmu_poll();
Lines 2555-2564 Link Here
2555	out_be32(mem_ctrl_sleep, 0x3f);	2731	out_be32(mem_ctrl_sleep, 0x3f);
2556	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,0,0);	2732	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,0,0);
2557	pbook_pci_restore();	2733	pbook_pci_restore();
2558		2734	pmu_unlock();
2559	/* wait for the PMU interrupt sequence to complete */
2560	while (asleep)
2561	mb();
2562		2735
2563	/* reenable interrupts */	2736	/* reenable interrupts */
2564	pmac_sleep_restore_intrs();	2737	pmac_sleep_restore_intrs();
Lines 2921-2928 Link Here
2921		3094
2922	EXPORT_SYMBOL(pmu_request);	3095	EXPORT_SYMBOL(pmu_request);
2923	EXPORT_SYMBOL(pmu_poll);	3096	EXPORT_SYMBOL(pmu_poll);
		3097	EXPORT_SYMBOL(pmu_poll_adb);
		3098	EXPORT_SYMBOL(pmu_wait_complete);
2924	EXPORT_SYMBOL(pmu_suspend);	3099	EXPORT_SYMBOL(pmu_suspend);
2925	EXPORT_SYMBOL(pmu_resume);	3100	EXPORT_SYMBOL(pmu_resume);
		3101	EXPORT_SYMBOL(pmu_unlock);
2926	EXPORT_SYMBOL(pmu_i2c_combined_read);	3102	EXPORT_SYMBOL(pmu_i2c_combined_read);
2927	EXPORT_SYMBOL(pmu_i2c_stdsub_write);	3103	EXPORT_SYMBOL(pmu_i2c_stdsub_write);
2928	EXPORT_SYMBOL(pmu_i2c_simple_read);	3104	EXPORT_SYMBOL(pmu_i2c_simple_read);

Lines 17-23 Link Here

(-)linux-2.4.22/drivers/net/Makefile (-2 / +2 lines)
17		17
18	export-objs := 8390.o arlan.o aironet4500_core.o aironet4500_card.o \	18	export-objs := 8390.o arlan.o aironet4500_core.o aironet4500_card.o \
19	ppp_async.o ppp_generic.o slhc.o pppox.o auto_irq.o \	19	ppp_async.o ppp_generic.o slhc.o pppox.o auto_irq.o \
20	net_init.o mii.o	20	net_init.o mii.o sungem_phy.o
21	list-multi := rcpci.o	21	list-multi := rcpci.o
22	rcpci-objs := rcpci45.o rclanmtl.o	22	rcpci-objs := rcpci45.o rclanmtl.o
23		23
Lines 67-73 Link Here
67	obj-$(CONFIG_SUNQE) += sunqe.o	67	obj-$(CONFIG_SUNQE) += sunqe.o
68	obj-$(CONFIG_SUNBMAC) += sunbmac.o	68	obj-$(CONFIG_SUNBMAC) += sunbmac.o
69	obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o	69	obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
70	obj-$(CONFIG_SUNGEM) += sungem.o	70	obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o
71		71
72	obj-$(CONFIG_MACE) += mace.o	72	obj-$(CONFIG_MACE) += mace.o
73	obj-$(CONFIG_BMAC) += bmac.o	73	obj-$(CONFIG_BMAC) += bmac.o

Lines 1386-1391 Link Here

(-)linux-2.4.22/drivers/net/irda/irda-usb.c (+3 lines)
1386	WARNING("usb-irda: bad class_descriptor type\n");	1386	WARNING("usb-irda: bad class_descriptor type\n");
1387	}	1387	}
1388	else {	1388	else {
		1389	le16_to_cpus (&(desc->wBaudRate));
		1390	le16_to_cpus (&(desc->bcdSpecRevision));
		1391
1389	#ifdef IU_DUMP_CLASS_DESC	1392	#ifdef IU_DUMP_CLASS_DESC
1390	irda_usb_dump_class_desc(desc);	1393	irda_usb_dump_class_desc(desc);
1391	#endif /* IU_DUMP_CLASS_DESC */	1394	#endif /* IU_DUMP_CLASS_DESC */

Lines 69-76 Link Here

(-)linux-2.4.22/drivers/net/ne2k-pci.c (-2 lines)
69	#if defined(__powerpc__)	69	#if defined(__powerpc__)
70	#define inl_le(addr) le32_to_cpu(inl(addr))	70	#define inl_le(addr) le32_to_cpu(inl(addr))
71	#define inw_le(addr) le16_to_cpu(inw(addr))	71	#define inw_le(addr) le16_to_cpu(inw(addr))
72	#define insl insl_ns
73	#define outsl outsl_ns
74	#endif	72	#endif
75		73
76	#define PFX DRV_NAME ": "	74	#define PFX DRV_NAME ": "

Lines 569-575 Link Here

(-)linux-2.4.22/drivers/net/pcnet32.c (-1 / +2 lines)
569	break;	569	break;
570	case 0x2625:	570	case 0x2625:
571	chipname = "PCnet/FAST III 79C973"; /* PCI */	571	chipname = "PCnet/FAST III 79C973"; /* PCI */
572	fdx = 1; mii = 1;	572	fdx = 1; mii = 1; fset = 1;
573	break;	573	break;
574	case 0x2626:	574	case 0x2626:
575	chipname = "PCnet/Home 79C978"; /* PCI */	575	chipname = "PCnet/Home 79C978"; /* PCI */
Lines 612-617 Link Here
612		612
613	if(fset)	613	if(fset)
614	{	614	{
		615	printk(KERN_INFO PFX "Activating Tx error recovery on %s\n", chipname);
615	a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) \| 0x0800));	616	a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) \| 0x0800));
616	a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) \| 0x0c00);	617	a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) \| 0x0c00);
617	dxsuflo = 1;	618	dxsuflo = 1;




 *  - Get rid of all those nasty mdelay's and replace them
 * with schedule_timeout.
 *  - Implement WOL
 *  - Currently, forced Gb mode is only supported on bcm54xx
 *    PHY for which I use the SPD2 bit of the control register.
 *    On m1011 PHY, I can't force as I don't have the specs, but
 *    I can at least detect gigabit with autoneg.
 */

#include <linux/config.h>

#include <asm/pmac_feature.h>
#endif

#include "sungem_phy.h"
#include "sungem.h"

/* Stripping FCS is causing problems, disabled for now */
#undef STRIP_FCS

#define DEFAULT_MSG	(NETIF_MSG_DRV		| \
			 NETIF_MSG_PROBE	| \
			 NETIF_MSG_LINK)

#define ADVERTISE_MASK	(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
			 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)

#define DRV_NAME	"sungem"
#define DRV_VERSION	"0.97"
#define DRV_RELDATE	"3/20/02"

MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
MODULE_LICENSE("GPL");

MODULE_PARM(gem_debug, "i");
MODULE_PARM_DESC(gem_debug, "bitmapped message enable number");
MODULE_PARM(link_mode, "i");
MODULE_PARM_DESC(link_mode, "default link mode");

int gem_debug = -1;
static int link_mode;

static u16 link_modes[] __devinitdata = {
	BMCR_ANENABLE,			/* 0 : autoneg */
	0,				/* 1 : 10bt half duplex */
	BMCR_SPEED100,			/* 2 : 100bt half duplex */
	BMCR_SPD2, /* bcm54xx only */   /* 3 : 1000bt half duplex */
	BMCR_FULLDPLX,			/* 4 : 10bt full duplex */
	BMCR_SPEED100|BMCR_FULLDPLX,	/* 5 : 100bt full duplex */
	BMCR_SPD2|BMCR_FULLDPLX		/* 6 : 1000bt full duplex */
};

#define GEM_MODULE_NAME	"gem"
#define PFX GEM_MODULE_NAME ": "


	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
	{0, }
};

MODULE_DEVICE_TABLE(pci, gem_pci_tbl);

static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
{
	u32 cmd;
	int limit = 10000;

	return cmd & MIF_FRAME_DATA;
}

static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
{
	struct gem *gp = dev->priv;
	return __phy_read(gp, mii_id, reg);
}

static inline u16 phy_read(struct gem *gp, int reg)
{
	return __phy_read(gp, gp->mii_phy_addr, reg);
}

static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
{
	u32 cmd;
	int limit = 10000;

	}
}

static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
{
	struct gem *gp = dev->priv;
	__phy_write(gp, mii_id, reg, val & 0xffff);
}

static inline void phy_write(struct gem *gp, int reg, u16 val)
{
	__phy_write(gp, gp->mii_phy_addr, reg, val);
}

static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)

	if (pcs_miistat & PCS_MIISTAT_LS) {
		printk(KERN_INFO "%s: PCS link is now up.\n",
		       dev->name);
		netif_carrier_on(gp->dev);
	} else {
		printk(KERN_INFO "%s: PCS link is now down.\n",
		       dev->name);
		netif_carrier_off(gp->dev);
		/* If this happens and the link timer is not running,
		 * reset so we re-negotiate.
		 */


		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
	}
	mb();
	gp->rx_new = gp->rx_old = 0;

	/* Now we must reprogram the rest of RX unit. */

			gp->dev->name, rxmac_stat);

	if (rxmac_stat & MAC_RXSTAT_OFLW) {
		u32 smac = readl(gp->regs + MAC_SMACHINE);

		printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
				dev->name, smac);
		gp->net_stats.rx_over_errors++;
		gp->net_stats.rx_fifo_errors++;


			count = 0;
		}
	}
	mb();
	if (kick >= 0)
		writel(kick, gp->regs + RXDMA_KICK);
}

		/* We must give this initial chunk to the device last.
		 * Otherwise we could race with the device.
		 */
		first_len = skb_headlen(skb);
		first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
					     ((unsigned long) skb->data & ~PAGE_MASK),
					     first_len, PCI_DMA_TODEVICE);

	if (netif_msg_tx_queued(gp))
		printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
		       dev->name, entry, skb->len);
	mb();
	writel(gp->tx_new, gp->regs + TXDMA_KICK);
	spin_unlock_irq(&gp->lock);


	} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));

	if (limit <= 0)
		printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
}

/* Must be invoked under gp->lock. */


}

/* Link modes of the BCM5400 PHY */
static int phy_BCM5400_link_table[8][3] = {
	{ 0, 0, 0 },	/* No link */
	{ 0, 0, 0 },	/* 10BT Half Duplex */
	{ 1, 0, 0 },	/* 10BT Full Duplex */
	{ 0, 1, 0 },	/* 100BT Half Duplex */
	{ 0, 1, 0 },	/* 100BT Half Duplex */
	{ 1, 1, 0 },	/* 100BT Full Duplex*/
	{ 1, 0, 1 },	/* 1000BT */
	{ 1, 0, 1 },	/* 1000BT */
};

/* Must be invoked under gp->lock. */
// XXX dbl check what that function should do when called on PCS PHY
static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
{
	u32 advertise, features;
	int autoneg;
	int speed;
	int duplex;

	if (gp->phy_type != phy_mii_mdio0 &&
     	    gp->phy_type != phy_mii_mdio1)
     	    	goto non_mii;

	/* Setup advertise */
	if (found_mii_phy(gp))
		features = gp->phy_mii.def->features;
	else
		features = 0;

	advertise = features & ADVERTISE_MASK;
	if (gp->phy_mii.advertising != 0)
		advertise &= gp->phy_mii.advertising;

	autoneg = gp->want_autoneg;
	speed = gp->phy_mii.speed;
	duplex = gp->phy_mii.duplex;
	
	/* Setup link parameters */
	if (!ep)
		goto start_aneg;
	if (ep->autoneg == AUTONEG_ENABLE) {
		advertise = ep->advertising;
		autoneg = 1;
		gp->link_advertise |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
		/* Can I advertise gigabit here ? I'd need BCM PHY docs... */
		gp->link_cntl = BMCR_ANENABLE;
	} else {
		autoneg = 0;
		speed = ep->speed;
		duplex = ep->duplex;
		else if (ep->speed == SPEED_1000 && gp->gigabit_capable)
			/* Hrm... check if this is right... */
			gp->link_cntl |= BMCR_SPD2;
		if (ep->duplex == DUPLEX_FULL)
			gp->link_cntl |= BMCR_FULLDPLX;
	}

start_aneg:
	/* Sanitize settings based on PHY capabilities */
	if ((features & SUPPORTED_Autoneg) == 0)
		autoneg = 0;
	if (speed == SPEED_1000 &&
	    !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
		speed = SPEED_100;
	if (speed == SPEED_100 &&
	    !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
		speed = SPEED_10;
	if (duplex == DUPLEX_FULL &&
	    !(features & (SUPPORTED_1000baseT_Full |
	    		  SUPPORTED_100baseT_Full |
	    		  SUPPORTED_10baseT_Full)))
	    	duplex = DUPLEX_HALF;
	if (speed == 0)
		speed = SPEED_10;
	
	/* If HW is down, we don't try to actually setup the PHY, we
	 * just store the settings
	 */
	if (!gp->hw_running) {
		gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
		gp->phy_mii.speed = speed;
		gp->phy_mii.duplex = duplex;
		return;
	}

	/* Configure PHY & start aneg */
	gp->want_autoneg = autoneg;
	if (autoneg) {
		if (found_mii_phy(gp))
			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
		ctl |= BMCR_ANRESTART;
		gp->lstate = link_aneg;
	} else {
		if (found_mii_phy(gp))
			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
		gp->lstate = link_force_ok;
	}
	phy_write(gp, MII_BMCR, ctl);

non_mii:
	gp->timer_ticks = 0;
	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
}

/* Must be invoked under gp->lock. */
static void gem_read_mii_link_mode(struct gem *gp, int *fd, int *spd, int *pause)
{
	u32 val;

	*fd = 0;
	*spd = 10;
	*pause = 0;
	
	if (gp->phy_mod == phymod_bcm5400 ||
	    gp->phy_mod == phymod_bcm5401 ||
	    gp->phy_mod == phymod_bcm5411) {
		int link_mode;	

	    	val = phy_read(gp, MII_BCM5400_AUXSTATUS);
		link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
			     MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
		*fd = phy_BCM5400_link_table[link_mode][0];
		*spd = phy_BCM5400_link_table[link_mode][2] ?
			1000 :
			(phy_BCM5400_link_table[link_mode][1] ? 100 : 10);
		val = phy_read(gp, MII_LPA);
		if (val & LPA_PAUSE)
			*pause = 1;
	} else {
		val = phy_read(gp, MII_LPA);

		if (val & (LPA_10FULL | LPA_100FULL))
			*fd = 1;
		if (val & (LPA_100FULL | LPA_100HALF))
			*spd = 100;

		if (gp->phy_mod == phymod_m1011) {
			val = phy_read(gp, 0x0a);
			if (val & 0xc00)
				*spd = 1000;
			if (val & 0x800)
				*fd = 1;
		}
	}
}

/* A link-up condition has occurred, initialize and enable the
 * rest of the chip.
 *
 * Must be invoked under gp->lock.
 */
static int gem_set_link_modes(struct gem *gp)
{
	u32 val;
	int full_duplex, speed, pause;

	full_duplex = 0;
	speed = SPEED_10;
	pause = 0;

	if (found_mii_phy(gp)) {
	    	if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
	    		return 1;
		full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
		speed = gp->phy_mii.speed;
		pause = gp->phy_mii.pause;
	} else if (gp->phy_type == phy_serialink ||
	    	   gp->phy_type == phy_serdes) {
			if (val & BMCR_SPEED100)
				speed = 100;
		}
	} else {
		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);

		if (pcs_lpa & PCS_MIIADV_FD)
			full_duplex = 1;
		speed = SPEED_1000;
	}

	if (netif_msg_link(gp))

		val |= MAC_XIFCFG_FLED;
	}

	if (speed == SPEED_1000)
		val |= (MAC_XIFCFG_GMII);

	writel(val, gp->regs + MAC_XIFCFG);

	/* If gigabit and half-duplex, enable carrier extension
	 * mode.  Else, disable it.
	 */
	if (speed == SPEED_1000 && !full_duplex) {
		val = readl(gp->regs + MAC_TXCFG);
		writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);


	writel(val, gp->regs + MAC_MCCFG);

	gem_start_dma(gp);

	return 0;
}

/* Must be invoked under gp->lock. */
static int gem_mdio_link_not_up(struct gem *gp)
{
	switch (gp->lstate) {
	case link_force_ret:
	if (gp->lstate == link_force_ret) {
		if (netif_msg_link(gp))
			printk(KERN_INFO "%s: Autoneg failed again, keeping"
				" forced mode\n", gp->dev->name);
		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
			gp->last_forced_speed, DUPLEX_HALF);
		gp->timer_ticks = 5;
		gp->lstate = link_force_ok;
		return 0;
	case link_aneg:

		if (netif_msg_link(gp))
			printk(KERN_INFO "%s: switching to forced 100bt\n",
				gp->dev->name);
		/* Try forced modes. */
		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
			DUPLEX_HALF);
		val |= BMCR_SPEED100;
		phy_write(gp, MII_BMCR, val);
		gp->timer_ticks = 5;
		gp->lstate = link_force_try;
		return 0;
	case link_force_try:
		/* Downgrade from 100 to 10 Mbps if necessary.
		 * If already at 10Mbps, warn user about the
		 * situation every 10 ticks.
		 */
		if (gp->phy_mii.speed == SPEED_100) {
			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
				DUPLEX_HALF);
			phy_write(gp, MII_BMCR, val);
			gp->timer_ticks = 5;
			if (netif_msg_link(gp))
				printk(KERN_INFO "%s: switching to forced 10bt\n",
					gp->dev->name);
			return 0;
		} else
			return 1;
	default:
		return 0;
	}
	return 0;
}

static void gem_init_rings(struct gem *);

static void gem_link_timer(unsigned long data)
{
	struct gem *gp = (struct gem *) data;
	int restart_aneg = 0;
		
	if (!gp->hw_running)
		return;


	if (gp->reset_task_pending)
		goto restart;
	    	
	if (gp->phy_type == phy_serialink ||
	    gp->phy_type == phy_serdes) {
		u16 val = phy_read(gp, MII_BMSR);
		u16 cntl = phy_read(gp, MII_BMCR);
		int up;

		/* When using autoneg, we really wait for ANEGCOMPLETE or we may
		 * get a "transcient" incorrect link state
		 */
		if (cntl & BMCR_ANENABLE)
			up = (val & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) == (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
		else
			up = (val & BMSR_LSTATUS) != 0;
		if (up) {
			/* Ok, here we got a link. If we had it due to a forced
			 * fallback, and we were configured for autoneg, we do
			 * retry a short autoneg pass. If you know your hub is
			 * broken, use ethtool ;)
			 */
			if (gp->lstate == link_force_try && (gp->link_cntl & BMCR_ANENABLE)) {
				gp->lstate = link_force_ret;
				gp->link_fcntl = phy_read(gp, MII_BMCR);
				gp->timer_ticks = 5;
				if (netif_msg_link(gp))
					printk(KERN_INFO "%s: Got link after fallback, retrying"
						" autoneg once...\n", gp->dev->name);
				phy_write(gp, MII_BMCR,
					  gp->link_fcntl | BMCR_ANENABLE | BMCR_ANRESTART);
			} else if (gp->lstate != link_up) {
				gp->lstate = link_up;
				if (gp->opened)
					gem_set_link_modes(gp);
			}
		} else {
			int restart = 0;

			/* If the link was previously up, we restart the
			 * whole process
			 */
			if (gp->lstate == link_up) {
				gp->lstate = link_down;
				if (netif_msg_link(gp))
					printk(KERN_INFO "%s: Link down\n",
						gp->dev->name);
				gp->reset_task_pending = 2;
				schedule_task(&gp->reset_task);
				restart = 1;
			} else if (++gp->timer_ticks > 10)
				restart = gem_mdio_link_not_up(gp);

			if (restart) {
				gem_begin_auto_negotiation(gp, NULL);
				goto out_unlock;
			}
		}
	} else {
		u32 val = readl(gp->regs + PCS_MIISTAT);

		if (!(val & PCS_MIISTAT_LS))


		if ((val & PCS_MIISTAT_LS) != 0) {
			gp->lstate = link_up;
			netif_carrier_on(gp->dev);
			if (gp->opened)
				(void)gem_set_link_modes(gp);
		}
		goto restart;
	}
	if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
		/* Ok, here we got a link. If we had it due to a forced
		 * fallback, and we were configured for autoneg, we do
		 * retry a short autoneg pass. If you know your hub is
		 * broken, use ethtool ;)
		 */
		if (gp->lstate == link_force_try && gp->want_autoneg) {
			gp->lstate = link_force_ret;
			gp->last_forced_speed = gp->phy_mii.speed;
			gp->timer_ticks = 5;
			if (netif_msg_link(gp))
				printk(KERN_INFO "%s: Got link after fallback, retrying"
					" autoneg once...\n", gp->dev->name);
			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
		} else if (gp->lstate != link_up) {
			gp->lstate = link_up;
			netif_carrier_on(gp->dev);
			if (gp->opened && gem_set_link_modes(gp))
				restart_aneg = 1;
		}
	} else {
		/* If the link was previously up, we restart the
		 * whole process
		 */
		if (gp->lstate == link_up) {
			gp->lstate = link_down;
			if (netif_msg_link(gp))
				printk(KERN_INFO "%s: Link down\n",
					gp->dev->name);
			netif_carrier_off(gp->dev);
			gp->reset_task_pending = 2;
			schedule_task(&gp->reset_task);
			restart_aneg = 1;
		} else if (++gp->timer_ticks > 10) {
			if (found_mii_phy(gp))
				restart_aneg = gem_mdio_link_not_up(gp);
			else
				restart_aneg = 1;
		}
	}
	if (restart_aneg) {
		gem_begin_auto_negotiation(gp, NULL);
		goto out_unlock;
	}

restart:
	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
out_unlock:

		txd->control_word = 0;
		txd->buffer = 0;
	}
	mb();

/* Must be invoked under gp->lock. */
static int gem_reset_one_mii_phy(struct gem *gp, int phy_addr)
{
	u16 val;
	int limit = 10000;
	
	val = __phy_read(gp, MII_BMCR, phy_addr);
	val &= ~BMCR_ISOLATE;
	val |= BMCR_RESET;
	__phy_write(gp, MII_BMCR, val, phy_addr);

	udelay(100);

	while (limit--) {
		val = __phy_read(gp, MII_BMCR, phy_addr);
		if ((val & BMCR_RESET) == 0)
			break;
		udelay(10);
	}
	if ((val & BMCR_ISOLATE) && limit > 0)
		__phy_write(gp, MII_BMCR, val & ~BMCR_ISOLATE, phy_addr);
	
	return (limit <= 0);
}

/* Must be invoked under gp->lock. */
static void gem_init_bcm5201_phy(struct gem *gp)
{
	u16 data;

	data = phy_read(gp, MII_BCM5201_MULTIPHY);
	data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
	phy_write(gp, MII_BCM5201_MULTIPHY, data);
}

/* Must be invoked under gp->lock. */
static void gem_init_bcm5400_phy(struct gem *gp)
{
	u16 data;

	/* Configure for gigabit full duplex */
	data = phy_read(gp, MII_BCM5400_AUXCONTROL);
	data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
	phy_write(gp, MII_BCM5400_AUXCONTROL, data);
	
	data = phy_read(gp, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(gp, MII_BCM5400_GB_CONTROL, data);
	
	mdelay(10);

	/* Reset and configure cascaded 10/100 PHY */
	gem_reset_one_mii_phy(gp, 0x1f);
	
	data = __phy_read(gp, MII_BCM5201_MULTIPHY, 0x1f);
	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
	__phy_write(gp, MII_BCM5201_MULTIPHY, data, 0x1f);

	data = phy_read(gp, MII_BCM5400_AUXCONTROL);
	data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
	phy_write(gp, MII_BCM5400_AUXCONTROL, data);
}

/* Must be invoked under gp->lock. */
static void gem_init_bcm5401_phy(struct gem *gp)
{
	u16 data;
	int rev;

	rev = phy_read(gp, MII_PHYSID2) & 0x000f;
	if (rev == 0 || rev == 3) {
		/* Some revisions of 5401 appear to need this
		 * initialisation sequence to disable, according
		 * to OF, "tap power management"
		 * 
		 * WARNING ! OF and Darwin don't agree on the
		 * register addresses. OF seem to interpret the
		 * register numbers below as decimal
		 *
		 * Note: This should (and does) match tg3_init_5401phy_dsp
		 *       in the tg3.c driver. -DaveM
		 */
		phy_write(gp, 0x18, 0x0c20);
		phy_write(gp, 0x17, 0x0012);
		phy_write(gp, 0x15, 0x1804);
		phy_write(gp, 0x17, 0x0013);
		phy_write(gp, 0x15, 0x1204);
		phy_write(gp, 0x17, 0x8006);
		phy_write(gp, 0x15, 0x0132);
		phy_write(gp, 0x17, 0x8006);
		phy_write(gp, 0x15, 0x0232);
		phy_write(gp, 0x17, 0x201f);
		phy_write(gp, 0x15, 0x0a20);
	}
	
	/* Configure for gigabit full duplex */
	data = phy_read(gp, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(gp, MII_BCM5400_GB_CONTROL, data);

	mdelay(1);

	/* Reset and configure cascaded 10/100 PHY */
	gem_reset_one_mii_phy(gp, 0x1f);
	
	data = __phy_read(gp, MII_BCM5201_MULTIPHY, 0x1f);
	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
	__phy_write(gp, MII_BCM5201_MULTIPHY, data, 0x1f);
}

/* Must be invoked under gp->lock. */
static void gem_init_bcm5411_phy(struct gem *gp)
{
	u16 data;

	/* Here's some more Apple black magic to setup
	 * some voltage stuffs.
	 */
	phy_write(gp, 0x1c, 0x8c23);
	phy_write(gp, 0x1c, 0x8ca3);
	phy_write(gp, 0x1c, 0x8c23);

	/* Here, Apple seems to want to reset it, do
	 * it as well
	 */
	phy_write(gp, MII_BMCR, BMCR_RESET);

	/* Start autoneg */
	phy_write(gp, MII_BMCR,
		  (BMCR_ANENABLE | BMCR_FULLDPLX |
		   BMCR_ANRESTART | BMCR_SPD2));

	data = phy_read(gp, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(gp, MII_BCM5400_GB_CONTROL, data);
}

/* Must be invoked under gp->lock. */
static void gem_init_phy(struct gem *gp)
{
	u32 mifcfg;
	
	if (!gp->wake_on_lan && gp->phy_mod == phymod_bcm5201)
		phy_write(gp, MII_BCM5201_INTERRUPT, 0);

	/* Revert MIF CFG setting done on stop_phy */
	mifcfg = readl(gp->regs + MIF_CFG);
	mifcfg &= ~MIF_CFG_BBMODE;

	
#ifdef CONFIG_ALL_PPC
	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
		int i, j;

		/* Those delay sucks, the HW seem to love them though, I'll
		 * serisouly consider breaking some locks here to be able
		 * to schedule instead
		 */
		pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
		mdelay(10);
		for (j = 0; j < 3; j++) {
			/* Some PHYs used by apple have problem getting back to us,
			 * we _know_ it's actually at addr 0, that's a hack, but
			 * it helps to do that reset now. I suspect some motherboards
			 * don't wire the PHY reset line properly, thus the PHY doesn't
			 * come back with the above pmac_call_feature.
			 */
			gp->mii_phy_addr = 0;
			phy_write(gp, MII_BMCR, BMCR_RESET);
			/* We should probably break some locks here and schedule... */
			mdelay(10);
			for (i = 0; i < 32; i++) {
				gp->mii_phy_addr = i;
				if (phy_read(gp, MII_BMCR) != 0xffff)
					break;
			}
			if (i == 32) {
				printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
				       gp->dev->name);
				gp->mii_phy_addr = 0;
			} else
				break;
		}
		if (i == 32) {
			printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
			       gp->dev->name);
			return;
		}
	}
#endif /* CONFIG_ALL_PPC */



	if (gp->phy_type == phy_mii_mdio0 ||
	    gp->phy_type == phy_mii_mdio1) {
	    	// XXX check for errors
		mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
	
		/* Take PHY out of isloate mode and reset it. */
		gem_reset_one_mii_phy(gp, gp->mii_phy_addr);

		phy_id = (phy_read(gp, MII_PHYSID1) << 16 | phy_read(gp, MII_PHYSID2))
			 	& 0xfffffff0;
		printk(KERN_INFO "%s: MII PHY ID: %x ", gp->dev->name, phy_id);
		switch(phy_id) {
		case 0x406210:
			gp->phy_mod = phymod_bcm5201;
			gem_init_bcm5201_phy(gp);
			printk("BCM 5201\n");
			break;

		case 0x4061e0:
			printk("BCM 5221\n");
			gp->phy_mod = phymod_bcm5221;
			break;

		case 0x206040:
			printk("BCM 5400\n");
			gp->phy_mod = phymod_bcm5400;
			gem_init_bcm5400_phy(gp);
			gp->gigabit_capable = 1;
			break;

		case 0x206050:
			printk("BCM 5401\n");
			gp->phy_mod = phymod_bcm5401;
			gem_init_bcm5401_phy(gp);
			gp->gigabit_capable = 1;
			break;

		case 0x206070:
			printk("BCM 5411\n");
			gp->phy_mod = phymod_bcm5411;
			gem_init_bcm5411_phy(gp);
			gp->gigabit_capable = 1;
			break;
		case 0x1410c60:
			printk("M1011 (Marvel ?)\n");
			gp->phy_mod = phymod_m1011;
			gp->gigabit_capable = 1;
			break;

		case 0x18074c0:
			printk("Lucent\n");
			gp->phy_mod = phymod_generic;
			break;

		case 0x437420:
			printk("Enable Semiconductor\n");
			gp->phy_mod = phymod_generic;
			break;

		default:
			printk("Unknown (Using generic mode)\n");
			gp->phy_mod = phymod_generic;
			break;
		};

		/* Init PHY */
		if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
			gp->phy_mii.def->ops->init(&gp->phy_mii);
		phy_write(gp, MII_BMCR, val);
		udelay(10);
		
		phy_write(gp, MII_ADVERTISE,
			  phy_read(gp, MII_ADVERTISE) |
			  (ADVERTISE_10HALF | ADVERTISE_10FULL |
			   ADVERTISE_100HALF | ADVERTISE_100FULL));
	} else {
		u32 val;
		int limit;

		else
			val |= PCS_SCTRL_LOOP;
		writel(val, gp->regs + PCS_SCTRL);
		gp->gigabit_capable = 1;
	}

	/* BMCR_SPD2 is a broadcom 54xx specific thing afaik */
	if (gp->phy_mod != phymod_bcm5400 && gp->phy_mod != phymod_bcm5401 &&
	    gp->phy_mod != phymod_bcm5411)
	    	gp->link_cntl &= ~BMCR_SPD2;
}

/* Must be invoked under gp->lock. */

{
	unsigned char *e = &gp->dev->dev_addr[0];

	writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM)
		writel(0x1bf0, gp->regs + MAC_SNDPAUSE);

	writel(0x00, gp->regs + MAC_IPG0);
	writel(0x08, gp->regs + MAC_IPG1);

	writel(0, gp->regs + MAC_AF0MSK);

	gp->mac_rx_cfg = gem_setup_multicast(gp);
#ifdef STRIP_FCS
	gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
#endif
	writel(0, gp->regs + MAC_NCOLL);
	writel(0, gp->regs + MAC_FASUCC);
	writel(0, gp->regs + MAC_ECOLL);

		/* Default aneg parameters */
		gp->timer_ticks = 0;
		gp->lstate = link_down;
		netif_carrier_off(gp->dev);

		/* Can I advertise gigabit here ? I'd need BCM PHY docs... */
		gem_begin_auto_negotiation(gp, NULL);
	} else {
		if (gp->lstate == link_up) {
			netif_carrier_on(gp->dev);
			gem_set_link_modes(gp);
		}
	}
}


{
	u32 mifcfg;

	if (!gp->wake_on_lan && gp->phy_mod == phymod_bcm5201)
		phy_write(gp, MII_BCM5201_INTERRUPT, 0);

	/* Make sure we aren't polling PHY status change. We
	 * don't currently use that feature though
	 */

	mifcfg &= ~MIF_CFG_POLL;
	writel(mifcfg, gp->regs + MIF_CFG);

	/* Here's a strange hack used by both MacOS 9 and X */
	phy_write(gp, MII_LPA, phy_read(gp, MII_LPA));

	if (gp->wake_on_lan) {
		/* Setup wake-on-lan */
	} else

		gem_stop(gp);
		writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
		writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
	}
		    gp->phy_mod == phymod_bcm5411) {
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
			phy_write(gp, MII_BMCR, BMCR_PDOWN);
#endif
		} else if (gp->phy_mod == phymod_bcm5201 || gp->phy_mod == phymod_bcm5221) {
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
			u16 val = phy_read(gp, MII_BCM5201_AUXMODE2)
			phy_write(gp, MII_BCM5201_AUXMODE2,
				  val & ~MII_BCM5201_AUXMODE2_LOWPOWER);
#endif				
			phy_write(gp, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
		} else if (gp->phy_mod == phymod_m1011)
			phy_write(gp, MII_BMCR, BMCR_PDOWN);

	if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
		gp->phy_mii.def->ops->suspend(&gp->phy_mii, 0 /* wake on lan options */);

	if (!gp->wake_on_lan) {
		/* According to Apple, we must set the MDIO pins to this begnign
		 * state or we may 1) eat more current, 2) damage some PHYs
		 */

		gp->hw_running = 1;
	}

	spin_lock_irq(&gp->lock);

	/* We can now request the interrupt as we know it's masked
	 * on the controller
	 */
	if (request_irq(gp->pdev->irq, gem_interrupt,
			SA_SHIRQ, dev->name, (void *)dev)) {
		spin_unlock_irq(&gp->lock);

		printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);

#ifdef CONFIG_ALL_PPC

		gp->pm_timer.expires = jiffies + 10*HZ;
		add_timer(&gp->pm_timer);
		up(&gp->pm_sem);
		spin_unlock_irq(&gp->lock);

		return -EAGAIN;
	}

       	spin_lock_irq(&gp->lock);

	/* Allocate & setup ring buffers */
	gem_init_rings(gp);


	netif_stop_queue(dev);

	rxcfg = readl(gp->regs + MAC_RXCFG);
	rxcfg_new = gem_setup_multicast(gp);
#ifdef STRIP_FCS
	rxcfg_new |= MAC_RXCFG_SFCS;
#endif
	gp->mac_rx_cfg = rxcfg_new;
	
	writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
	while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {

static int gem_ethtool_ioctl(struct net_device *dev, void *ep_user)
{
	struct gem *gp = dev->priv;
	u16 bmcr;
	int full_duplex, speed, pause;
	struct ethtool_cmd ecmd;

	if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))

		
	switch(ecmd.cmd) {
        case ETHTOOL_GDRVINFO: {
		struct ethtool_drvinfo info = { .cmd = ETHTOOL_GDRVINFO };

		strncpy(info.driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
		strncpy(info.version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);

	}

	case ETHTOOL_GSET:
		if (gp->phy_type == phy_mii_mdio0 ||
	     	    gp->phy_type == phy_mii_mdio1) {
	     	    	if (gp->phy_mii.def)
	     	    		ecmd.supported = gp->phy_mii.def->features;
	     	    	else
	     	    		ecmd.supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;

			/* XXX hardcoded stuff for now */
			ecmd.port = PORT_MII;
			ecmd.transceiver = XCVR_EXTERNAL;
			ecmd.phy_address = 0; /* XXX fixed PHYAD */

			/* Return current PHY settings */
			spin_lock_irq(&gp->lock);
			ecmd.autoneg = gp->want_autoneg;
			ecmd.speed = gp->phy_mii.speed;
			ecmd.duplex = gp->phy_mii.duplex;			
			ecmd.advertising = gp->phy_mii.advertising;
			/* If we started with a forced mode, we don't have a default
			 * advertise set, we need to return something sensible so
			 * userland can re-enable autoneg properly */
			if (ecmd.advertising == 0)
				ecmd.advertising = ecmd.supported;
			spin_unlock_irq(&gp->lock);
		} else { // XXX PCS ?
	     	    ecmd.supported =
			(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
			 SUPPORTED_Autoneg);
		    ecmd.advertising = ecmd.supported;
		if (gp->gigabit_capable)
			ecmd.supported |=
				(SUPPORTED_1000baseT_Half |
				 SUPPORTED_1000baseT_Full);

		/* XXX hardcoded stuff for now */
		ecmd.port = PORT_MII;
		ecmd.transceiver = XCVR_EXTERNAL;
		ecmd.phy_address = 0; /* XXX fixed PHYAD */

		/* Record PHY settings if HW is on. */
		spin_lock_irq(&gp->lock);
		if (gp->hw_running) {
			bmcr = phy_read(gp, MII_BMCR);
			gem_read_mii_link_mode(gp, &full_duplex, &speed, &pause);
		} else
			bmcr = 0;
		spin_unlock_irq(&gp->lock);
		if (bmcr & BMCR_ANENABLE) {
			ecmd.autoneg = AUTONEG_ENABLE;
			ecmd.speed = speed == 10 ? SPEED_10 : (speed == 1000 ? SPEED_1000 : SPEED_100);
			ecmd.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
		} else {
			ecmd.autoneg = AUTONEG_DISABLE;
			ecmd.speed =
				(bmcr & BMCR_SPEED100) ?
				SPEED_100 : SPEED_10;
			ecmd.duplex =
				(bmcr & BMCR_FULLDPLX) ?
				DUPLEX_FULL : DUPLEX_HALF;
		}
		if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
			return -EFAULT;

		    ecmd.autoneg != AUTONEG_DISABLE)
			return -EINVAL;

		if (ecmd.autoneg == AUTONEG_ENABLE &&
		    ecmd.advertising == 0)
		    	return -EINVAL;

		if (ecmd.autoneg == AUTONEG_DISABLE &&
		    ((ecmd.speed != SPEED_1000 &&
		      ecmd.speed != SPEED_100 &&
		      ecmd.speed != SPEED_10) ||
		     (ecmd.duplex != DUPLEX_HALF &&
		      ecmd.duplex != DUPLEX_FULL)))
			return -EINVAL;
	      
		/* Apply settings and restart link process. */
		spin_lock_irq(&gp->lock);
		gem_begin_auto_negotiation(gp, &ecmd);

		return 0;

	case ETHTOOL_NWAY_RST:
		if (!gp->want_autoneg)
			return -EINVAL;

		/* Restart link process. */


	/* get link status */
	case ETHTOOL_GLINK: {
		struct ethtool_value edata = { .cmd = ETHTOOL_GLINK };

		edata.data = (gp->lstate == link_up);
		if (copy_to_user(ep_user, &edata, sizeof(edata)))


	/* get message-level */
	case ETHTOOL_GMSGLVL: {
		struct ethtool_value edata = { .cmd = ETHTOOL_GMSGLVL };

		edata.data = gp->msg_enable;
		if (copy_to_user(ep_user, &edata, sizeof(edata)))

		/* Fallthrough... */

	case SIOCGMIIREG:		/* Read MII PHY register. */
		if (!gp->hw_running)
			rc = -EIO;
		else {
			data->val_out = __phy_read(gp, data->phy_id & 0x1f, data->reg_num & 0x1f);
			rc = 0;
		}
		break;

	case SIOCSMIIREG:		/* Write MII PHY register. */
		if (!capable(CAP_NET_ADMIN))
			rc = -EPERM;
		else if (!gp->hw_running)
			rc = -EIO;
		else {
			__phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
			rc = 0;
		}
		break;

	 */
	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
	    pdev->device == PCI_DEVICE_ID_SUN_GEM &&
	    !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
		pci_using_dac = 1;
	} else {
		err = pci_set_dma_mask(pdev, (u64) 0xffffffff);

	dev->base_addr = (long) pdev;
	gp->dev = dev;

	gp->msg_enable = DEFAULT_MSG;

	spin_lock_init(&gp->lock);
	init_MUTEX(&gp->pm_sem);

	INIT_TQUEUE(&gp->pm_task, gem_pm_task, gp);
	INIT_TQUEUE(&gp->reset_task, gem_reset_task, gp);
	
	/* Default link parameters */
	if (link_mode >= 0 && link_mode <= 6)
		gp->link_cntl = link_modes[link_mode];
	else
		gp->link_cntl = BMCR_ANENABLE;
	gp->lstate = link_down;
	gp->timer_ticks = 0;
	netif_carrier_off(dev);

	gp->regs = (unsigned long) ioremap(gemreg_base, gemreg_len);
	if (gp->regs == 0UL) {

	gem_stop(gp);
	spin_unlock_irq(&gp->lock);

	/* Fill up the mii_phy structure (even if we won't use it) */
	gp->phy_mii.dev = dev;
	gp->phy_mii.mdio_read = _phy_read;
	gp->phy_mii.mdio_write = _phy_write;

	/* By default, we start with autoneg */
	gp->want_autoneg = 1;
	
	if (gem_check_invariants(gp))
		goto err_out_iounmap;

	/* It is guaranteed that the returned buffer will be at least
	gp->hw_running = 1;
	gem_init_phy(gp);
	gem_begin_auto_negotiation(gp, NULL);
	spin_unlock_irq(&gp->lock);

	/* It is guarenteed that the returned buffer will be at least
	 * PAGE_SIZE aligned.
	 */
	gp->init_block = (struct gem_init_block *)


	printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
	       dev->name);

	for (i = 0; i < 6; i++)
		printk("%2.2x%c", dev->dev_addr[i],
		       i == 5 ? ' ' : ':');
	printk("\n");

	/* Detect & init PHY, start autoneg */
	spin_lock_irq(&gp->lock);
	gp->hw_running = 1;
	gem_init_phy(gp);
	gem_begin_auto_negotiation(gp, NULL);
	spin_unlock_irq(&gp->lock);

	if (gp->phy_type == phy_mii_mdio0 ||
     	    gp->phy_type == phy_mii_mdio1)
		printk(KERN_INFO "%s: Found %s PHY\n", dev->name, 
			gp->phy_mii.def ? gp->phy_mii.def->name : "no");

	pci_set_drvdata(pdev, dev);

	dev->open = gem_open;




	u64	buffer;
};

#define TXDCTRL_BUFSZ	0x0000000000007fffULL	/* Buffer Size		*/
#define TXDCTRL_CSTART	0x00000000001f8000ULL	/* CSUM Start Offset	*/
#define TXDCTRL_COFF	0x000000001fe00000ULL	/* CSUM Stuff Offset	*/
#define TXDCTRL_CENAB	0x0000000020000000ULL	/* CSUM Enable		*/
#define TXDCTRL_EOF	0x0000000040000000ULL	/* End of Frame		*/
#define TXDCTRL_SOF	0x0000000080000000ULL	/* Start of Frame	*/
#define TXDCTRL_INTME	0x0000000100000000ULL	/* "Interrupt Me"	*/
#define TXDCTRL_NOCRC	0x0000000200000000ULL	/* No CRC Present	*/

/* GEM requires that RX descriptors are provided four at a time,
 * aligned.  Also, the RX ring may not wrap around.  This means that

	u64	buffer;
};

#define RXDCTRL_TCPCSUM	0x000000000000ffffULL	/* TCP Pseudo-CSUM	*/
#define RXDCTRL_BUFSZ	0x000000007fff0000ULL	/* Buffer Size		*/
#define RXDCTRL_OWN	0x0000000080000000ULL	/* GEM owns this entry	*/
#define RXDCTRL_HASHVAL	0x0ffff00000000000ULL	/* Hash Value		*/
#define RXDCTRL_HPASS	0x1000000000000000ULL	/* Passed Hash Filter	*/
#define RXDCTRL_ALTMAC	0x2000000000000000ULL	/* Matched ALT MAC	*/
#define RXDCTRL_BAD	0x4000000000000000ULL	/* Frame has bad CRC	*/

#define RXDCTRL_FRESH(gp)	\
	((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \

	phy_serdes,
};

enum gem_phy_model {
	phymod_generic,
	phymod_bcm5201,
	phymod_bcm5221,
	phymod_bcm5400,
	phymod_bcm5401,
	phymod_bcm5411,
	phymod_m1011,
};

enum link_state {
	link_down = 0,	/* No link, will retry */
	link_aneg,	/* Autoneg in progress */

	struct net_device_stats net_stats;

	enum gem_phy_type	phy_type;
	struct mii_phy		phy_mii;
	
	int			tx_fifo_sz;
	int			rx_fifo_sz;
	int			rx_pause_off;
	int			rx_pause_on;
	int			mii_phy_addr;
	int			gigabit_capable;

	u32			mac_rx_cfg;
	u32			swrst_base;

	/* Autoneg & PHY control */
	int			want_autoneg;
	int			last_forced_speed;
	int			link_fcntl;
	enum link_state		lstate;
	struct timer_list	link_timer;
	int			timer_ticks;

#endif
};

#define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) \
				&& gp->phy_mii.def && gp->phy_mii.def->ops)
			
#define ALIGNED_RX_SKB_ADDR(addr) \
        ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)




/*
 * PHY drivers for the sungem ethernet driver.
 * 
 * This file could be shared with other drivers.
 * 
 * (c) 2002, Benjamin Herrenscmidt (benh@kernel.crashing.org)
 *
 * TODO:
 *  - Implement WOL
 *  - Add support for PHYs that provide an IRQ line
 *  - Eventually moved the entire polling state machine in
 *    there (out of the eth driver), so that it can easily be
 *    skipped on PHYs that implement it in hardware.
 *  - On LXT971 & BCM5201, Apple uses some chip specific regs
 *    to read the link status. Figure out why and if it makes
 *    sense to do the same (magic aneg ?)
 *  - Apple has some additional power management code for some
 *    Broadcom PHYs that they "hide" from the OpenSource version
 *    of darwin, still need to reverse engineer that
 */

#include <linux/config.h>

#include <linux/module.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>

#include "sungem_phy.h"

/* Link modes of the BCM5400 PHY */
static int phy_BCM5400_link_table[8][3] = {
	{ 0, 0, 0 },	/* No link */
	{ 0, 0, 0 },	/* 10BT Half Duplex */
	{ 1, 0, 0 },	/* 10BT Full Duplex */
	{ 0, 1, 0 },	/* 100BT Half Duplex */
	{ 0, 1, 0 },	/* 100BT Half Duplex */
	{ 1, 1, 0 },	/* 100BT Full Duplex*/
	{ 1, 0, 1 },	/* 1000BT */
	{ 1, 0, 1 },	/* 1000BT */
};

static inline int __phy_read(struct mii_phy* phy, int id, int reg)
{
	return phy->mdio_read(phy->dev, id, reg);
}

static inline void __phy_write(struct mii_phy* phy, int id, int reg, int val)
{
	phy->mdio_write(phy->dev, id, reg, val);
}

static inline int phy_read(struct mii_phy* phy, int reg)
{
	return phy->mdio_read(phy->dev, phy->mii_id, reg);
}

static inline void phy_write(struct mii_phy* phy, int reg, int val)
{
	phy->mdio_write(phy->dev, phy->mii_id, reg, val);
}

static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
{
	u16 val;
	int limit = 10000;
	
	val = __phy_read(phy, phy_id, MII_BMCR);
	val &= ~BMCR_ISOLATE;
	val |= BMCR_RESET;
	__phy_write(phy, phy_id, MII_BMCR, val);

	udelay(100);

	while (limit--) {
		val = __phy_read(phy, phy_id, MII_BMCR);
		if ((val & BMCR_RESET) == 0)
			break;
		udelay(10);
	}
	if ((val & BMCR_ISOLATE) && limit > 0)
		__phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
	
	return (limit <= 0);
}

static int bcm5201_init(struct mii_phy* phy)
{
	u16 data;

	data = phy_read(phy, MII_BCM5201_MULTIPHY);
	data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
	phy_write(phy, MII_BCM5201_MULTIPHY, data);

	return 0;
}

static int bcm5201_suspend(struct mii_phy* phy, int wol_options)
{
	if (!wol_options)
		phy_write(phy, MII_BCM5201_INTERRUPT, 0);

	/* Here's a strange hack used by both MacOS 9 and X */
	phy_write(phy, MII_LPA, phy_read(phy, MII_LPA));
	
	if (!wol_options) {
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
		u16 val = phy_read(phy, MII_BCM5201_AUXMODE2)
		phy_write(phy, MII_BCM5201_AUXMODE2,
			  val & ~MII_BCM5201_AUXMODE2_LOWPOWER);
#endif			
		phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
	}

	return 0;
}

static int bcm5221_init(struct mii_phy* phy)
{
	u16 data;

	data = phy_read(phy, MII_BCM5221_TEST);
	phy_write(phy, MII_BCM5221_TEST,
		data | MII_BCM5221_TEST_ENABLE_SHADOWS);

	data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
	phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
		data | MII_BCM5221_SHDOW_AUX_STAT2_APD);

	data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
	phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
		data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);

	data = phy_read(phy, MII_BCM5221_TEST);
	phy_write(phy, MII_BCM5221_TEST,
		data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);

	return 0;
}

static int bcm5400_init(struct mii_phy* phy)
{
	u16 data;

	/* Configure for gigabit full duplex */
	data = phy_read(phy, MII_BCM5400_AUXCONTROL);
	data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
	phy_write(phy, MII_BCM5400_AUXCONTROL, data);
	
	data = phy_read(phy, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(phy, MII_BCM5400_GB_CONTROL, data);
	
	mdelay(10);

	/* Reset and configure cascaded 10/100 PHY */
	(void)reset_one_mii_phy(phy, 0x1f);
	
	data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
	__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);

	data = phy_read(phy, MII_BCM5400_AUXCONTROL);
	data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
	phy_write(phy, MII_BCM5400_AUXCONTROL, data);

	return 0;
}

static int bcm5400_suspend(struct mii_phy* phy, int wol_options)
{
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
	phy_write(phy, MII_BMCR, BMCR_PDOWN);
#endif
	return 0;
}

static int bcm5401_init(struct mii_phy* phy)
{
	u16 data;
	int rev;

	rev = phy_read(phy, MII_PHYSID2) & 0x000f;
	if (rev == 0 || rev == 3) {
		/* Some revisions of 5401 appear to need this
		 * initialisation sequence to disable, according
		 * to OF, "tap power management"
		 * 
		 * WARNING ! OF and Darwin don't agree on the
		 * register addresses. OF seem to interpret the
		 * register numbers below as decimal
		 *
		 * Note: This should (and does) match tg3_init_5401phy_dsp
		 *       in the tg3.c driver. -DaveM
		 */
		phy_write(phy, 0x18, 0x0c20);
		phy_write(phy, 0x17, 0x0012);
		phy_write(phy, 0x15, 0x1804);
		phy_write(phy, 0x17, 0x0013);
		phy_write(phy, 0x15, 0x1204);
		phy_write(phy, 0x17, 0x8006);
		phy_write(phy, 0x15, 0x0132);
		phy_write(phy, 0x17, 0x8006);
		phy_write(phy, 0x15, 0x0232);
		phy_write(phy, 0x17, 0x201f);
		phy_write(phy, 0x15, 0x0a20);
	}
	
	/* Configure for gigabit full duplex */
	data = phy_read(phy, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(phy, MII_BCM5400_GB_CONTROL, data);

	mdelay(10);

	/* Reset and configure cascaded 10/100 PHY */
	(void)reset_one_mii_phy(phy, 0x1f);
	
	data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
	__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);

	return 0;
}

static int bcm5401_suspend(struct mii_phy* phy, int wol_options)
{
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
	phy_write(phy, MII_BMCR, BMCR_PDOWN);
#endif
	return 0;
}

static int bcm5411_init(struct mii_phy* phy)
{
	u16 data;

	/* Here's some more Apple black magic to setup
	 * some voltage stuffs.
	 */
	phy_write(phy, 0x1c, 0x8c23);
	phy_write(phy, 0x1c, 0x8ca3);
	phy_write(phy, 0x1c, 0x8c23);

	/* Here, Apple seems to want to reset it, do
	 * it as well
	 */
	phy_write(phy, MII_BMCR, BMCR_RESET);
	phy_write(phy, MII_BMCR, 0x1340);

	data = phy_read(phy, MII_BCM5400_GB_CONTROL);
	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
	phy_write(phy, MII_BCM5400_GB_CONTROL, data);

	mdelay(10);

	/* Reset and configure cascaded 10/100 PHY */
	(void)reset_one_mii_phy(phy, 0x1f);
	
	return 0;
}

static int bcm5411_suspend(struct mii_phy* phy, int wol_options)
{
	phy_write(phy, MII_BMCR, BMCR_PDOWN);

	return 0;
}

static int bcm5421_init(struct mii_phy* phy)
{
	u16 data;
	int rev;

	rev = phy_read(phy, MII_PHYSID2) & 0x000f;
	if (rev == 0) {
		/* This is borrowed from MacOS
		 */
		phy_write(phy, 0x18, 0x1007);
		data = phy_read(phy, 0x18);
		phy_write(phy, 0x18, data | 0x0400);
		phy_write(phy, 0x18, 0x0007);
		data = phy_read(phy, 0x18);
		phy_write(phy, 0x18, data | 0x0800);
		phy_write(phy, 0x17, 0x000a);
		data = phy_read(phy, 0x15);
		phy_write(phy, 0x15, data | 0x0200);
	}
#if 0
	/* This has to be verified before I enable it */
	/* Enable automatic low-power */
	phy_write(phy, 0x1c, 0x9002);
	phy_write(phy, 0x1c, 0xa821);
	phy_write(phy, 0x1c, 0x941d);
#endif
	return 0;
}

static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
{
	u16 ctl, adv;
	
	phy->autoneg = 1;
	phy->speed = SPEED_10;
	phy->duplex = DUPLEX_HALF;
	phy->pause = 0;
	phy->advertising = advertise;

	/* Setup standard advertise */
	adv = phy_read(phy, MII_ADVERTISE);
	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
	if (advertise & ADVERTISED_10baseT_Half)
		adv |= ADVERTISE_10HALF;
	if (advertise & ADVERTISED_10baseT_Full)
		adv |= ADVERTISE_10FULL;
	if (advertise & ADVERTISED_100baseT_Half)
		adv |= ADVERTISE_100HALF;
	if (advertise & ADVERTISED_100baseT_Full)
		adv |= ADVERTISE_100FULL;
	phy_write(phy, MII_ADVERTISE, adv);

	/* Setup 1000BT advertise */
	adv = phy_read(phy, MII_1000BASETCONTROL);
	adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
	if (advertise & SUPPORTED_1000baseT_Half)
		adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
	if (advertise & SUPPORTED_1000baseT_Full)
		adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
	phy_write(phy, MII_1000BASETCONTROL, adv);

	/* Start/Restart aneg */
	ctl = phy_read(phy, MII_BMCR);
	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
{
	u16 ctl;
	
	phy->autoneg = 0;
	phy->speed = speed;
	phy->duplex = fd;
	phy->pause = 0;

	ctl = phy_read(phy, MII_BMCR);
	ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);

	/* First reset the PHY */
	phy_write(phy, MII_BMCR, ctl | BMCR_RESET);

	/* Select speed & duplex */
	switch(speed) {
	case SPEED_10:
		break;
	case SPEED_100:
		ctl |= BMCR_SPEED100;
		break;
	case SPEED_1000:
		ctl |= BMCR_SPD2;
	}
	if (fd == DUPLEX_FULL)
		ctl |= BMCR_FULLDPLX;

	// XXX Should we set the sungem to GII now on 1000BT ?
	
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int bcm54xx_read_link(struct mii_phy *phy)
{
	int link_mode;	
	u16 val;
	
	if (phy->autoneg) {
	    	val = phy_read(phy, MII_BCM5400_AUXSTATUS);
		link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
			     MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
		phy->duplex = phy_BCM5400_link_table[link_mode][0] ? DUPLEX_FULL : DUPLEX_HALF;
		phy->speed = phy_BCM5400_link_table[link_mode][2] ?
				SPEED_1000 :
				(phy_BCM5400_link_table[link_mode][1] ? SPEED_100 : SPEED_10);
		val = phy_read(phy, MII_LPA);
		phy->pause = ((val & LPA_PAUSE) != 0);
	}
	/* On non-aneg, we assume what we put in BMCR is the speed,
	 * though magic-aneg shouldn't prevent this case from occurring
	 */

	return 0;
}

static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
{
	u16 ctl, adv;
	
	phy->autoneg = 1;
	phy->speed = SPEED_10;
	phy->duplex = DUPLEX_HALF;
	phy->pause = 0;
	phy->advertising = advertise;

	/* Setup standard advertise */
	adv = phy_read(phy, MII_ADVERTISE);
	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
	if (advertise & ADVERTISED_10baseT_Half)
		adv |= ADVERTISE_10HALF;
	if (advertise & ADVERTISED_10baseT_Full)
		adv |= ADVERTISE_10FULL;
	if (advertise & ADVERTISED_100baseT_Half)
		adv |= ADVERTISE_100HALF;
	if (advertise & ADVERTISED_100baseT_Full)
		adv |= ADVERTISE_100FULL;
	phy_write(phy, MII_ADVERTISE, adv);

	/* Setup 1000BT advertise & enable crossover detect
	 * XXX How do we advertise 1000BT ? Darwin source is
	 * confusing here, they read from specific control and
	 * write to control... Someone has specs for those
	 * beasts ?
	 */
	adv = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
	adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
	adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
			MII_1000BASETCONTROL_HALFDUPLEXCAP);
	if (advertise & SUPPORTED_1000baseT_Half)
		adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
	if (advertise & SUPPORTED_1000baseT_Full)
		adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
	phy_write(phy, MII_1000BASETCONTROL, adv);

	/* Start/Restart aneg */
	ctl = phy_read(phy, MII_BMCR);
	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
{
	u16 ctl, ctl2;
	
	phy->autoneg = 0;
	phy->speed = speed;
	phy->duplex = fd;
	phy->pause = 0;

	ctl = phy_read(phy, MII_BMCR);
	ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
	ctl |= BMCR_RESET;

	/* Select speed & duplex */
	switch(speed) {
	case SPEED_10:
		break;
	case SPEED_100:
		ctl |= BMCR_SPEED100;
		break;
	/* I'm not sure about the one below, again, Darwin source is
	 * quite confusing and I lack chip specs
	 */
	case SPEED_1000:
		ctl |= BMCR_SPD2;
	}
	if (fd == DUPLEX_FULL)
		ctl |= BMCR_FULLDPLX;

	/* Disable crossover. Again, the way Apple does it is strange,
	 * though I don't assume they are wrong ;)
	 */
	ctl2 = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
	ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
		MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
		MII_1000BASETCONTROL_FULLDUPLEXCAP |
		MII_1000BASETCONTROL_HALFDUPLEXCAP);
	if (speed == SPEED_1000)
		ctl2 |= (fd == DUPLEX_FULL) ?
			MII_1000BASETCONTROL_FULLDUPLEXCAP :
			MII_1000BASETCONTROL_HALFDUPLEXCAP;
	phy_write(phy, MII_1000BASETCONTROL, ctl2);

	// XXX Should we set the sungem to GII now on 1000BT ?
	
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int marvell_read_link(struct mii_phy *phy)
{
	u16 status;

	if (phy->autoneg) {
		status = phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
		if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
			return -EAGAIN;
		if (status & MII_M1011_PHY_SPEC_STATUS_1000)
			phy->speed = SPEED_1000;
		else if (status & MII_M1011_PHY_SPEC_STATUS_100)
			phy->speed = SPEED_100;
		else
			phy->speed = SPEED_10;
		if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
			phy->duplex = DUPLEX_FULL;
		else
			phy->duplex = DUPLEX_HALF;
		phy->pause = 0; /* XXX Check against spec ! */
	}
	/* On non-aneg, we assume what we put in BMCR is the speed,
	 * though magic-aneg shouldn't prevent this case from occurring
	 */

	return 0;
}

static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
	u16 ctl, adv;
	
	phy->autoneg = 1;
	phy->speed = SPEED_10;
	phy->duplex = DUPLEX_HALF;
	phy->pause = 0;
	phy->advertising = advertise;

	/* Setup standard advertise */
	adv = phy_read(phy, MII_ADVERTISE);
	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
	if (advertise & ADVERTISED_10baseT_Half)
		adv |= ADVERTISE_10HALF;
	if (advertise & ADVERTISED_10baseT_Full)
		adv |= ADVERTISE_10FULL;
	if (advertise & ADVERTISED_100baseT_Half)
		adv |= ADVERTISE_100HALF;
	if (advertise & ADVERTISED_100baseT_Full)
		adv |= ADVERTISE_100FULL;
	phy_write(phy, MII_ADVERTISE, adv);

	/* Start/Restart aneg */
	ctl = phy_read(phy, MII_BMCR);
	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
	u16 ctl;
	
	phy->autoneg = 0;
	phy->speed = speed;
	phy->duplex = fd;
	phy->pause = 0;

	ctl = phy_read(phy, MII_BMCR);
	ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);

	/* First reset the PHY */
	phy_write(phy, MII_BMCR, ctl | BMCR_RESET);

	/* Select speed & duplex */
	switch(speed) {
	case SPEED_10:
		break;
	case SPEED_100:
		ctl |= BMCR_SPEED100;
		break;
	case SPEED_1000:
	default:
		return -EINVAL;
	}
	if (fd == DUPLEX_FULL)
		ctl |= BMCR_FULLDPLX;
	phy_write(phy, MII_BMCR, ctl);

	return 0;
}

static int genmii_poll_link(struct mii_phy *phy)
{
	u16 status;
	
	(void)phy_read(phy, MII_BMSR);
	status = phy_read(phy, MII_BMSR);
	if ((status & BMSR_LSTATUS) == 0)
		return 0;
	if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
		return 0;
	return 1;
}

static int genmii_read_link(struct mii_phy *phy)
{
	u16 lpa;

	if (phy->autoneg) {
		lpa = phy_read(phy, MII_LPA);

		if (lpa & (LPA_10FULL | LPA_100FULL))
			phy->duplex = DUPLEX_FULL;
		else
			phy->duplex = DUPLEX_HALF;
		if (lpa & (LPA_100FULL | LPA_100HALF))
			phy->speed = SPEED_100;
		else
			phy->speed = SPEED_10;
		phy->pause = 0;
	}
	/* On non-aneg, we assume what we put in BMCR is the speed,
	 * though magic-aneg shouldn't prevent this case from occurring
	 */

	 return 0;
}


#define MII_BASIC_FEATURES	(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
				 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
				 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
#define MII_GBIT_FEATURES	(MII_BASIC_FEATURES | \
				 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)

/* Broadcom BCM 5201 */
static struct mii_phy_ops bcm5201_phy_ops = {
	init:		bcm5201_init,
	suspend:	bcm5201_suspend,
	setup_aneg:	genmii_setup_aneg,
	setup_forced:	genmii_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	genmii_read_link,
};

static struct mii_phy_def bcm5201_phy_def = {
	phy_id:		0x00406210,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5201",
	features:	MII_BASIC_FEATURES,
	magic_aneg:	0,
	ops:		&bcm5201_phy_ops
};

/* Broadcom BCM 5221 */
static struct mii_phy_ops bcm5221_phy_ops = {
	suspend:	bcm5201_suspend,
	init:		bcm5221_init,
	setup_aneg:	genmii_setup_aneg,
	setup_forced:	genmii_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	genmii_read_link,
};

static struct mii_phy_def bcm5221_phy_def = {
	phy_id:		0x004061e0,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5221",
	features:	MII_BASIC_FEATURES,
	magic_aneg:	0,
	ops:		&bcm5221_phy_ops
};

/* Broadcom BCM 5400 */
static struct mii_phy_ops bcm5400_phy_ops = {
	init:		bcm5400_init,
	suspend:	bcm5400_suspend,
	setup_aneg:	bcm54xx_setup_aneg,
	setup_forced:	bcm54xx_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	bcm54xx_read_link,
};

static struct mii_phy_def bcm5400_phy_def = {
	phy_id:		0x00206040,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5400",
	features:	MII_GBIT_FEATURES,
	magic_aneg:	1,
	ops:		&bcm5400_phy_ops
};

/* Broadcom BCM 5401 */
static struct mii_phy_ops bcm5401_phy_ops = {
	init:		bcm5401_init,
	suspend:	bcm5401_suspend,
	setup_aneg:	bcm54xx_setup_aneg,
	setup_forced:	bcm54xx_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	bcm54xx_read_link,
};

static struct mii_phy_def bcm5401_phy_def = {
	phy_id:		0x00206050,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5401",
	features:	MII_GBIT_FEATURES,
	magic_aneg:	1,
	ops:		&bcm5401_phy_ops
};

/* Broadcom BCM 5411 */
static struct mii_phy_ops bcm5411_phy_ops = {
	init:		bcm5411_init,
	suspend:	bcm5411_suspend,
	setup_aneg:	bcm54xx_setup_aneg,
	setup_forced:	bcm54xx_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	bcm54xx_read_link,
};

static struct mii_phy_def bcm5411_phy_def = {
	phy_id:		0x00206070,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5411",
	features:	MII_GBIT_FEATURES,
	magic_aneg:	1,
	ops:		&bcm5411_phy_ops
};

/* Broadcom BCM 5421 */
static struct mii_phy_ops bcm5421_phy_ops = {
	init:		bcm5421_init,
	suspend:	bcm5411_suspend,
	setup_aneg:	bcm54xx_setup_aneg,
	setup_forced:	bcm54xx_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	bcm54xx_read_link,
};

static struct mii_phy_def bcm5421_phy_def = {
	phy_id:		0x002060e0,
	phy_id_mask:	0xfffffff0,
	name:		"BCM5421",
	features:	MII_GBIT_FEATURES,
	magic_aneg:	1,
	ops:		&bcm5421_phy_ops
};

/* Marvell 88E1101 (Apple seem to deal with 2 different revs,
 * I masked out the 8 last bits to get both, but some specs
 * would be useful here) --BenH.
 */
static struct mii_phy_ops marvell_phy_ops = {
	setup_aneg:	marvell_setup_aneg,
	setup_forced:	marvell_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	marvell_read_link
};

static struct mii_phy_def marvell_phy_def = {
	phy_id:		0x01410c00,
	phy_id_mask:	0xffffff00,
	name:		"Marvell 88E1101",
	features:	MII_GBIT_FEATURES,
	magic_aneg:	1,
	ops:		&marvell_phy_ops
};

/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
	setup_aneg:	genmii_setup_aneg,
	setup_forced:	genmii_setup_forced,
	poll_link:	genmii_poll_link,
	read_link:	genmii_read_link
};

static struct mii_phy_def genmii_phy_def = {
	phy_id:		0x00000000,
	phy_id_mask:	0x00000000,
	name:		"Generic MII",
	features:	MII_BASIC_FEATURES,
	magic_aneg:	0,
	ops:		&generic_phy_ops
};

static struct mii_phy_def* mii_phy_table[] = {
	&bcm5201_phy_def,
	&bcm5221_phy_def,
	&bcm5400_phy_def,
	&bcm5401_phy_def,
	&bcm5411_phy_def,
	&bcm5421_phy_def,
	&marvell_phy_def,
	&genmii_phy_def,
	NULL
};

int mii_phy_probe(struct mii_phy *phy, int mii_id)
{
	int rc;
	u32 id;
	struct mii_phy_def* def;
	int i;

	/* We do not reset the mii_phy structure as the driver
	 * may re-probe the PHY regulary
	 */
	phy->mii_id = mii_id;
	
	/* Take PHY out of isloate mode and reset it. */
	rc = reset_one_mii_phy(phy, mii_id);
	if (rc)
		goto fail;

	/* Read ID and find matching entry */	
	id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2))
			 	& 0xfffffff0;
	for (i=0; (def = mii_phy_table[i]) != NULL; i++)
		if ((id & def->phy_id_mask) == def->phy_id)
			break;
	/* Should never be NULL (we have a generic entry), but... */
	if (def == NULL)
		goto fail;

	phy->def = def;
	
	return 0;
fail:
	phy->speed = 0;
	phy->duplex = 0;
	phy->pause = 0;
	phy->advertising = 0;
	return -ENODEV;
}

EXPORT_SYMBOL(mii_phy_probe);
MODULE_LICENSE("GPL");





#ifndef __SUNGEM_PHY_H__
#define __SUNGEM_PHY_H__

struct mii_phy;

/* Operations supported by any kind of PHY */
struct mii_phy_ops
{
	int		(*init)(struct mii_phy *phy);
	int		(*suspend)(struct mii_phy *phy, int wol_options);
	int		(*setup_aneg)(struct mii_phy *phy, u32 advertise);
	int		(*setup_forced)(struct mii_phy *phy, int speed, int fd);
	int		(*poll_link)(struct mii_phy *phy);
	int		(*read_link)(struct mii_phy *phy);
};

/* Structure used to statically define an mii/gii based PHY */
struct mii_phy_def
{
	u32				phy_id;		/* Concatenated ID1 << 16 | ID2 */
	u32				phy_id_mask;	/* Significant bits */
	u32				features;	/* Ethtool SUPPORTED_* defines */
	int				magic_aneg;	/* Autoneg does all speed test for us */
	const char*			name;
	const struct mii_phy_ops*	ops;
};

/* An instance of a PHY, partially borrowed from mii_if_info */
struct mii_phy
{
	struct mii_phy_def*	def;
	int			advertising;
	int			mii_id;

	/* 1: autoneg enabled, 0: disabled */
	int			autoneg;

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int			speed;
	int			duplex;
	int			pause;

	/* Provided by host chip */
	struct net_device*	dev;
	int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
	void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
};

/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
 * filled, the remaining fields will be filled on return
 */
extern int mii_phy_probe(struct mii_phy *phy, int mii_id);


/* MII definitions missing from mii.h */

#define BMCR_SPD2	0x0040		/* Gigabit enable (bcm54xx)	*/
#define LPA_PAUSE	0x0400

/* More PHY registers (model specific) */

/* MII BCM5201 MULTIPHY interrupt register */
#define MII_BCM5201_INTERRUPT			0x1A
#define MII_BCM5201_INTERRUPT_INTENABLE		0x4000

#define MII_BCM5201_AUXMODE2			0x1B
#define MII_BCM5201_AUXMODE2_LOWPOWER		0x0008

#define MII_BCM5201_MULTIPHY                    0x1E

/* MII BCM5201 MULTIPHY register bits */
#define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
#define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008

/* MII BCM5221 Additional registers */
#define MII_BCM5221_TEST			0x1f
#define MII_BCM5221_TEST_ENABLE_SHADOWS		0x0080
#define MII_BCM5221_SHDOW_AUX_STAT2		0x1b
#define MII_BCM5221_SHDOW_AUX_STAT2_APD		0x0020
#define MII_BCM5221_SHDOW_AUX_MODE4		0x1a
#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR	0x0004

/* MII BCM5400 1000-BASET Control register */
#define MII_BCM5400_GB_CONTROL			0x09
#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP	0x0200

/* MII BCM5400 AUXCONTROL register */
#define MII_BCM5400_AUXCONTROL                  0x18
#define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004

/* MII BCM5400 AUXSTATUS register */
#define MII_BCM5400_AUXSTATUS                   0x19
#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8  

/* 1000BT control (Marvell & BCM54xx at least) */
#define MII_1000BASETCONTROL			0x09
#define MII_1000BASETCONTROL_FULLDUPLEXCAP	0x0200
#define MII_1000BASETCONTROL_HALFDUPLEXCAP	0x0100

/* Marvell 88E1011 PHY control */
#define MII_M1011_PHY_SPEC_CONTROL		0x10
#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX	0x20
#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX	0x40

/* Marvell 88E1011 PHY status */
#define MII_M1011_PHY_SPEC_STATUS		0x11
#define MII_M1011_PHY_SPEC_STATUS_1000		0x8000
#define MII_M1011_PHY_SPEC_STATUS_100		0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK	0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX	0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED	0x0800

#endif /* __SUNGEM_PHY_H__ */

Lines 145-150 Link Here

(-)linux-2.4.22/drivers/net/tg3.c (+2 lines)
145	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },	145	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
146	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,	146	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
147	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },	147	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
		148	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
		149	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
148	{ 0, }	150	{ 0, }
149	};	151	};
150		152

Lines 474-479 Link Here

(-)linux-2.4.22/drivers/net/tulip/tulip_core.c (+9 lines)
474	} else	474	} else
475	tulip_select_media(dev, 1);	475	tulip_select_media(dev, 1);
476		476
		477	/* check for Apple 100BaseTX card and disable loops */
		478	if ((dev->dev_addr[0] == 0x00) &&
		479	(dev->dev_addr[1] == 0x05) &&
		480	(dev->dev_addr[2] == 0x02) &&
		481	(tp->chip_id == DC21140)) {
		482	outl(0x10f, ioaddr + CSR12);
		483	outl(0x03, ioaddr + CSR12);
		484	}
		485
477	/* Start the chip's Tx to process setup frame. */	486	/* Start the chip's Tx to process setup frame. */
478	tulip_stop_rxtx(tp);	487	tulip_stop_rxtx(tp);
479	barrier();	488	barrier();

Line 0 Link Here

(-)linux-2.4.22/drivers/net/wan/8253x/build (+8 lines)
	1	cc -g -o 8253xcfg -I. -U__KERNEL__ 8253xcfg.c
	2	cc -g -o 8253xspeed -I. -U__KERNEL__ 8253xspeed.c
	3	cc -g -o 8253xmode -I. -U__KERNEL__ 8253xmode.c
	4	cc -g -o 8253xpeer -I. -U__KERNEL__ 8253xpeer.c
	5	cc -g -o eprom9050 -I. -U__KERNEL__ eprom9050.c
	6
	7
	8

Lines 15-20 Link Here

(-)linux-2.4.22/drivers/net/wireless/Config.in (+1 lines)
15	if [ "$CONFIG_PCI" = "y" ]; then	15	if [ "$CONFIG_PCI" = "y" ]; then
16	dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL	16	dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
17	dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL	17	dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
		18	dep_tristate ' Prism II devices connected via a TMD7160 (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18	fi	19	fi
19		20
20	# If Pcmcia is compiled in, offer Pcmcia cards...	21	# If Pcmcia is compiled in, offer Pcmcia cards...

Lines 19-24 Link Here

(-)linux-2.4.22/drivers/net/wireless/Makefile (+1 lines)
19	obj-$(CONFIG_APPLE_AIRPORT) += airport.o	19	obj-$(CONFIG_APPLE_AIRPORT) += airport.o
20	obj-$(CONFIG_PLX_HERMES) += orinoco_plx.o	20	obj-$(CONFIG_PLX_HERMES) += orinoco_plx.o
21	obj-$(CONFIG_PCI_HERMES) += orinoco_pci.o	21	obj-$(CONFIG_PCI_HERMES) += orinoco_pci.o
		22	obj-$(CONFIG_TMD_HERMES) += orinoco_tmd.o
22		23
23	obj-$(CONFIG_AIRO) += airo.o	24	obj-$(CONFIG_AIRO) += airo.o
24	obj-$(CONFIG_AIRO_CS) += airo_cs.o airo.o	25	obj-$(CONFIG_AIRO_CS) += airo_cs.o airo.o

Lines 28-34 Link Here

(-)linux-2.4.22/drivers/pci/pci.c (-5 / +12 lines)
28	#include <asm/page.h>	28	#include <asm/page.h>
29	#include <asm/dma.h> /* isa_dma_bridge_buggy */	29	#include <asm/dma.h> /* isa_dma_bridge_buggy */
30		30
31	#undef DEBUG	31	#define DEBUG
32		32
33	#ifdef DEBUG	33	#ifdef DEBUG
34	#define DBG(x...) printk(x)	34	#define DBG(x...) printk(x)
Lines 1059-1074 Link Here
1059	unsigned int pos, reg, next;	1059	unsigned int pos, reg, next;
1060	u32 l, sz;	1060	u32 l, sz;
1061	struct resource *res;	1061	struct resource *res;
		1062	int is_kl = (dev->device == 0x22 && dev->vendor == 0x106b);
1062		1063
		1064	if (is_kl)
		1065	howmany = 1;
1063	for(pos=0; pos<howmany; pos = next) {	1066	for(pos=0; pos<howmany; pos = next) {
1064	next = pos+1;	1067	next = pos+1;
1065	res = &dev->resource[pos];	1068	res = &dev->resource[pos];
1066	res->name = dev->name;	1069	res->name = dev->name;
1067	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	1070	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
1068	pci_read_config_dword(dev, reg, &l);	1071	pci_read_config_dword(dev, reg, &l);
1069	pci_write_config_dword(dev, reg, ~0);	1072	if (is_kl)
1070	pci_read_config_dword(dev, reg, &sz);	1073	sz = 0x00080000;
1071	pci_write_config_dword(dev, reg, l);	1074	else {
		1075	pci_write_config_dword(dev, reg, ~0);
		1076	pci_read_config_dword(dev, reg, &sz);
		1077	pci_write_config_dword(dev, reg, l);
		1078	}
1072	if (!sz \|\| sz == 0xffffffff)	1079	if (!sz \|\| sz == 0xffffffff)
1073	continue;	1080	continue;
1074	if (l == 0xffffffff)	1081	if (l == 0xffffffff)
Lines 1309-1315 Link Here
1309	if (!pass)	1316	if (!pass)
1310	return max;	1317	return max;
1311	pci_read_config_word(dev, PCI_COMMAND, &cr);	1318	pci_read_config_word(dev, PCI_COMMAND, &cr);
1312	pci_write_config_word(dev, PCI_COMMAND, 0x0000);	1319	//pci_write_config_word(dev, PCI_COMMAND, 0x0000);
1313	pci_write_config_word(dev, PCI_STATUS, 0xffff);	1320	pci_write_config_word(dev, PCI_STATUS, 0xffff);
1314		1321
1315	child = pci_add_new_bus(bus, dev, ++max);	1322	child = pci_add_new_bus(bus, dev, ++max);

Lines 27-39 Link Here

(-)linux-2.4.22/drivers/sound/dmasound/Config.in (-5 / +19 lines)
27	fi	27	fi
28		28
29	# the new dmasound_pmac driver needs access to the i2c bus	29	# the new dmasound_pmac driver needs access to the i2c bus
		30	# and nvram.
30	if [ "$CONFIG_DMASOUND_PMAC" = "y" ] ; then	31	if [ "$CONFIG_DMASOUND_PMAC" = "y" ] ; then
31	define_tristate CONFIG_I2C y	32	if [ "$CONFIG_I2C" != "y" ]; then
32	define_tristate CONFIG_I2C_KEYWEST y	33	define_tristate CONFIG_I2C y
		34	fi
		35	if [ "$CONFIG_I2C_KEYWEST" != "y" ]; then
		36	define_tristate CONFIG_I2C_KEYWEST y
		37	fi
		38	if [ "$CONFIG_NVRAM" != "y" -a "$CONFIG_NVRAM" != "m" ]; then
		39	define_tristate CONFIG_NVRAM y
		40	fi
33	else	41	else
34	if [ "$CONFIG_DMASOUND_PMAC" = "m" ] ; then	42	if [ "$CONFIG_DMASOUND_PMAC" = "m" ] ; then
35	define_tristate CONFIG_I2C m	43	if [ "$CONFIG_I2C" != "y" -a "$CONFIG_I2C" != "m" ]; then
36	define_tristate CONFIG_I2C_KEYWEST m	44	define_tristate CONFIG_I2C m
		45	fi
		46	if [ "$CONFIG_I2C_KEYWEST" != "y" -a "$CONFIG_I2C_KEYWEST" != "m" ]; then
		47	define_tristate CONFIG_I2C_KEYWEST m
		48	fi
		49	if [ "$CONFIG_NVRAM" != "y" -a "$CONFIG_NVRAM" != "m" ]; then
		50	define_tristate CONFIG_NVRAM y
		51	fi
37	fi	52	fi
38	fi	53	fi
39

Lines 13-19 Link Here

(-)linux-2.4.22/drivers/sound/dmasound/Makefile (-1 / +2 lines)
13		13
14	list-multi := dmasound_pmac.o	14	list-multi := dmasound_pmac.o
15		15
16	dmasound_pmac-objs := dmasound_awacs.o trans_16.o tas3001c.o dac3550a.o	16	dmasound_pmac-objs := dmasound_awacs.o trans_16.o dac3550a.o tas_common.o \
		17	tas3001c.o tas3001c_tables.o tas3004.o tas3004_tables.o
17		18
18	obj-$(CONFIG_DMASOUND) += dmasound_core.o	19	obj-$(CONFIG_DMASOUND) += dmasound_core.o
19	obj-$(CONFIG_DMASOUND_ATARI) += dmasound_atari.o	20	obj-$(CONFIG_DMASOUND_ATARI) += dmasound_atari.o





#define RATE_LOW	1	/* HIGH = 48kHz, etc;  LOW = 44.1kHz, etc. */

/*******************/
/* Burgundy values */
/*******************/

#define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)
#define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)

#define DEF_BURGUNDY_ATTENLINEOUT (0xCC)
#define DEF_BURGUNDY_ATTENHP (0xCC)

/*********************/
/* i2s layout values */
/*********************/

#define I2S_REG_INT_CTL			0x00
#define I2S_REG_SERIAL_FORMAT		0x10
#define I2S_REG_CODEC_MSG_OUT		0x20
#define I2S_REG_CODEC_MSG_IN		0x30
#define I2S_REG_FRAME_COUNT		0x40
#define I2S_REG_FRAME_MATCH		0x50
#define I2S_REG_DATAWORD_SIZES		0x60
#define I2S_REG_PEAKLEVEL_SEL		0x70
#define I2S_REG_PEAKLEVEL_IN0		0x80
#define I2S_REG_PEAKLEVEL_IN1		0x90

#endif /* _AWACS_DEFS_H_ */

Lines 45-51 Link Here

(-)linux-2.4.22/drivers/sound/dmasound/dmasound_awacs.c (-261 / +341 lines)
45	* 01/02/2002 [0.7] - BenH	45	* 01/02/2002 [0.7] - BenH
46	* - all sort of minor bits went in since the latest update, I	46	* - all sort of minor bits went in since the latest update, I
47	* bumped the version number for that reason	47	* bumped the version number for that reason
48	*/	48	*
		49	* 07/26/2002 [0.8] - BenH
		50	* - More minor bits since last changelog (I should be more careful
		51	* with those)
		52	* - Support for snapper & better tumbler integration by Toby Sargeant
		53	* - Headphone detect for scremer by Julien Blache
		54	* - More tumbler fixed by Andreas Schwab
		55	*/
49		56
50	/* GENERAL FIXME/TODO: check that the assumptions about what is written to	57	/* GENERAL FIXME/TODO: check that the assumptions about what is written to
51	mac-io is valid for DACA & Tumbler.	58	mac-io is valid for DACA & Tumbler.
Lines 88-97 Link Here
88		95
89	#include "awacs_defs.h"	96	#include "awacs_defs.h"
90	#include "dmasound.h"	97	#include "dmasound.h"
		98	#include "tas3001c.h"
		99	#include "tas3004.h"
		100	#include "tas_common.h"
91		101
92	#define DMASOUND_AWACS_REVISION 0	102	#define DMASOUND_AWACS_REVISION 0
93	#define DMASOUND_AWACS_EDITION 7	103	#define DMASOUND_AWACS_EDITION 7
94		104
		105	#define AWACS_SNAPPER 110 /* fake revision # for snapper */
95	#define AWACS_BURGUNDY 100 /* fake revision # for burgundy */	106	#define AWACS_BURGUNDY 100 /* fake revision # for burgundy */
96	#define AWACS_TUMBLER 90 /* fake revision # for tumbler */	107	#define AWACS_TUMBLER 90 /* fake revision # for tumbler */
97	#define AWACS_DACA 80 /* fake revision # for daca (ibook) */	108	#define AWACS_DACA 80 /* fake revision # for daca (ibook) */
Lines 102-112 Link Here
102	*/	113	*/
103	static int awacs_irq, awacs_tx_irq, awacs_rx_irq;	114	static int awacs_irq, awacs_tx_irq, awacs_rx_irq;
104	static volatile struct awacs_regs *awacs;	115	static volatile struct awacs_regs *awacs;
		116	static volatile u32 *i2s;
105	static volatile struct dbdma_regs awacs_txdma, awacs_rxdma;	117	static volatile struct dbdma_regs awacs_txdma, awacs_rxdma;
106	static int awacs_rate_index;	118	static int awacs_rate_index;
107	static int awacs_subframe;	119	static int awacs_subframe;
108	static int awacs_spkr_vol;	120	static int awacs_spkr_vol;
109	static struct device_node* awacs_node;	121	static struct device_node* awacs_node;
		122	static struct device_node* i2s_node;
110		123
111	static char awacs_name[64];	124	static char awacs_name[64];
112	static int awacs_revision;	125	static int awacs_revision;
Lines 163-168 Link Here
163	static int cd_lev = 0x6363 ; /* 99 % */	176	static int cd_lev = 0x6363 ; /* 99 % */
164	static int line_lev = 0 ;	177	static int line_lev = 0 ;
165		178
		179	static int hdp_connected = 0;
		180
166	/*	181	/*
167	* Stuff for outputting a beep. The values range from -327 to +327	182	* Stuff for outputting a beep. The values range from -327 to +327
168	* so we can multiply by an amplitude in the range 0..100 to get a	183	* so we can multiply by an amplitude in the range 0..100 to get a
Lines 293-311 Link Here
293	extern int daca_enter_sleep(void);	308	extern int daca_enter_sleep(void);
294	extern int daca_leave_sleep(void);	309	extern int daca_leave_sleep(void);
295		310
296	extern int tas_init(void);
297	extern int tas_cleanup(void);
298	extern int tumbler_set_volume(uint left_vol, uint right_vol);
299	extern void tumbler_get_volume(uint * left_vol, uint *right_vol);
300	extern void tumbler_set_treble(int treble);
301	extern void tumbler_get_treble(int *treble);
302	extern void tumbler_set_bass(int bass);
303	extern void tumbler_get_bass(int *bass);
304	extern void tumbler_set_pcm_lvl(int pcm_lvl);
305	extern void tumbler_get_pcm_lvl(int *pcm_lvl);
306	extern int tumbler_enter_sleep(void);
307	extern int tumbler_leave_sleep(void);
308
309	#define TRY_LOCK() \	311	#define TRY_LOCK() \
310	if ((rc = down_interruptible(&dmasound_sem)) != 0) \	312	if ((rc = down_interruptible(&dmasound_sem)) != 0) \
311	return rc;	313	return rc;
Lines 332-338 Link Here
332	}	334	}
333		335
334		336
335	/* AE - TUMBLER START *******************************************************/	337	/* AE - TUMBLER / SNAPPER START **********************************************/
336		338
337		339
338	int gpio_audio_reset, gpio_audio_reset_pol;	340	int gpio_audio_reset, gpio_audio_reset_pol;
Lines 394-410 Link Here
394	return ((pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, gpio_addr, 0) & 0x02) !=0);	396	return ((pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, gpio_addr, 0) & 0x02) !=0);
395	}	397	}
396		398
		399	/*
		400	* Headphone interrupt via GPIO (Tumbler, Snapper, DACA)
		401	*/
397	static void	402	static void
398	headphone_intr(int irq, void devid, struct pt_regs regs)	403	headphone_intr(int irq, void devid, struct pt_regs regs)
399	{	404	{
400	if (read_audio_gpio(gpio_headphone_detect) == gpio_headphone_detect_pol) {	405	if (read_audio_gpio(gpio_headphone_detect) == gpio_headphone_detect_pol) {
401	printk(KERN_INFO "Audio jack plugged, muting speakers.\n");	406	printk(KERN_INFO "Audio jack plugged, muting speakers.\n");
402	write_audio_gpio(gpio_amp_mute, gpio_amp_mute_pol);
403	write_audio_gpio(gpio_headphone_mute, !gpio_headphone_mute_pol);	407	write_audio_gpio(gpio_headphone_mute, !gpio_headphone_mute_pol);
		408	write_audio_gpio(gpio_amp_mute, gpio_amp_mute_pol);
		409	tas_output_device_change(sound_device_id,TAS_OUTPUT_HEADPHONES,0);
404	} else {	410	} else {
405	printk(KERN_INFO "Audio jack unplugged, enabling speakers.\n");	411	printk(KERN_INFO "Audio jack unplugged, enabling speakers.\n");
406	write_audio_gpio(gpio_amp_mute, !gpio_amp_mute_pol);	412	write_audio_gpio(gpio_amp_mute, !gpio_amp_mute_pol);
407	write_audio_gpio(gpio_headphone_mute, gpio_headphone_mute_pol);	413	write_audio_gpio(gpio_headphone_mute, gpio_headphone_mute_pol);
		414	tas_output_device_change(sound_device_id,TAS_OUTPUT_INTERNAL_SPKR,0);
408	}	415	}
409	}	416	}
410		417
Lines 412-418 Link Here
412	/* Initialize tumbler */	419	/* Initialize tumbler */
413		420
414	static int	421	static int
415	awacs_tumbler_init(void)	422	tas_dmasound_init(void)
416	{	423	{
417	setup_audio_gpio(	424	setup_audio_gpio(
418	"audio-hw-reset",	425	"audio-hw-reset",
Lines 469-483 Link Here
469		476
470		477
471	static int	478	static int
472	awacs_tumbler_cleanup(void)	479	tas_dmasound_cleanup(void)
473	{	480	{
474	if (gpio_headphone_irq)	481	if (gpio_headphone_irq)
475	free_irq(gpio_headphone_irq, 0);	482	free_irq(gpio_headphone_irq, 0);
476	return 0;	483	return 0;
477	}	484	}
478		485
		486	/* We don't support 48k yet */
		487	static int tas_freqs[1] = { 44100 } ;
		488	static int tas_freqs_ok[1] = { 1 } ;
479		489
480	/* AE - TUMBLER END *******************************************************/	490	/* don't know what to do really - just have to leave it where
		491	* OF left things
		492	*/
		493
		494	static int
		495	tas_set_frame_rate(void)
		496	{
		497	if (i2s) {
		498	out_le32(i2s + (I2S_REG_SERIAL_FORMAT >> 2), 0x41190000);
		499	out_le32(i2s + (I2S_REG_DATAWORD_SIZES >> 2), 0x02000200);
		500	}
		501	dmasound.hard.speed = 44100 ;
		502	awacs_rate_index = 0 ;
		503	return 44100 ;
		504	}
		505
		506	static int
		507	tas_mixer_ioctl(u_int cmd, u_long arg)
		508	{
		509	int data;
		510	int rc;
		511
		512	rc=tas_device_ioctl(cmd, arg);
		513	if (rc != -EINVAL) {
		514	return rc;
		515	}
		516
		517	if ((cmd & ~0xff) == MIXER_WRITE(0) &&
		518	tas_supported_mixers() & (1<<(cmd & 0xff))) {
		519	rc = get_user(data, (int *)(arg));
		520	if (rc<0) return rc;
		521	tas_set_mixer_level(cmd & 0xff, data);
		522	tas_get_mixer_level(cmd & 0xff, &data);
		523	return ioctl_return2((int *)(arg), data);
		524	}
		525	if ((cmd & ~0xff) == MIXER_READ(0) &&
		526	tas_supported_mixers() & (1<<(cmd & 0xff))) {
		527	tas_get_mixer_level(cmd & 0xff, &data);
		528	return ioctl_return2((int *)(arg), data);
		529	}
		530
		531	switch(cmd) {
		532	case SOUND_MIXER_READ_DEVMASK:
		533	data = tas_supported_mixers() \| SOUND_MASK_SPEAKER;
		534	rc = IOCTL_OUT(arg, data);
		535	break;
		536	case SOUND_MIXER_READ_STEREODEVS:
		537	data = tas_stereo_mixers();
		538	rc = IOCTL_OUT(arg, data);
		539	break;
		540	case SOUND_MIXER_READ_CAPS:
		541	rc = IOCTL_OUT(arg, 0);
		542	break;
		543	case SOUND_MIXER_READ_RECMASK:
		544	data = 0;
		545	rc = IOCTL_OUT(arg, data);
		546	break;
		547	case SOUND_MIXER_READ_RECSRC:
		548	data = 0;
		549	rc = IOCTL_OUT(arg, data);
		550	break;
		551	case SOUND_MIXER_WRITE_RECSRC:
		552	IOCTL_IN(arg, data);
		553	data =0;
		554	rc = IOCTL_OUT(arg, data);
555	break;
556	case SOUND_MIXER_WRITE_SPEAKER: /* really bell volume */
557	IOCTL_IN(arg, data);
558	beep_vol = data & 0xff;
559	/* fall through */
560	case SOUND_MIXER_READ_SPEAKER:
561	rc = IOCTL_OUT(arg, (beep_vol<<8) \| beep_vol);
562	break;
563	case SOUND_MIXER_OUTMASK:
564	case SOUND_MIXER_OUTSRC:
565	default:
566	rc = -EINVAL;
567	}
568
569	return rc;
570	}
571
572	static void __init
573	tas_init_frame_rates(unsigned int *prop, unsigned int l)
574	{
575	int i ;
576	if (prop) {
577	for (i=0; i<1; i++)
578	tas_freqs_ok[i] = 0;
579	for (l /= sizeof(int); l > 0; --l) {
580	unsigned int r = *prop++;
581	/* Apple 'Fixed' format */
582	if (r >= 0x10000)
583	r >>= 16;
584	for (i = 0; i < 1; ++i) {
585	if (r == tas_freqs[i]) {
586	tas_freqs_ok[i] = 1;
587	break;
588	}
589	}
590	}
591	}
592	/* else we assume that all the rates are available */
593	}
594
595
596	/* AE - TUMBLER / SNAPPER END **********************************************/
481		597
482		598
483		599
Lines 509-516 Link Here
509		625
510	static int __init PMacIrqInit(void)	626	static int __init PMacIrqInit(void)
511	{	627	{
512	if (request_irq(awacs_irq, pmac_awacs_intr, 0, "Built-in Sound misc", 0)	628	if (awacs)
513	\|\| request_irq(awacs_tx_irq, pmac_awacs_tx_intr, 0, "Built-in Sound out", 0)	629	if (request_irq(awacs_irq, pmac_awacs_intr, 0, "Built-in Sound misc", 0))
		630	return 0;
		631	if (request_irq(awacs_tx_irq, pmac_awacs_tx_intr, 0, "Built-in Sound out", 0)
514	\|\| request_irq(awacs_rx_irq, pmac_awacs_rx_intr, 0, "Built-in Sound in", 0))	632	\|\| request_irq(awacs_rx_irq, pmac_awacs_rx_intr, 0, "Built-in Sound in", 0))
515	return 0;	633	return 0;
516	return 1;	634	return 1;
Lines 523-545 Link Here
523	DBDMA_DO_STOP(awacs_txdma);	641	DBDMA_DO_STOP(awacs_txdma);
524	DBDMA_DO_STOP(awacs_rxdma);	642	DBDMA_DO_STOP(awacs_rxdma);
525		643
526	/* disable interrupts from awacs interface */	644	if (awacs)
527	out_le32(&awacs->control, in_le32(&awacs->control) & 0xfff);	645	/* disable interrupts from awacs interface */
528		646	out_le32(&awacs->control, in_le32(&awacs->control) & 0xfff);
		647
529	/* Switch off the sound clock */	648	/* Switch off the sound clock */
530	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 0);	649	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 0);
531	/* Make sure proper bits are set on pismo & tipb */	650	/* Make sure proper bits are set on pismo & tipb */
532	if (machine_is_compatible("PowerBook3,1") \|\|	651	if ((machine_is_compatible("PowerBook3,1") \|\|
533	machine_is_compatible("PowerBook3,2")) {	652	machine_is_compatible("PowerBook3,2")) && awacs) {
534	awacs_reg[1] \|= MASK_PAROUT0 \| MASK_PAROUT1;	653	awacs_reg[1] \|= MASK_PAROUT0 \| MASK_PAROUT1;
535	awacs_write(MASK_ADDR1 \| awacs_reg[1]);	654	awacs_write(MASK_ADDR1 \| awacs_reg[1]);
536	wait_ms(200);	655	wait_ms(200);
537	}	656	}
538	free_irq(awacs_irq, 0);	657	if (awacs)
		658	free_irq(awacs_irq, 0);
539	free_irq(awacs_tx_irq, 0);	659	free_irq(awacs_tx_irq, 0);
540	free_irq(awacs_rx_irq, 0);	660	free_irq(awacs_rx_irq, 0);
541	/* all OF versions I've seen use this value */	661
542	iounmap((void *)awacs);	662	if (awacs)
		663	iounmap((void *)awacs);
		664	if (i2s)
		665	iounmap((void *)i2s);
543	iounmap((void *)awacs_txdma);	666	iounmap((void *)awacs_txdma);
544	iounmap((void *)awacs_rxdma);	667	iounmap((void *)awacs_rxdma);
545		668
Lines 555-561 Link Here
555	kfree(beep_dbdma_cmd_space);	678	kfree(beep_dbdma_cmd_space);
556	if (beep_buf) {	679	if (beep_buf) {
557	kfree(beep_buf);	680	kfree(beep_buf);
		681	#ifdef CONFIG_VT
558	kd_mksound = orig_mksound;	682	kd_mksound = orig_mksound;
		683	#endif
559	}	684	}
560	#ifdef CONFIG_PMAC_PBOOK	685	#ifdef CONFIG_PMAC_PBOOK
561	pmu_unregister_sleep_notifier(&awacs_sleep_notifier);	686	pmu_unregister_sleep_notifier(&awacs_sleep_notifier);
Lines 569-594 Link Here
569	DBDMA_DO_STOP(awacs_txdma);	694	DBDMA_DO_STOP(awacs_txdma);
570	}	695	}
571		696
572	static int tumbler_freqs[2] = { 48000, 44100 } ;
573	static int tumbler_freqs_ok[2] = { 1, 1 } ;
574
575	/* don't know what to do really - just have to leave it where
576	* OF left things
577	*/
578
579	static int tumbler_set_frame_rate(void)
580	{
581	dmasound.hard.speed = 44100 ;
582	awacs_rate_index = 0 ;
583	return 44100 ;
584	}
585
586	/* don't know what to do really - just have to leave it where	697	/* don't know what to do really - just have to leave it where
587	* OF left things	698	* OF left things
588	*/	699	*/
589		700
590	static int daca_set_frame_rate(void)	701	static int daca_set_frame_rate(void)
591	{	702	{
		703	if (i2s) {
		704	out_le32(i2s + (I2S_REG_SERIAL_FORMAT >> 2), 0x41190000);
		705	out_le32(i2s + (I2S_REG_DATAWORD_SIZES >> 2), 0x02000200);
		706	}
592	dmasound.hard.speed = 44100 ;	707	dmasound.hard.speed = 44100 ;
593	awacs_rate_index = 0 ;	708	awacs_rate_index = 0 ;
594	return 44100 ;	709	return 44100 ;
Lines 599-605 Link Here
599	};	714	};
600	static int awacs_freqs_ok[8] = { 1, 1, 1, 1, 1, 1, 1, 1 };	715	static int awacs_freqs_ok[8] = { 1, 1, 1, 1, 1, 1, 1, 1 };
601		716
602	static int awacs_set_frame_rate(int desired, int catch_r)	717	static int
		718	awacs_set_frame_rate(int desired, int catch_r)
603	{	719	{
604	int tolerance, i = 8 ;	720	int tolerance, i = 8 ;
605	/*	721	/*
Lines 623-635 Link Here
623	return dmasound.hard.speed;	739	return dmasound.hard.speed;
624	}	740	}
625		741
626	static int burgundy_frame_rates = 1 ;	742	static int
627	static int burgundy_set_frame_rate(void)	743	burgundy_set_frame_rate(void)
628	{	744	{
629	#ifdef DEBUG_DMASOUND
630	if (burgundy_frame_rates > 1)
631	printk("dmasound_pmac: warning Burgundy had more than one frame rate\n");
632	#endif
633	awacs_rate_index = 0 ;	745	awacs_rate_index = 0 ;
634	awacs_reg[1] = (awacs_reg[1] & ~MASK_SAMPLERATE) ;	746	awacs_reg[1] = (awacs_reg[1] & ~MASK_SAMPLERATE) ;
635	/* XXX disable error interrupt on burgundy for now */	747	/* XXX disable error interrupt on burgundy for now */
Lines 637-660 Link Here
637	return 44100 ;	749	return 44100 ;
638	}	750	}
639		751
640	static int set_frame_rate(int desired, int catch_r)	752	static int
		753	set_frame_rate(int desired, int catch_r)
641	{	754	{
642	switch (awacs_revision) {	755	switch (awacs_revision) {
643	case AWACS_BURGUNDY:	756	case AWACS_BURGUNDY:
644	dmasound.hard.speed =	757	dmasound.hard.speed = burgundy_set_frame_rate();
645	burgundy_set_frame_rate();
646	break ;	758	break ;
647	case AWACS_TUMBLER:	759	case AWACS_TUMBLER:
648	dmasound.hard.speed =	760	case AWACS_SNAPPER:
649	tumbler_set_frame_rate();	761	dmasound.hard.speed = tas_set_frame_rate();
650	break ;	762	break ;
651	case AWACS_DACA:	763	case AWACS_DACA:
652	dmasound.hard.speed =	764	dmasound.hard.speed =
653	daca_set_frame_rate();	765	daca_set_frame_rate();
654	break ;	766	break ;
655	default:	767	default:
656	dmasound.hard.speed =	768	dmasound.hard.speed = awacs_set_frame_rate(desired,
657	awacs_set_frame_rate(desired, catch_r);	769	catch_r);
658	break ;	770	break ;
659	}	771	}
660	return dmasound.hard.speed ;	772	return dmasound.hard.speed ;
Lines 704-714 Link Here
704	dmasound.trans_write = &transAwacsExpand;	816	dmasound.trans_write = &transAwacsExpand;
705	dmasound.trans_read = &transAwacsNormalRead;	817	dmasound.trans_read = &transAwacsNormalRead;
706		818
707	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))	819	if (awacs) {
708	out_le32(&awacs->byteswap, BS_VAL);	820	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))
709	else	821	out_le32(&awacs->byteswap, BS_VAL);
710	out_le32(&awacs->byteswap, 0);	822	else
711		823	out_le32(&awacs->byteswap, 0);
		824	}
		825
712	expand_bal = -dmasound.soft.speed;	826	expand_bal = -dmasound.soft.speed;
713	}	827	}
714		828
Lines 793-799 Link Here
793		907
794	static int PMacSetVolume(int volume)	908	static int PMacSetVolume(int volume)
795	{	909	{
796	return awacs_volume_setter(volume, 2, MASK_AMUTE, 6);	910	printk(KERN_WARNING "Bogus call to PMacSetVolume !\n");
		911	return 0;
		912	}
		913
		914	static void awacs_setup_for_beep(int speed)
		915	{
		916	out_le32(&awacs->control,
		917	(in_le32(&awacs->control) & ~0x1f00)
		918	\| ((speed > 0 ? speed : awacs_rate_index) << 8));
		919
		920	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE) && speed == -1)
		921	out_le32(&awacs->byteswap, BS_VAL);
		922	else
		923	out_le32(&awacs->byteswap, 0);
797	}	924	}
798		925
799	static void __PMacPlay(void)	926	static void __PMacPlay(void)
Lines 816-830 Link Here
816	out_le32(&awacs_txdma->control, (RUN\|PAUSE\|FLUSH\|WAKE) << 16);	943	out_le32(&awacs_txdma->control, (RUN\|PAUSE\|FLUSH\|WAKE) << 16);
817	while ( (in_le32(&awacs_txdma->status) & RUN) && count--)	944	while ( (in_le32(&awacs_txdma->status) & RUN) && count--)
818	udelay(1);	945	udelay(1);
819	/* FIXME: check that this is OK for other chip sets */	946	if (awacs)
820	out_le32(&awacs->control,	947	awacs_setup_for_beep(-1);
821	(in_le32(&awacs->control) & ~0x1f00)
822	\| (awacs_rate_index << 8));
823
824	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))
825	out_le32(&awacs->byteswap, BS_VAL);
826	else
827	out_le32(&awacs->byteswap, 0);
828	out_le32(&awacs_txdma->cmdptr,	948	out_le32(&awacs_txdma->cmdptr,
829	virt_to_bus(&(awacs_tx_cmds[next_frg])));	949	virt_to_bus(&(awacs_tx_cmds[next_frg])));
830		950
Lines 925-930 Link Here
925	{	1045	{
926	int i = write_sq.front;	1046	int i = write_sq.front;
927	int stat;	1047	int stat;
		1048	int i_nowrap = write_sq.front;
928	volatile struct dbdma_cmd *cp;	1049	volatile struct dbdma_cmd *cp;
929	/* != 0 when we are dealing with a DEAD xfer */	1050	/* != 0 when we are dealing with a DEAD xfer */
930	static int emergency_in_use = 0 ;	1051	static int emergency_in_use = 0 ;
Lines 981-986 Link Here
981	emergency_in_use = 0 ; /* done that */	1102	emergency_in_use = 0 ; /* done that */
982	--write_sq.count;	1103	--write_sq.count;
983	--write_sq.active;	1104	--write_sq.active;
		1105	i_nowrap++;
984	if (++i >= write_sq.max_count)	1106	if (++i >= write_sq.max_count)
985	i = 0;	1107	i = 0;
986	}	1108	}
Lines 993-999 Link Here
993	}	1115	}
994		1116
995	/* if we used some data up then wake the writer to supply some more*/	1117	/* if we used some data up then wake the writer to supply some more*/
996	if (i != write_sq.front)	1118	if (i_nowrap != write_sq.front)
997	WAKE_UP(write_sq.action_queue);	1119	WAKE_UP(write_sq.action_queue);
998	write_sq.front = i;	1120	write_sq.front = i;
999		1121
Lines 1090-1098 Link Here
1090	pmac_awacs_intr(int irq, void devid, struct pt_regs regs)	1212	pmac_awacs_intr(int irq, void devid, struct pt_regs regs)
1091	{	1213	{
1092	int ctrl = in_le32(&awacs->control);	1214	int ctrl = in_le32(&awacs->control);
		1215	int status = in_le32(&awacs->codec_stat);
		1216	int r1;
1093		1217
1094	if (ctrl & MASK_PORTCHG) {	1218	if (ctrl & MASK_PORTCHG) {
1095	/* do something when headphone is plugged/unplugged? */	1219	/* tested on Screamer, should work on others too */
		1220	if (awacs_revision == AWACS_SCREAMER) {
		1221	if (((status & MASK_HDPCONN) >> 3) && (hdp_connected == 0)) {
		1222	hdp_connected = 1;
		1223
		1224	r1 = awacs_reg[1] \| MASK_SPKMUTE;
		1225	awacs_reg[1] = r1;
		1226	awacs_write(r1 \| MASK_ADDR_MUTE);
		1227	} else if (((status & MASK_HDPCONN) >> 3 == 0) && (hdp_connected == 1)) {
		1228	hdp_connected = 0;
		1229
		1230	r1 = awacs_reg[1] & ~MASK_SPKMUTE;
		1231	awacs_reg[1] = r1;
		1232	awacs_write(r1 \| MASK_ADDR_MUTE);
		1233	}
		1234	}
1096	}	1235	}
1097	if (ctrl & MASK_CNTLERR) {	1236	if (ctrl & MASK_CNTLERR) {
1098	int err = (in_le32(&awacs->codec_stat) & MASK_ERRCODE) >> 16;	1237	int err = (in_le32(&awacs->codec_stat) & MASK_ERRCODE) >> 16;
Lines 1108-1114 Link Here
1108	awacs_write(int val)	1247	awacs_write(int val)
1109	{	1248	{
1110	int count = 300 ;	1249	int count = 300 ;
1111	if (awacs_revision >= AWACS_DACA)	1250	if (awacs_revision >= AWACS_DACA \|\| !awacs)
1112	return ;	1251	return ;
1113		1252
1114	while ((in_le32(&awacs->codec_ctrl) & MASK_NEWECMD) && count--)	1253	while ((in_le32(&awacs->codec_ctrl) & MASK_NEWECMD) && count--)
Lines 1131-1144 Link Here
1131	out_le32(&awacs_txdma->control, (RUN\|PAUSE\|FLUSH\|WAKE) << 16);	1270	out_le32(&awacs_txdma->control, (RUN\|PAUSE\|FLUSH\|WAKE) << 16);
1132	while ((in_le32(&awacs_txdma->status) & RUN) && count--)	1271	while ((in_le32(&awacs_txdma->status) & RUN) && count--)
1133	udelay(1);	1272	udelay(1);
1134	/* FIXME: check this is OK for DACA, Tumbler */	1273	if (awacs)
1135	out_le32(&awacs->control,	1274	awacs_setup_for_beep(-1);
1136	(in_le32(&awacs->control) & ~0x1f00)
1137	\| (awacs_rate_index << 8));
1138	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))
1139	out_le32(&awacs->byteswap, BS_VAL);
1140	else
1141	out_le32(&awacs->byteswap, 0);
1142	beep_playing = 0;	1275	beep_playing = 0;
1143	}	1276	}
1144	restore_flags(flags);	1277	restore_flags(flags);
Lines 1233-1243 Link Here
1233	out_le32(&awacs_txdma->control, (RUN\|WAKE\|FLUSH\|PAUSE) << 16);	1366	out_le32(&awacs_txdma->control, (RUN\|WAKE\|FLUSH\|PAUSE) << 16);
1234	while ((in_le32(&awacs_txdma->status) & RUN) && count--)	1367	while ((in_le32(&awacs_txdma->status) & RUN) && count--)
1235	udelay(1); /* timeout > 2 samples at lowest rate*/	1368	udelay(1); /* timeout > 2 samples at lowest rate*/
1236	/* FIXME: check this is OK on DACA, Tumbler */	1369	if (awacs)
1237	out_le32(&awacs->control,	1370	awacs_setup_for_beep(beep_speed);
1238	(in_le32(&awacs->control) & ~0x1f00)
1239	\| (beep_speed << 8));
1240	out_le32(&awacs->byteswap, 0); /* force BE */
1241	out_le32(&awacs_txdma->cmdptr, virt_to_bus(beep_dbdma_cmd));	1371	out_le32(&awacs_txdma->cmdptr, virt_to_bus(beep_dbdma_cmd));
1242	(void)in_le32(&awacs_txdma->status);	1372	(void)in_le32(&awacs_txdma->status);
1243	out_le32(&awacs_txdma->control, RUN \| (RUN << 16));	1373	out_le32(&awacs_txdma->control, RUN \| (RUN << 16));
Lines 1263-1272 Link Here
1263	awacs_write(awacs_reg[1] + MASK_ADDR1);	1393	awacs_write(awacs_reg[1] + MASK_ADDR1);
1264	awacs_write(awacs_reg[7] + MASK_ADDR7);	1394	awacs_write(awacs_reg[7] + MASK_ADDR7);
1265	}	1395	}
1266	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))	1396	if (awacs) {
1267	out_le32(&awacs->byteswap, BS_VAL);	1397	if (hw_can_byteswap && (dmasound.hard.format == AFMT_S16_LE))
1268	else	1398	out_le32(&awacs->byteswap, BS_VAL);
1269	out_le32(&awacs->byteswap, 0);	1399	else
		1400	out_le32(&awacs->byteswap, 0);
		1401	}
1270	}	1402	}
1271		1403
1272	#ifdef CONFIG_PMAC_PBOOK	1404	#ifdef CONFIG_PMAC_PBOOK
Lines 1293-1301 Link Here
1293	/* stop rx - if going - a bit of a daft user... but */	1425	/* stop rx - if going - a bit of a daft user... but */
1294	out_le32(&awacs_rxdma->control, (RUN\|WAKE\|FLUSH << 16));	1426	out_le32(&awacs_rxdma->control, (RUN\|WAKE\|FLUSH << 16));
1295	/* deny interrupts */	1427	/* deny interrupts */
		1428	if (awacs)
		1429	disable_irq(awacs_irq);
		1430	disable_irq(awacs_tx_irq);
		1431	disable_irq(awacs_rx_irq);
		1432	/* Chip specific sleep code */
1296	switch (awacs_revision) {	1433	switch (awacs_revision) {
1297	case AWACS_TUMBLER:	1434	case AWACS_TUMBLER:
1298	tumbler_enter_sleep(); /* Stub for now */	1435	case AWACS_SNAPPER:
		1436	write_audio_gpio(gpio_headphone_mute, gpio_headphone_mute_pol);
		1437	write_audio_gpio(gpio_amp_mute, gpio_amp_mute_pol);
		1438	tas_enter_sleep();
		1439	write_audio_gpio(gpio_audio_reset, gpio_audio_reset_pol);
1299	break ;	1440	break ;
1300	case AWACS_DACA:	1441	case AWACS_DACA:
1301	daca_enter_sleep();	1442	daca_enter_sleep();
Lines 1308-1324 Link Here
1308	out_le32(&awacs->control, 0x11) ;	1449	out_le32(&awacs->control, 0x11) ;
1309	break ;	1450	break ;
1310	}	1451	}
1311	disable_irq(awacs_irq);
1312	disable_irq(awacs_tx_irq);
1313	disable_irq(awacs_rx_irq);
1314	/* Disable sound clock */	1452	/* Disable sound clock */
1315	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 0);	1453	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 0);
1316	/* According to Darwin, we do that after turning off the sound	1454	/* According to Darwin, we do that after turning off the sound
1317	* chip clock. All this will have to be cleaned up once we properly	1455	* chip clock. All this will have to be cleaned up once we properly
1318	* parse the OF sound-objects	1456	* parse the OF sound-objects
1319	*/	1457	*/
1320	if (machine_is_compatible("PowerBook3,1") \|\|	1458	if ((machine_is_compatible("PowerBook3,1") \|\|
1321	machine_is_compatible("PowerBook3,2")) {	1459	machine_is_compatible("PowerBook3,2")) && awacs) {
1322	awacs_reg[1] \|= MASK_PAROUT0 \| MASK_PAROUT1;	1460	awacs_reg[1] \|= MASK_PAROUT0 \| MASK_PAROUT1;
1323	awacs_write(MASK_ADDR1 \| awacs_reg[1]);	1461	awacs_write(MASK_ADDR1 \| awacs_reg[1]);
1324	wait_ms(200);	1462	wait_ms(200);
Lines 1327-1334 Link Here
1327	case PBOOK_WAKE:	1465	case PBOOK_WAKE:
1328	/* Enable sound clock */	1466	/* Enable sound clock */
1329	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 1);	1467	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, awacs_node, 0, 1);
1330	if (machine_is_compatible("PowerBook3,1") \|\|	1468	if ((machine_is_compatible("PowerBook3,1") \|\|
1331	machine_is_compatible("PowerBook3,2")) {	1469	machine_is_compatible("PowerBook3,2")) && awacs) {
1332	wait_ms(100);	1470	wait_ms(100);
1333	awacs_reg[1] &= ~(MASK_PAROUT0 \| MASK_PAROUT1);	1471	awacs_reg[1] &= ~(MASK_PAROUT0 \| MASK_PAROUT1);
1334	awacs_write(MASK_ADDR1 \| awacs_reg[1]);	1472	awacs_write(MASK_ADDR1 \| awacs_reg[1]);
Lines 1338-1345 Link Here
1338	/* restore settings */	1476	/* restore settings */
1339	switch (awacs_revision) {	1477	switch (awacs_revision) {
1340	case AWACS_TUMBLER:	1478	case AWACS_TUMBLER:
		1479	case AWACS_SNAPPER:
		1480	write_audio_gpio(gpio_headphone_mute, gpio_headphone_mute_pol);
		1481	write_audio_gpio(gpio_amp_mute, gpio_amp_mute_pol);
		1482	write_audio_gpio(gpio_audio_reset, gpio_audio_reset_pol);
		1483	wait_ms(100);
		1484	write_audio_gpio(gpio_audio_reset, !gpio_audio_reset_pol);
		1485	wait_ms(150);
		1486	tas_leave_sleep(); /* Stub for now */
1341	headphone_intr(0,0,0);	1487	headphone_intr(0,0,0);
1342	tumbler_leave_sleep(); /* Stub for now */
1343	break;	1488	break;
1344	case AWACS_DACA:	1489	case AWACS_DACA:
1345	wait_ms(10); /* Check this !!! */	1490	wait_ms(10); /* Check this !!! */
Lines 1354-1370 Link Here
1354	break ;	1499	break ;
1355	}	1500	}
1356	/* Recalibrate chip */	1501	/* Recalibrate chip */
1357	if (awacs_revision == AWACS_SCREAMER)	1502	if (awacs_revision == AWACS_SCREAMER && awacs)
1358	awacs_recalibrate();	1503	awacs_recalibrate();
1359	/* Make sure dma is stopped */	1504	/* Make sure dma is stopped */
1360	PMacSilence();	1505	PMacSilence();
1361	enable_irq(awacs_irq);	1506	if (awacs)
		1507	enable_irq(awacs_irq);
1362	enable_irq(awacs_tx_irq);	1508	enable_irq(awacs_tx_irq);
1363	enable_irq(awacs_rx_irq);	1509	enable_irq(awacs_rx_irq);
1364	/* OK, allow ints back again */	1510	if (awacs) {
1365	out_le32(&awacs->control, MASK_IEPC	1511	/* OK, allow ints back again */
1366	\| (awacs_rate_index << 8) \| 0x11	1512	out_le32(&awacs->control, MASK_IEPC
1367	\| (awacs_revision < AWACS_DACA ? MASK_IEE: 0));	1513	\| (awacs_rate_index << 8) \| 0x11
		1514	\| (awacs_revision < AWACS_DACA ? MASK_IEE: 0));
		1515	}
1368	if (macio_base && is_pbook_g3) {	1516	if (macio_base && is_pbook_g3) {
1369	/* FIXME: should restore the setup we had...*/	1517	/* FIXME: should restore the setup we had...*/
1370	out_8(macio_base + 0x37, 3);	1518	out_8(macio_base + 0x37, 3);
Lines 1952-1958 Link Here
1952	case SOUND_MIXER_READ_SPEAKER:	2100	case SOUND_MIXER_READ_SPEAKER:
1953	data = awacs_burgundy_rcb(MASK_ADDR_BURGUNDY_ATTENSPEAKER);	2101	data = awacs_burgundy_rcb(MASK_ADDR_BURGUNDY_ATTENSPEAKER);
1954	data = (((data & 0xf)100)/16) + ((((data>>4)100)/16)<<8);	2102	data = (((data & 0xf)100)/16) + ((((data>>4)100)/16)<<8);
1955	rc = IOCTL_OUT(arg, ~data);	2103	rc = IOCTL_OUT(arg, (~data) & 0x0000ffff);
1956	break;	2104	break;
1957	case SOUND_MIXER_WRITE_ALTPCM: /* really bell volume */	2105	case SOUND_MIXER_WRITE_ALTPCM: /* really bell volume */
1958	IOCTL_IN(arg, data);	2106	IOCTL_IN(arg, data);
Lines 2007-2095 Link Here
2007	return rc;	2155	return rc;
2008	}	2156	}
2009		2157
2010	static int tumbler_mixer_ioctl(u_int cmd, u_long arg)
2011	{
2012	int data;
2013	int rc;
2014
2015	/* We are, we are, we are... Tumbler (and very dumb) */
2016	/* Ok, we're not THAT dumb anymore, but still pretty dumb :-) */
2017
2018	switch(cmd) {
2019	case SOUND_MIXER_READ_DEVMASK:
2020	data = SOUND_MASK_VOLUME \| SOUND_MASK_ALTPCM \|
2021	SOUND_MASK_BASS \| SOUND_MASK_TREBLE \|
2022	SOUND_MASK_PCM;
2023	rc = IOCTL_OUT(arg, data);
2024	break;
2025	case SOUND_MIXER_READ_RECMASK:
2026	data = 0;
2027	rc = IOCTL_OUT(arg, data);
2028	break;
2029	case SOUND_MIXER_READ_RECSRC:
2030	data = 0;
2031	rc = IOCTL_OUT(arg, data);
2032	break;
2033	case SOUND_MIXER_WRITE_RECSRC:
2034	IOCTL_IN(arg, data);
2035	data =0;
2036	rc = IOCTL_OUT(arg, data);
2037	break;
2038	case SOUND_MIXER_READ_STEREODEVS:
2039	data = SOUND_MASK_VOLUME \| SOUND_MASK_PCM;
2040	rc = IOCTL_OUT(arg, data);
2041	break;
2042	case SOUND_MIXER_READ_CAPS:
2043	rc = IOCTL_OUT(arg, 0);
2044	break;
2045	case SOUND_MIXER_WRITE_BASS:
2046	IOCTL_IN(arg, data);
2047	tumbler_set_bass(data);
2048	/* Fall through */
2049	case SOUND_MIXER_READ_BASS:
2050	tumbler_get_bass(&data);
2051	rc = IOCTL_OUT(arg, data);
2052	break;
2053	case SOUND_MIXER_WRITE_TREBLE:
2054	IOCTL_IN(arg, data);
2055	tumbler_set_treble(data);
2056	/* Fall through */
2057	case SOUND_MIXER_READ_TREBLE:
2058	tumbler_get_treble(&data);
2059	rc = IOCTL_OUT(arg, data);
2060	break;
2061	case SOUND_MIXER_WRITE_PCM:
2062	IOCTL_IN(arg, data);
2063	tumbler_set_pcm_lvl(data);
2064	/* Fall through */
2065	case SOUND_MIXER_READ_PCM:
2066	tumbler_get_pcm_lvl(&data);
2067	IOCTL_OUT(arg, data);
2068	break;
2069	case SOUND_MIXER_WRITE_VOLUME:
2070	IOCTL_IN(arg, data);
2071	tumbler_set_volume(data, data);
2072	/* Fall through */
2073	case SOUND_MIXER_READ_VOLUME:
2074	tumbler_get_volume(& data, &data);
2075	rc = IOCTL_OUT(arg, data);
2076	break;
2077	case SOUND_MIXER_WRITE_ALTPCM: /* really bell volume */
2078	IOCTL_IN(arg, data);
2079	beep_vol = data & 0xff;
2080	/* fall through */
2081	case SOUND_MIXER_READ_ALTPCM:
2082	rc = IOCTL_OUT(arg, beep_vol);
2083	break;
2084	case SOUND_MIXER_OUTMASK:
2085	case SOUND_MIXER_OUTSRC:
2086	default:
2087	rc = -EINVAL;
2088	}
2089
2090	return rc;
2091	}
2092
2093	static int daca_mixer_ioctl(u_int cmd, u_long arg)	2158	static int daca_mixer_ioctl(u_int cmd, u_long arg)
2094	{	2159	{
2095	int data;	2160	int data;
Lines 2154-2160 Link Here
2154	rc = daca_mixer_ioctl(cmd, arg);	2219	rc = daca_mixer_ioctl(cmd, arg);
2155	break;	2220	break;
2156	case AWACS_TUMBLER:	2221	case AWACS_TUMBLER:
2157	rc = tumbler_mixer_ioctl(cmd, arg);	2222	case AWACS_SNAPPER:
		2223	rc = tas_mixer_ioctl(cmd, arg);
2158	break ;	2224	break ;
2159	default: /* ;-)) */	2225	default: /* ;-)) */
2160	rc = awacs_mixer_ioctl(cmd, arg);	2226	rc = awacs_mixer_ioctl(cmd, arg);
Lines 2171-2177 Link Here
2171	case AWACS_TUMBLER:	2237	case AWACS_TUMBLER:
2172	printk("AE-Init tumbler mixer\n");	2238	printk("AE-Init tumbler mixer\n");
2173	break ;	2239	break ;
2174		2240	case AWACS_SNAPPER:
		2241	printk("AE-Init snapper mixer\n");
		2242	break ;
2175	case AWACS_DACA:	2243	case AWACS_DACA:
2176	case AWACS_BURGUNDY:	2244	case AWACS_BURGUNDY:
2177	break ; /* don't know yet */	2245	break ; /* don't know yet */
Lines 2362-2373 Link Here
2362	len += sprintf(b,"44100 ") ;	2430	len += sprintf(b,"44100 ") ;
2363	break ;	2431	break ;
2364	case AWACS_TUMBLER:	2432	case AWACS_TUMBLER:
2365	for (i=0; i<2; i++){	2433	case AWACS_SNAPPER:
2366	if (tumbler_freqs_ok[i])	2434	for (i=0; i<1; i++){
2367	len += sprintf(b+len,"%d ", tumbler_freqs[i]) ;	2435	if (tas_freqs_ok[i])
		2436	len += sprintf(b+len,"%d ", tas_freqs[i]) ;
2368	}	2437	}
2369	break ;	2438	break ;
2370
2371	case AWACS_AWACS:	2439	case AWACS_AWACS:
2372	case AWACS_SCREAMER:	2440	case AWACS_SCREAMER:
2373	default:	2441	default:
Lines 2469-2476 Link Here
2469	code that looks for chip properties knows how to go about it.	2537	code that looks for chip properties knows how to go about it.
2470	*/	2538	*/
2471		2539
2472	static struct device_node	2540	static struct device_node* __init
2473	__init *get_snd_io_node(void)	2541	get_snd_io_node(void)
2474	{	2542	{
2475	struct device_node *np = NULL;	2543	struct device_node *np = NULL;
2476		2544
Lines 2491-2497 Link Here
2491	* this seems to be what iBooks (& Tumbler) have.	2559	* this seems to be what iBooks (& Tumbler) have.
2492	*/	2560	*/
2493	if (np == NULL)	2561	if (np == NULL)
2494	np = find_devices("i2s-a");	2562	np = i2s_node = find_devices("i2s-a");
2495		2563
2496	/* if we didn't find this - perhaps we are on an early model	2564	/* if we didn't find this - perhaps we are on an early model
2497	* which _only_ has an 'awacs' node	2565	* which _only_ has an 'awacs' node
Lines 2511-2518 Link Here
2511	we have to deduce the info other ways for these.	2579	we have to deduce the info other ways for these.
2512	*/	2580	*/
2513		2581
2514	static struct device_node	2582	static struct device_node* __init
2515	__init get_snd_info_node(struct device_node io)	2583	get_snd_info_node(struct device_node *io)
2516	{	2584	{
2517	struct device_node *info;	2585	struct device_node *info;
2518		2586
Lines 2526-2533 Link Here
2526	/* Find out what type of codec we have.	2594	/* Find out what type of codec we have.
2527	*/	2595	*/
2528		2596
2529	static int	2597	static int __init
2530	__init get_codec_type(struct device_node *info)	2598	get_codec_type(struct device_node *info)
2531	{	2599	{
2532	/* already set if pre-davbus model and info will be NULL */	2600	/* already set if pre-davbus model and info will be NULL */
2533	int codec = awacs_revision ;	2601	int codec = awacs_revision ;
Lines 2544-2557 Link Here
2544	codec = AWACS_DACA;	2612	codec = AWACS_DACA;
2545	if (device_is_compatible(info, "tumbler"))	2613	if (device_is_compatible(info, "tumbler"))
2546	codec = AWACS_TUMBLER;	2614	codec = AWACS_TUMBLER;
		2615	if (device_is_compatible(info, "snapper"))
		2616	codec = AWACS_SNAPPER;
2547	}	2617	}
2548	return codec ;	2618	return codec ;
2549	}	2619	}
2550		2620
2551	/* find out what type, if any, of expansion card we have	2621	/* find out what type, if any, of expansion card we have
2552	*/	2622	*/
2553	static void	2623	static void __init
2554	__init get_expansion_type(void)	2624	get_expansion_type(void)
2555	{	2625	{
2556	if (find_devices("perch") != NULL)	2626	if (find_devices("perch") != NULL)
2557	has_perch = 1;	2627	has_perch = 1;
Lines 2569-2576 Link Here
2569	* Set dmasound.mach.max_dsp_rate on the basis of these routines.	2639	* Set dmasound.mach.max_dsp_rate on the basis of these routines.
2570	*/	2640	*/
2571		2641
2572	static void	2642	static void __init
2573	__init init_awacs_frame_rates(unsigned int *prop, unsigned int l)	2643	awacs_init_frame_rates(unsigned int *prop, unsigned int l)
2574	{	2644	{
2575	int i ;	2645	int i ;
2576	if (prop) {	2646	if (prop) {
Lines 2592-2622 Link Here
2592	/* else we assume that all the rates are available */	2662	/* else we assume that all the rates are available */
2593	}	2663	}
2594		2664
2595	static void	2665	static void __init
2596	__init init_tumbler_frame_rates(unsigned int *prop, unsigned int l)	2666	burgundy_init_frame_rates(unsigned int *prop, unsigned int l)
2597	{
2598	int i ;
2599	if (prop) {
2600	for (i=0; i<2; i++)
2601	tumbler_freqs_ok[i] = 0;
2602	for (l /= sizeof(int); l > 0; --l) {
2603	unsigned int r = *prop++;
2604	/* Apple 'Fixed' format */
2605	if (r >= 0x10000)
2606	r >>= 16;
2607	for (i = 0; i < 2; ++i) {
2608	if (r == tumbler_freqs[i]) {
2609	tumbler_freqs_ok[i] = 1;
2610	break;
2611	}
2612	}
2613	}
2614	}
2615	/* else we assume that all the rates are available */
2616	}
2617
2618	static void
2619	__init init_burgundy_frame_rates(unsigned int *prop, unsigned int l)
2620	{	2667	{
2621	int temp[9] ;	2668	int temp[9] ;
2622	int i = 0 ;	2669	int i = 0 ;
Lines 2641-2648 Link Here
2641	#endif	2688	#endif
2642	}	2689	}
2643		2690
2644	static void	2691	static void __init
2645	__init init_daca_frame_rates(unsigned int *prop, unsigned int l)	2692	daca_init_frame_rates(unsigned int *prop, unsigned int l)
2646	{	2693	{
2647	int temp[9] ;	2694	int temp[9] ;
2648	int i = 0 ;	2695	int i = 0 ;
Lines 2668-2688 Link Here
2668	#endif	2715	#endif
2669	}	2716	}
2670		2717
2671	static void	2718	static void __init
2672	__init init_frame_rates(unsigned int *prop, unsigned int l)	2719	init_frame_rates(unsigned int *prop, unsigned int l)
2673	{	2720	{
2674	switch (awacs_revision){	2721	switch (awacs_revision) {
2675	case AWACS_TUMBLER:	2722	case AWACS_TUMBLER:
2676	init_tumbler_frame_rates(prop, l);	2723	case AWACS_SNAPPER:
		2724	tas_init_frame_rates(prop, l);
2677	break ;	2725	break ;
2678	case AWACS_DACA:	2726	case AWACS_DACA:
2679	init_daca_frame_rates(prop, l);	2727	daca_init_frame_rates(prop, l);
2680	break ;	2728	break ;
2681	case AWACS_BURGUNDY:	2729	case AWACS_BURGUNDY:
2682	init_burgundy_frame_rates(prop, l);	2730	burgundy_init_frame_rates(prop, l);
2683	break ;	2731	break ;
2684	default: /* ;-))) */	2732	default:
2685	init_awacs_frame_rates(prop, l);	2733	awacs_init_frame_rates(prop, l);
2686	break ;	2734	break ;
2687	}	2735	}
2688	}	2736	}
Lines 2690-2700 Link Here
2690	/* find things/machines that can't do mac-io byteswap	2738	/* find things/machines that can't do mac-io byteswap
2691	*/	2739	*/
2692		2740
2693	static void	2741	static void __init
2694	__init set_hw_byteswap(struct device_node *io)	2742	set_hw_byteswap(struct device_node *io)
2695	{	2743	{
2696	struct device_node *mio ;	2744	struct device_node *mio ;
2697	unsigned int *p, kl = 0 ;	2745	unsigned int kl = 0 ;
2698		2746
2699	/* if seems that Keylargo can't byte-swap */	2747	/* if seems that Keylargo can't byte-swap */
2700		2748
Lines 2741-2749 Link Here
2741	if( beep_dbdma_cmd_space ) kfree(beep_dbdma_cmd_space) ;	2789	if( beep_dbdma_cmd_space ) kfree(beep_dbdma_cmd_space) ;
2742	return -ENOMEM ;	2790	return -ENOMEM ;
2743	}	2791	}
		2792	#ifdef CONFIG_VT
2744	/* OK, we should be safe to claim the mksound vector now */	2793	/* OK, we should be safe to claim the mksound vector now */
2745	orig_mksound = kd_mksound;	2794	orig_mksound = kd_mksound;
2746	kd_mksound = awacs_mksound;	2795	kd_mksound = awacs_mksound;
		2796	#endif
2747	return 0 ;	2797	return 0 ;
2748	}	2798	}
2749		2799
Lines 2839-2861 Link Here
2839	}	2889	}
2840		2890
2841	/* all OF versions I've seen use this value */	2891	/* all OF versions I've seen use this value */
2842	awacs = (volatile struct awacs_regs *)	2892	if (i2s_node)
2843	ioremap(io->addrs[0].address, 0x1000);	2893	i2s = (u32 *)ioremap(io->addrs[0].address, 0x1000);
		2894	else
		2895	awacs = (volatile struct awacs_regs *)
		2896	ioremap(io->addrs[0].address, 0x1000);
2844	awacs_txdma = (volatile struct dbdma_regs *)	2897	awacs_txdma = (volatile struct dbdma_regs *)
2845	ioremap(io->addrs[1].address, 0x100);	2898	ioremap(io->addrs[1].address, 0x100);
2846	awacs_rxdma = (volatile struct dbdma_regs *)	2899	awacs_rxdma = (volatile struct dbdma_regs *)
2847	ioremap(io->addrs[2].address, 0x100);	2900	ioremap(io->addrs[2].address, 0x100);
2848		2901
2849	#ifdef CONFIG_PMAC_PBOOK
2850	/* first of all make sure that the chip is powered up....*/	2902	/* first of all make sure that the chip is powered up....*/
2851	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, io, 0, 1);	2903	pmac_call_feature(PMAC_FTR_SOUND_CHIP_ENABLE, io, 0, 1);
2852	if (awacs_revision == AWACS_SCREAMER)	2904	if (awacs_revision == AWACS_SCREAMER && awacs)
2853	awacs_recalibrate();	2905	awacs_recalibrate();
2854	#endif	2906
2855	awacs_irq = io->intrs[0].line;	2907	awacs_irq = io->intrs[0].line;
2856	awacs_tx_irq = io->intrs[1].line;	2908	awacs_tx_irq = io->intrs[1].line;
2857	awacs_rx_irq = io->intrs[2].line;	2909	awacs_rx_irq = io->intrs[2].line;
2858		2910
		2911	/* Hack for legacy crap that will be killed someday */
2859	awacs_node = io;	2912	awacs_node = io;
2860		2913
2861	/* if we have an awacs or screamer - probe the chip to make	2914	/* if we have an awacs or screamer - probe the chip to make
Lines 2906-2913 Link Here
2906	/* if it's there use it to set up frame rates */	2959	/* if it's there use it to set up frame rates */
2907	init_frame_rates(prop, l) ;	2960	init_frame_rates(prop, l) ;
2908	}	2961	}
2909		2962
2910	out_le32(&awacs->control, 0x11); /* set everything quiesent */	2963	if (awacs)
		2964	out_le32(&awacs->control, 0x11); /* set everything quiesent */
2911		2965
2912	set_hw_byteswap(io) ; /* figure out if the h/w can do it */	2966	set_hw_byteswap(io) ; /* figure out if the h/w can do it */
2913		2967
Lines 2942-2950 Link Here
2942	#ifdef CONFIG_KMOD	2996	#ifdef CONFIG_KMOD
2943	request_module("i2c-keywest");	2997	request_module("i2c-keywest");
2944	#endif /* CONFIG_KMOD */	2998	#endif /* CONFIG_KMOD */
2945	awacs_tumbler_init();	2999	tas_register_driver(&tas3001c_hooks);
2946	tas_init();	3000	tas_init(I2C_DRIVERID_TAS3001C, I2C_DRIVERNAME_TAS3001C);
		3001	tas_dmasound_init();
		3002	tas_post_init();
2947	break ;	3003	break ;
		3004	case AWACS_SNAPPER:
		3005	#ifdef CONFIG_KMOD
		3006	request_module("i2c-keywest");
		3007	#endif /* CONFIG_KMOD */
		3008	tas_register_driver(&tas3004_hooks);
		3009	tas_init(I2C_DRIVERID_TAS3004,I2C_DRIVERNAME_TAS3004);
		3010	tas_dmasound_init();
		3011	tas_post_init();
		3012	break;
2948	case AWACS_DACA:	3013	case AWACS_DACA:
2949	#ifdef CONFIG_KMOD	3014	#ifdef CONFIG_KMOD
2950	request_module("i2c-keywest");	3015	request_module("i2c-keywest");
Lines 3028-3038 Link Here
3028	dmasound.mach.hardware_afmts = AFMT_S16_BE ;	3093	dmasound.mach.hardware_afmts = AFMT_S16_BE ;
3029		3094
3030	/* shut out chips that do output only.	3095	/* shut out chips that do output only.
3031	may need to extend this to machines which have no inputs - even tho'	3096	* may need to extend this to machines which have no inputs - even tho'
3032	they use screamer - IIRC one of the powerbooks is like this.	3097	* they use screamer - IIRC one of the powerbooks is like this.
3033	*/	3098	*
		3099	* FIXME: Actually, some TUMBLER and SNAPPER do have inputs...
		3100	*/
3034		3101
3035	if (awacs_revision != AWACS_TUMBLER && awacs_revision != AWACS_DACA) {	3102	if (awacs_revision != AWACS_TUMBLER &&
		3103	awacs_revision != AWACS_SNAPPER &&
		3104	awacs_revision != AWACS_DACA) {
3036	dmasound.mach.capabilities = DSP_CAP_DUPLEX ;	3105	dmasound.mach.capabilities = DSP_CAP_DUPLEX ;
3037	dmasound.mach.record = PMacRecord ;	3106	dmasound.mach.record = PMacRecord ;
3038	}	3107	}
Lines 3050-3055 Link Here
3050	case AWACS_TUMBLER:	3119	case AWACS_TUMBLER:
3051	sprintf(awacs_name, "PowerMac Tumbler ") ;	3120	sprintf(awacs_name, "PowerMac Tumbler ") ;
3052	break ;	3121	break ;
		3122	case AWACS_SNAPPER:
		3123	sprintf(awacs_name, "PowerMac Snapper ") ;
		3124	break ;
3053	case AWACS_SCREAMER:	3125	case AWACS_SCREAMER:
3054	sprintf(awacs_name, "PowerMac Screamer ") ;	3126	sprintf(awacs_name, "PowerMac Screamer ") ;
3055	break ;	3127	break ;
Lines 3066-3072 Link Here
3066	{	3138	{
3067	switch (awacs_revision) {	3139	switch (awacs_revision) {
3068	case AWACS_TUMBLER:	3140	case AWACS_TUMBLER:
3069	awacs_tumbler_cleanup();	3141	case AWACS_SNAPPER:
		3142	tas_dmasound_cleanup();
3070	tas_cleanup();	3143	tas_cleanup();
3071	break ;	3144	break ;
3072	case AWACS_DACA:	3145	case AWACS_DACA:
Lines 3081-3083 Link Here
3081		3154
3082	module_init(dmasound_awacs_init);	3155	module_init(dmasound_awacs_init);
3083	module_exit(dmasound_awacs_cleanup);	3156	module_exit(dmasound_awacs_cleanup);
		3157	/*
		3158	* Local Variables:
		3159	* tab-width: 8
		3160	* indent-tabs-mode: t
		3161	* c-basic-offset: 8
		3162	* End:
		3163	*/




/*
 * Driver for the i2c/i2s based TA3004 sound chip used
 * on some Apple hardware. Also known as "snapper".
 *
 * Tobias Sargeant <tobias.sargeant@bigpond.com>
 * Based upon, tas3001c.c by Christopher C. Chimelis <chris@debian.org>:
 *  for more details.
 *
 * Modified by Christopher C. Chimelis <chris@debian.org>:
 *
 *   TODO:
 *   -----
 *   * Enable DRC since the TiBook speakers are less than good
 *   * Enable control over input line 2 (is this connected?)
 *   * Implement sleep support (at least mute everything and
 *   * set gains to minimum during sleep)
 *   * Look into some of Darwin's tweaks regarding the mute
 *   * lines (delays & different behaviour on some HW)
 *   * Implement sleep support
 *
 *   Version 0.4:
 *   ------------
 *   * Balance control finally works (can someone document OSS better please?)
 *   * Moved to a struct for common values referenced in the driver
 *   * Put stubs in for sleep/wake-up support for now.  This will take some
 *     experimentation to make sure that the timing is right, since the
 *     TAS hardware requires specific timing while enabling low-power mode.
 *     I may cheat for now and just reset the chip on wake-up, but I'd rather
 *     not if I don't have to.
 *
 *   Version 0.3:
 *   ------------
 *   * Fixed volume control
 *   * Added bass and treble control
 *   * Added PCM line level control (mixer 1 in the TAS manual)
 *
 */


#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/soundcard.h>
#include <asm/uaccess.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/prom.h>

#include "dmasound.h"
#include "tas_common.h"
#include "tas3001c.h"

#include "tas_ioctl.h"

#define TAS3001C_BIQUAD_FILTER_COUNT  6
#define TAS3001C_BIQUAD_CHANNEL_COUNT 2

#define VOL_DEFAULT	(100 * 4 / 5)
#define INPUT_DEFAULT	(100 * 4 / 5)
#define BASS_DEFAULT	(100 / 2)
#define TREBLE_DEFAULT	(100 / 2)

struct tas3001c_data_t {
	struct tas_data_t super;
	int device_id;
	int output_id;
	int speaker_id;
	struct tas_drce_t drce_state;
};

#define VOL_DEFAULT	(((((TAS_SETTING_MAX*4)/5)<<0)<<8) | (((TAS_SETTING_MAX*4)/5)<<0))
#define INPUT_DEFAULT	(((TAS_SETTING_MAX*4)/5)<<0)
#define BASS_DEFAULT	((TAS_SETTING_MAX/2)<<0)
#define TREBLE_DEFAULT	((TAS_SETTING_MAX/2)<<0)

static const union tas_biquad_t
tas3001c_eq_unity={
	buf: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 }
};

int tumbler_enter_sleep(void);
int tumbler_leave_sleep(void);

static inline unsigned char db_to_regval(short db) {
	int r=0;
static int tas_detach_client(struct i2c_client *client);

	r=(db+0x59a0) / 0x60;
static int tas_id;
static int tas_initialized;

	if (r < 0x91) return 0x91;
	if (r > 0xef) return 0xef;
	return r;
}

static inline short quantize_db(short db) {
	return db_to_regval(db) * 0x60 - 0x59a0;
}
	uint treble;		/* treble */
	uint bass;		/* bass */
	uint pcm_level;		/* pcm level */
};

struct i2c_driver tas_driver = {  
	name:		"TAS3001C driver  V 0.3",
	id:		I2C_DRIVERID_TAS,
	flags:		I2C_DF_NOTIFY,
	attach_adapter:	&tas_attach_adapter,
	detach_client:	&tas_detach_client,
	command:	NULL,
	inc_use:	NULL, /* &tas_inc_use, */
	dec_use:	NULL  /* &tas_dev_use  */
};

static inline int
register_width(enum tas3001c_reg_t r)
{
	switch(r) {
	case TAS3001C_REG_MCR:
 	case TAS3001C_REG_TREBLE:
	case TAS3001C_REG_BASS:
		return 1;

	case TAS3001C_REG_DRC:
		return 2;

	case TAS3001C_REG_MIXER1:
	case TAS3001C_REG_MIXER2:
		return 3;

	case TAS3001C_REG_VOLUME:
		return 6;

	case TAS3001C_REG_LEFT_BIQUAD0:
	case TAS3001C_REG_LEFT_BIQUAD1:
	case TAS3001C_REG_LEFT_BIQUAD2:
	case TAS3001C_REG_LEFT_BIQUAD3:
	case TAS3001C_REG_LEFT_BIQUAD4:
	case TAS3001C_REG_LEFT_BIQUAD5:
	case TAS3001C_REG_LEFT_BIQUAD6:

	case TAS3001C_REG_RIGHT_BIQUAD0:
	case TAS3001C_REG_RIGHT_BIQUAD1:
	case TAS3001C_REG_RIGHT_BIQUAD2:
	case TAS3001C_REG_RIGHT_BIQUAD3:
	case TAS3001C_REG_RIGHT_BIQUAD4:
	case TAS3001C_REG_RIGHT_BIQUAD5:
	case TAS3001C_REG_RIGHT_BIQUAD6:
		return 15;

	default:
		return 0;
	}
}

static int
tas3001c_write_register(	struct tas3001c_data_t *self,
				enum tas3001c_reg_t reg_num,
				char *data,
				uint write_mode)
{
	if (reg_num==TAS3001C_REG_MCR ||
	    reg_num==TAS3001C_REG_BASS ||
	    reg_num==TAS3001C_REG_TREBLE) {
		return tas_write_byte_register(&self->super,
					       (uint)reg_num,
					       *data,
					       write_mode);
	} else {
		return tas_write_register(&self->super,
					  (uint)reg_num,
					  register_width(reg_num),
					  data,
					  write_mode);
	}
	return 0;
}

static int
tas3001c_sync_register(	struct tas3001c_data_t *self,
			enum tas3001c_reg_t reg_num)
{
	if (reg_num==TAS3001C_REG_MCR ||
	    reg_num==TAS3001C_REG_BASS ||
	    reg_num==TAS3001C_REG_TREBLE) {
		return tas_sync_byte_register(&self->super,
					      (uint)reg_num,
					      register_width(reg_num));
	} else {
		return tas_sync_register(&self->super,
					 (uint)reg_num,
					 register_width(reg_num));
	}
}

static int
tas3001c_read_register(	struct tas3001c_data_t *self,
			enum tas3001c_reg_t reg_num,
			char *data,
			uint write_mode)
{
	return tas_read_register(&self->super,
				 (uint)reg_num,
				 register_width(reg_num),
				 data);
}

static inline int
tas3001c_fast_load(struct tas3001c_data_t *self, int fast)
{
	if (fast)
		self->super.shadow[TAS3001C_REG_MCR][0] |= 0x80;
	else
		self->super.shadow[TAS3001C_REG_MCR][0] &= 0x7f;
	return tas3001c_sync_register(self,TAS3001C_REG_MCR);
}

static uint
tas3001c_supported_mixers(struct tas3001c_data_t *self)
{
	return SOUND_MASK_VOLUME |
		SOUND_MASK_PCM |
		SOUND_MASK_ALTPCM |
		SOUND_MASK_TREBLE |
		SOUND_MASK_BASS;
}

static int
tas3001c_mixer_is_stereo(struct tas3001c_data_t *self,int mixer)
{
	switch(mixer) {
	case SOUND_MIXER_VOLUME:
		return 1;
	default:
		return 0;
	}
}

static uint
tas3001c_stereo_mixers(struct tas3001c_data_t *self)
{
	uint r=tas3001c_supported_mixers(self);
	uint i;
	
	for (i=1; i<SOUND_MIXER_NRDEVICES; i++)
		if (r&(1<<i) && !tas3001c_mixer_is_stereo(self,i))
			r &= ~(1<<i);
	return r;
}

static int
tas3001c_get_mixer_level(struct tas3001c_data_t *self,int mixer,uint *level)
{
	if (!self)
		return -1;
		
	*level=self->super.mixer[mixer];
	*treble = data->treble;
	
	return 0;
}

static int
tas3001c_set_mixer_level(struct tas3001c_data_t *self,int mixer,uint level)
{
	int rc;
	tas_shadow_t *shadow;
	if (!tumbler_client)
		return -1;

	uint temp;
	uint offset=0;

	if (!self)
		return -1;
		
	shadow=self->super.shadow;

	if (!tas3001c_mixer_is_stereo(self,mixer))
		level = tas_mono_to_stereo(level);

	switch(mixer) {
	case SOUND_MIXER_VOLUME:
		temp = tas3001c_gain.master[level&0xff];
		shadow[TAS3001C_REG_VOLUME][0] = (temp >> 16) & 0xff;
		shadow[TAS3001C_REG_VOLUME][1] = (temp >> 8)  & 0xff;
		shadow[TAS3001C_REG_VOLUME][2] = (temp >> 0)  & 0xff;
		temp = tas3001c_gain.master[(level>>8)&0xff];
		shadow[TAS3001C_REG_VOLUME][3] = (temp >> 16) & 0xff;
		shadow[TAS3001C_REG_VOLUME][4] = (temp >> 8)  & 0xff;
		shadow[TAS3001C_REG_VOLUME][5] = (temp >> 0)  & 0xff;
		rc = tas3001c_sync_register(self,TAS3001C_REG_VOLUME);
		break;
	case SOUND_MIXER_ALTPCM:
		/* tas3001c_fast_load(self, 1); */
		level = tas_mono_to_stereo(level);
		temp = tas3001c_gain.mixer[level&0xff];
		shadow[TAS3001C_REG_MIXER2][offset+0] = (temp >> 16) & 0xff;
		shadow[TAS3001C_REG_MIXER2][offset+1] = (temp >> 8)  & 0xff;
		shadow[TAS3001C_REG_MIXER2][offset+2] = (temp >> 0)  & 0xff;
		rc = tas3001c_sync_register(self,TAS3001C_REG_MIXER2);
		/* tas3001c_fast_load(self, 0); */
		break;
	case SOUND_MIXER_PCM:
		/* tas3001c_fast_load(self, 1); */
		level = tas_mono_to_stereo(level);
		temp = tas3001c_gain.mixer[level&0xff];
		shadow[TAS3001C_REG_MIXER1][offset+0] = (temp >> 16) & 0xff;
		shadow[TAS3001C_REG_MIXER1][offset+1] = (temp >> 8)  & 0xff;
		shadow[TAS3001C_REG_MIXER1][offset+2] = (temp >> 0)  & 0xff;
		rc = tas3001c_sync_register(self,TAS3001C_REG_MIXER1);
		/* tas3001c_fast_load(self, 0); */
		break;
	case SOUND_MIXER_TREBLE:
		temp = tas3001c_gain.treble[level&0xff];
		shadow[TAS3001C_REG_TREBLE][0]=temp&0xff;
		rc = tas3001c_sync_register(self,TAS3001C_REG_TREBLE);
		break;
	case SOUND_MIXER_BASS:
		temp = tas3001c_gain.bass[level&0xff];
		shadow[TAS3001C_REG_BASS][0]=temp&0xff;
		rc = tas3001c_sync_register(self,TAS3001C_REG_BASS);
		break;
	default:
		rc = -1;
		break;
	}
	if (rc < 0)
		return rc;
	self->super.mixer[mixer]=level;
	return 0;
}

static int
tas3001c_leave_sleep(struct tas3001c_data_t *self)
{
	unsigned char mcr = (1<<6)+(2<<4)+(2<<2);
	char block;
	struct tas_data_t *data;

	if (!self)
		return -1;

	/* Make sure something answers on the i2c bus */
	if (tas3001c_write_register(self, TAS3001C_REG_MCR, &mcr,
	    WRITE_NORMAL|FORCE_WRITE) < 0)
	    	return -1;

	tas3001c_fast_load(self, 1);

	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD0);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD1);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD2);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD3);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD4);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD5);

	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD0);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD1);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD2);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD3);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD4);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD5);

	tas3001c_fast_load(self, 0);
	if (bass > TAS_SETTING_MAX)
		bass = TAS_SETTING_MAX;
	bass = ((bass * 72) / TAS_SETTING_MAX) << 0;
	bass = tas_bass_table[bass];
	block = (bass >> 0)  & 0xff;

	(void)tas3001c_sync_register(self,TAS3001C_REG_BASS);
	(void)tas3001c_sync_register(self,TAS3001C_REG_TREBLE);
	(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER1);
	(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER2);
	(void)tas3001c_sync_register(self,TAS3001C_REG_VOLUME);

	return 0;
}

static int
tas3001c_enter_sleep(struct tas3001c_data_t *self)
{
	/* Stub for now, but I have the details on low-power mode */
	if (!self)
		return -1; 
	}
	data->bass = cur_bass_pers;
	return 0;
}

static int
tas3001c_sync_biquad(	struct tas3001c_data_t *self,
			u_int channel,
			u_int filter)
{
	enum tas3001c_reg_t reg;
	char block;
	struct tas_data_t *data;

	if (channel >= TAS3001C_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3001C_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3001C_REG_RIGHT_BIQUAD0 : TAS3001C_REG_LEFT_BIQUAD0 ) + filter;

	return tas3001c_sync_register(self,reg);
}

static int
tas3001c_write_biquad_shadow(	struct tas3001c_data_t *self,
				u_int channel,
				u_int filter,
				const union tas_biquad_t *biquad)
{
	tas_shadow_t *shadow=self->super.shadow;
	enum tas3001c_reg_t reg;

	if (channel >= TAS3001C_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3001C_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3001C_REG_RIGHT_BIQUAD0 : TAS3001C_REG_LEFT_BIQUAD0 ) + filter;

	SET_4_20(shadow[reg], 0,biquad->coeff.b0);
	SET_4_20(shadow[reg], 3,biquad->coeff.b1);
	SET_4_20(shadow[reg], 6,biquad->coeff.b2);
	SET_4_20(shadow[reg], 9,biquad->coeff.a1);
	SET_4_20(shadow[reg],12,biquad->coeff.a2);

	if (tumbler_set_register(TAS_SET_TREBLE, &block) < 0) {
		printk("tas3001c: failed to set treble \n");  
		return -1; 
	}
	data->treble = cur_treble_pers;
	return 0;
}

static int
tas3001c_write_biquad(	struct tas3001c_data_t *self,
			u_int channel,
			u_int filter,
			const union tas_biquad_t *biquad)
{
	int rc;
	unsigned char block[3];
	struct tas_data_t *data;

	rc=tas3001c_write_biquad_shadow(self, channel, filter, biquad);
	if (rc < 0) return rc;

	return tas3001c_sync_biquad(self, channel, filter);
}

static int
tas3001c_write_biquad_list(	struct tas3001c_data_t *self,
				u_int filter_count,
				u_int flags,
				struct tas_biquad_ctrl_t *biquads)
{
	int i;
	int rc;

	if (flags & TAS_BIQUAD_FAST_LOAD) tas3001c_fast_load(self,1);

	for (i=0; i<filter_count; i++) {
		rc=tas3001c_write_biquad(self,
					 biquads[i].channel,
					 biquads[i].filter,
					 &biquads[i].data);
		if (rc < 0) break;
	}

	if (flags & TAS_BIQUAD_FAST_LOAD) {
		tas3001c_fast_load(self,0);

		(void)tas3001c_sync_register(self,TAS3001C_REG_BASS);
		(void)tas3001c_sync_register(self,TAS3001C_REG_TREBLE);
		(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER1);
		(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER2);
		(void)tas3001c_sync_register(self,TAS3001C_REG_VOLUME);
	}
	data->pcm_level = pcm_lvl_pers;

	return rc;
}

static int
tas3001c_read_biquad(	struct tas3001c_data_t *self,
			u_int channel,
			u_int filter,
			union tas_biquad_t *biquad)
{
	tas_shadow_t *shadow=self->super.shadow;
	enum tas3001c_reg_t reg;

	if (channel >= TAS3001C_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3001C_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3001C_REG_RIGHT_BIQUAD0 : TAS3001C_REG_LEFT_BIQUAD0 ) + filter;

	biquad->coeff.b0=GET_4_20(shadow[reg], 0);
	biquad->coeff.b1=GET_4_20(shadow[reg], 3);
	biquad->coeff.b2=GET_4_20(shadow[reg], 6);
	biquad->coeff.a1=GET_4_20(shadow[reg], 9);
	biquad->coeff.a2=GET_4_20(shadow[reg],12);
	
	return 0;	
}

static int
tas3001c_eq_rw(	struct tas3001c_data_t *self,
		u_int cmd,
		u_long arg)
{
	int rc;
	struct tas_biquad_ctrl_t biquad;
	unsigned char block[6];
	struct tas_data_t *data;

	if (copy_from_user((void *)&biquad, (const void *)arg, sizeof(struct tas_biquad_ctrl_t))) {
		return -EFAULT;
	}

	if (cmd & SIOC_IN) {
		rc=tas3001c_write_biquad(self, biquad.channel, biquad.filter, &biquad.data);
		if (rc != 0) return rc;
	}

	if (cmd & SIOC_OUT) {
		rc=tas3001c_read_biquad(self, biquad.channel, biquad.filter, &biquad.data);
		if (rc != 0) return rc;

		if (copy_to_user((void *)arg, (const void *)&biquad, sizeof(struct tas_biquad_ctrl_t))) {
			return -EFAULT;
		}

	}
	return 0;
}

static int
tas3001c_eq_list_rw(	struct tas3001c_data_t *self,
			u_int cmd,
			u_long arg)
{
	int rc;
	int filter_count;
	int flags;
	int i,j;
	char sync_required[2][6];
	struct tas_biquad_ctrl_t biquad;

	memset(sync_required,0,sizeof(sync_required));

	if (copy_from_user((void *)&filter_count,
			   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t,filter_count),
			   sizeof(int))) {
		return -EFAULT;
	}

	if (copy_from_user((void *)&flags,
			   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t,flags),
			   sizeof(int))) {
		return -EFAULT;
	}

	if (cmd & SIOC_IN) {
	}
	block[2] = (left_vol >> 0)  & 0xff;

	for (i=0; i < filter_count; i++) {
		if (copy_from_user((void *)&biquad,
				   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t, biquads[i]),
				   sizeof(struct tas_biquad_ctrl_t))) {
			return -EFAULT;
		}

		if (cmd & SIOC_IN) {
			sync_required[biquad.channel][biquad.filter]=1;
			rc=tas3001c_write_biquad_shadow(self, biquad.channel, biquad.filter, &biquad.data);
			if (rc != 0) return rc;
		}

		if (cmd & SIOC_OUT) {
			rc=tas3001c_read_biquad(self, biquad.channel, biquad.filter, &biquad.data);
			if (rc != 0) return rc;

			if (copy_to_user((void *)arg + offsetof(struct tas_biquad_ctrl_list_t, biquads[i]),
					 (const void *)&biquad,
					 sizeof(struct tas_biquad_ctrl_t))) {
				return -EFAULT;
			}
		}
	}

	if (cmd & SIOC_IN) {
		if (flags & TAS_BIQUAD_FAST_LOAD) tas3001c_fast_load(self,1);
		for (i=0; i<2; i++) {
			for (j=0; j<6; j++) {
				if (sync_required[i][j]) {
					rc=tas3001c_sync_biquad(self, i, j);
					if (rc < 0) return rc;
				}
			}
		}
		if (flags & TAS_BIQUAD_FAST_LOAD) {
			tas3001c_fast_load(self,0);
			/* now we need to set up the mixers again,
			   because leaving fast mode resets them. */
			(void)tas3001c_sync_register(self,TAS3001C_REG_BASS);
			(void)tas3001c_sync_register(self,TAS3001C_REG_TREBLE);
			(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER1);
			(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER2);
			(void)tas3001c_sync_register(self,TAS3001C_REG_VOLUME);
		}
	}
	data->left_vol = left_vol_pers;
	data->right_vol = right_vol_pers;

	return 0;
}

static int
tas3001c_update_drce(	struct tas3001c_data_t *self,
			int flags,
			struct tas_drce_t *drce)
{
	tas_shadow_t *shadow;
	shadow=self->super.shadow;

	shadow[TAS3001C_REG_DRC][1] = 0xc1;

	if (flags & TAS_DRCE_THRESHOLD) {
		self->drce_state.threshold=quantize_db(drce->threshold);
		shadow[TAS3001C_REG_DRC][2] = db_to_regval(self->drce_state.threshold);
	}

	if (flags & TAS_DRCE_ENABLE) {
		self->drce_state.enable = drce->enable;
	}

	if (!self->drce_state.enable) {
		shadow[TAS3001C_REG_DRC][0] = 0xf0;
	}

#ifdef DEBUG_DRCE
	printk("DRCE IOCTL: set [ ENABLE:%x THRESH:%x\n",
	       self->drce_state.enable,
	       self->drce_state.threshold);

	printk("DRCE IOCTL: reg [ %02x %02x ]\n",
	       (unsigned char)shadow[TAS3001C_REG_DRC][0],
	       (unsigned char)shadow[TAS3001C_REG_DRC][1]);
#endif

	return tas3001c_sync_register(self, TAS3001C_REG_DRC);
}

static int
tas3001c_drce_rw(	struct tas3001c_data_t *self,
			u_int cmd,
			u_long arg)
{
	int rc;
	struct tas_drce_ctrl_t drce_ctrl;

	if (copy_from_user((void *)&drce_ctrl,
			   (const void *)arg,
			   sizeof(struct tas_drce_ctrl_t))) {
		return -EFAULT;
	}

#ifdef DEBUG_DRCE
	printk("DRCE IOCTL: input [ FLAGS:%x ENABLE:%x THRESH:%x\n",
	       drce_ctrl.flags,
	       drce_ctrl.data.enable,
	       drce_ctrl.data.threshold);
#endif

	if (cmd & SIOC_IN) {
		rc = tas3001c_update_drce(self, drce_ctrl.flags, &drce_ctrl.data);
		if (rc < 0)
			return rc;
	}

	if (cmd & SIOC_OUT) {
		if (drce_ctrl.flags & TAS_DRCE_ENABLE)
			drce_ctrl.data.enable = self->drce_state.enable;

		if (drce_ctrl.flags & TAS_DRCE_THRESHOLD)
			drce_ctrl.data.threshold = self->drce_state.threshold;

		if (copy_to_user((void *)arg,
				 (const void *)&drce_ctrl,
				 sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}
	}

	return 0;
}

static void
tas3001c_update_device_parameters(struct tas3001c_data_t *self)
{
	int i,j;
		tas_detect_client(adapter, tas_i2c_address);

	if (!self) return;

	if (self->output_id == TAS_OUTPUT_HEADPHONES) {
		tas3001c_fast_load(self, 1);

		for (i=0; i<TAS3001C_BIQUAD_CHANNEL_COUNT; i++) {
			for (j=0; j<TAS3001C_BIQUAD_FILTER_COUNT; j++) {
				tas3001c_write_biquad(self, i, j, &tas3001c_eq_unity);
			}
		}

		tas3001c_fast_load(self, 0);

		(void)tas3001c_sync_register(self,TAS3001C_REG_BASS);
		(void)tas3001c_sync_register(self,TAS3001C_REG_TREBLE);
		(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER1);
		(void)tas3001c_sync_register(self,TAS3001C_REG_MIXER2);
		(void)tas3001c_sync_register(self,TAS3001C_REG_VOLUME);

		return;
	}

	for (i=0; tas3001c_eq_prefs[i]; i++) {
		struct tas_eq_pref_t *eq = tas3001c_eq_prefs[i];

		if (eq->device_id == self->device_id &&
		    (eq->output_id == 0 || eq->output_id == self->output_id) &&
		    (eq->speaker_id == 0 || eq->speaker_id == self->speaker_id)) {

			tas3001c_update_drce(self, TAS_DRCE_ALL, eq->drce);
			tas3001c_write_biquad_list(self, eq->filter_count, TAS_BIQUAD_FAST_LOAD, eq->biquads);

			break;
		}
	}
}

static void
tas3001c_device_change_handler(void *self)
{
	if (!self) return;
	*/

	tas3001c_update_device_parameters((struct tas3001c_data_t *)self);
}

static struct tq_struct device_change_task;

static int
tas3001c_output_device_change(	struct tas3001c_data_t *self,
				int device_id,
				int output_id,
				int speaker_id)
{
	self->device_id=device_id;
	self->output_id=output_id;
	self->speaker_id=speaker_id;

	schedule_task(&device_change_task);
	tumbler_set_pcm_lvl(INPUT_DEFAULT);
	tumbler_set_bass(BASS_DEFAULT);
	tumbler_set_treble(TREBLE_DEFAULT);

	return 0;
}

static int
tas3001c_device_ioctl(	struct tas3001c_data_t *self,
			u_int cmd,
			u_long arg)
{
	switch (cmd) {
	case TAS_READ_EQ:
	case TAS_WRITE_EQ:
		return tas3001c_eq_rw(self, cmd, arg);

	case TAS_READ_EQ_LIST:
	case TAS_WRITE_EQ_LIST:
		return tas3001c_eq_list_rw(self, cmd, arg);
		goto bail;
	}

	case TAS_READ_EQ_FILTER_COUNT:
		put_user(TAS3001C_BIQUAD_FILTER_COUNT, (uint *)(arg));
		return 0;

	case TAS_READ_EQ_CHANNEL_COUNT:
		put_user(TAS3001C_BIQUAD_CHANNEL_COUNT, (uint *)(arg));
		return 0;
	new_client->driver = &tas_driver;
	new_client->flags = 0;

	case TAS_READ_DRCE:
	case TAS_WRITE_DRCE:
		return tas3001c_drce_rw(self, cmd, arg);

	case TAS_READ_DRCE_CAPS:
		put_user(TAS_DRCE_ENABLE | TAS_DRCE_THRESHOLD, (uint *)(arg));
		return 0;

	case TAS_READ_DRCE_MIN:
	case TAS_READ_DRCE_MAX: {
		struct tas_drce_ctrl_t drce_ctrl;

		if (copy_from_user((void *)&drce_ctrl,
				   (const void *)arg,
				   sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}

		if (drce_ctrl.flags & TAS_DRCE_THRESHOLD) {
			if (cmd == TAS_READ_DRCE_MIN) {
				drce_ctrl.data.threshold=-36<<8;
			} else {
				drce_ctrl.data.threshold=-6<<8;
			}
		}

		if (copy_to_user((void *)arg,
				 (const void *)&drce_ctrl,
				 sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}
	}

	/* Tell the i2c layer a new client has arrived */
	if (i2c_attach_client(new_client)) {
		rc = -ENODEV;
		goto bail;
	}

	return -EINVAL;
		kfree(new_client);
	return rc;
}

static int
tas3001c_init_mixer(struct tas3001c_data_t *self)
{
	unsigned char mcr = (1<<6)+(2<<4)+(2<<2);

	/* Make sure something answers on the i2c bus */
	if (tas3001c_write_register(self, TAS3001C_REG_MCR, &mcr,
	    WRITE_NORMAL|FORCE_WRITE) < 0)
		return -1;

	tas3001c_fast_load(self, 1);

	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD0);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD1);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD2);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD3);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD4);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD5);
	(void)tas3001c_sync_register(self,TAS3001C_REG_RIGHT_BIQUAD6);

	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD0);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD1);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD2);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD3);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD4);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD5);
	(void)tas3001c_sync_register(self,TAS3001C_REG_LEFT_BIQUAD6);

	tas3001c_fast_load(self, 0);

	tas3001c_set_mixer_level(self, SOUND_MIXER_VOLUME, VOL_DEFAULT<<8 | VOL_DEFAULT);
	tas3001c_set_mixer_level(self, SOUND_MIXER_PCM, INPUT_DEFAULT<<8 | INPUT_DEFAULT);
	tas3001c_set_mixer_level(self, SOUND_MIXER_ALTPCM, 0);

	tas3001c_set_mixer_level(self, SOUND_MIXER_BASS, BASS_DEFAULT);
	tas3001c_set_mixer_level(self, SOUND_MIXER_TREBLE, TREBLE_DEFAULT);

	return 0;
}

static int
tas3001c_uninit_mixer(struct tas3001c_data_t *self)
{
	tas3001c_set_mixer_level(self, SOUND_MIXER_VOLUME, 0);
	tas3001c_set_mixer_level(self, SOUND_MIXER_PCM,    0);
	tas3001c_set_mixer_level(self, SOUND_MIXER_ALTPCM, 0);

	tas3001c_set_mixer_level(self, SOUND_MIXER_BASS,   0);
	tas3001c_set_mixer_level(self, SOUND_MIXER_TREBLE, 0);

	return 0;
}

static int
tas3001c_init(struct i2c_client *client)
{
	struct tas3001c_data_t *self;
	int i,j;

	if (tas_initialized)
		return 0;

	self = kmalloc(sizeof(struct tas3001c_data_t) +
			TAS3001C_REG_MAX * sizeof(tas_shadow_t),
			GFP_KERNEL);
	if (self == NULL)
		return -ENOMEM;
	client->data = (void *)self;
	self->super.client = client;
	self->super.shadow = (tas_shadow_t *)(self+1);

	self->output_id=TAS_OUTPUT_HEADPHONES;
	self->device_id=0;
	self->speaker_id=0;

	for (i=0; i<TAS3001C_BIQUAD_CHANNEL_COUNT; i++) {
		for (j=0; j<TAS3001C_BIQUAD_FILTER_COUNT; j++) {
			tas3001c_write_biquad_shadow(self, i, j, &tas3001c_eq_unity);
		}
	}
	INIT_TQUEUE(&device_change_task, tas3001c_device_change_handler, (void *)self);

	return 0;
}

static void
tas3001c_uninit(struct tas3001c_data_t *self)
{
	tas3001c_uninit_mixer(self);
	kfree(self);
}

struct tas_driver_hooks_t tas3001c_hooks = {
	init:                   (tas_hook_init_t)tas3001c_init,
	post_init:              (tas_hook_post_init_t)tas3001c_init_mixer,
	uninit:                 (tas_hook_uninit_t)tas3001c_uninit,

	get_mixer_level:        (tas_hook_get_mixer_level_t)tas3001c_get_mixer_level,
	set_mixer_level:        (tas_hook_set_mixer_level_t)tas3001c_set_mixer_level,

	enter_sleep:            (tas_hook_enter_sleep_t)tas3001c_enter_sleep,
	leave_sleep:            (tas_hook_leave_sleep_t)tas3001c_leave_sleep,

	supported_mixers:       (tas_hook_supported_mixers_t)tas3001c_supported_mixers,
	mixer_is_stereo:        (tas_hook_mixer_is_stereo_t)tas3001c_mixer_is_stereo,
	stereo_mixers:          (tas_hook_stereo_mixers_t)tas3001c_stereo_mixers,

	output_device_change:   (tas_hook_output_device_change_t)tas3001c_output_device_change,

	device_ioctl:           (tas_hook_device_ioctl_t)tas3001c_device_ioctl
};

/*
 * Local Variables:
 * tab-width: 8
 * indent-tabs-mode: t
 * c-basic-offset: 8
 * End:
 */




/*
 * Header file for the i2c/i2s based TA3001c sound chip used
 * on some Apple hardware. Also known as "tumbler".
 *
 *  This file is subject to the terms and conditions of the GNU General Public

 * Written by Christopher C. Chimelis <chris@debian.org>
 */

#ifndef _TAS3001C_H_
#define _TAS3001C_H_

#include <linux/types.h>
 * Macros that correspond to the registers that we write to
 * when setting the various values.
 */
#define TAS_DRC			0x02	/* DRC		*/
#define TAS_VOLUME		0x04	/* Volume	*/
#define TAS_TREBLE		0x05	/* Treble	*/
#define TAS_BASS		0x06	/* Bass		*/
#define TAS_MIXER1		0x07	/* PCM line	*/
#define TAS_MIXER2		0x08	/* Input (Unk)	*/

/*
 * Macros that define various arguments to tas_set_register()
 */
#define TAS_SET_DRC		TAS_DRC, 2
#define TAS_SET_VOLUME		TAS_VOLUME, 6
#define TAS_SET_TREBLE		TAS_TREBLE, 1
#define TAS_SET_BASS		TAS_BASS, 1
#define TAS_SET_MIXER1		TAS_MIXER1, 3
#define TAS_SET_MIXER2		TAS_MIXER2, 3

#include "tas_common.h"
#include "tas_eq_prefs.h"

/*
 * Macros that correspond to the registers that we write to
 * when setting the various values.
 * for the chip, however, it's zero-sourced for your shopping pleasure
 * (meaning, you'll have to compute the difference between the desired
 * dB and the index value of the proper setting.
 *
 * This table should've been replaced by the formula:
 * 	dB = 20 log(x)
 * but, since there's no log() or supporting functions like exp(),
 * my implementation of the above won't work. Yeah, I could do it
 * the hard way, but this table is just easier :-)
 *
 * For reference, -70 dB = tas_volume_table[0]
 */

#define TAS3001C_VERSION	"0.3"
#define TAS3001C_DATE	        "20011214"
	0x00000019,	0x0000001a,	0x0000001c,	/* -68.5, -68.0, -67.5 */
	0x0000001d,	0x0000001f,	0x00000021,	/* -67.0, -66.5, -66.0 */
	0x00000023,	0x00000025,	0x00000027,	/* -65.5, -65.0, -64.5 */
	0x00000029,	0x0000002c,	0x0000002e,	/* -64.0, -63.5, -63.0 */
	0x00000031,	0x00000034,	0x00000037,	/* -62.5, -62.0, -61.5 */
	0x0000003a,	0x0000003e,	0x00000042,	/* -61.0, -60.5, -60.0 */
	0x00000045,	0x0000004a,	0x0000004e,	/* -59.5, -59.0, -58.5 */
	0x00000053,	0x00000057,	0x0000005d,	/* -58.0, -57.5, -57.0 */
	0x00000062,	0x00000068,	0x0000006e,	/* -56.5, -56.0, -55.5 */
	0x00000075,	0x0000007b,	0x00000083,	/* -55.0, -54.5, -54.0 */
	0x0000008b,	0x00000093,	0x0000009b,	/* -53.5, -53.0, -52.5 */
	0x000000a5,	0x000000ae,	0x000000b9,	/* -52.0, -51.5, -51.0 */
	0x000000c4,	0x000000cf,	0x000000dc,	/* -50.5, -50.0, -49.5 */
	0x000000e9,	0x000000f6,	0x00000105,	/* -49.0, -48.5, -48.0 */
	0x00000114,	0x00000125,	0x00000136,	/* -47.5, -47.0, -46.5 */
	0x00000148,	0x0000015c,	0x00000171,	/* -46.0, -45.5, -45.0 */
	0x00000186,	0x0000019e,	0x000001b6,	/* -44.5, -44.0, -43.5 */
	0x000001d0,	0x000001eb,	0x00000209,	/* -43.0, -42.5, -42.0 */
	0x00000227,	0x00000248,	0x0000026b,	/* -41.5, -41.0, -40.5 */
	0x0000028f,	0x000002b6,	0x000002df,	/* -40.0, -39.5, -39.0 */
	0x0000030b,	0x00000339,	0x0000036a,	/* -38.5, -38.0, -37.5 */
	0x0000039e,	0x000003d5,	0x0000040f,	/* -37.0, -36.5, -36.0 */
	0x0000044c,	0x0000048d,	0x000004d2,	/* -35.5, -35.0, -34.5 */
	0x0000051c,	0x00000569,	0x000005bb,	/* -34.0, -33.5, -33.0 */
	0x00000612,	0x0000066e,	0x000006d0,	/* -32.5, -32.0, -31.5 */
	0x00000737,	0x000007a5,	0x00000818,	/* -31.0, -30.5, -30.0 */
	0x00000893,	0x00000915,	0x0000099f,	/* -29.5, -29.0, -28.5 */
	0x00000a31,	0x00000acc,	0x00000b6f,	/* -28.0, -27.5, -27.0 */
	0x00000c1d,	0x00000cd5,	0x00000d97,	/* -26.5, -26.0, -25.5 */
	0x00000e65,	0x00000f40,	0x00001027,	/* -25.0, -24.5, -24.0 */
	0x0000111c,	0x00001220,	0x00001333,	/* -23.5, -23.0, -22.5 */
	0x00001456,	0x0000158a,	0x000016d1,	/* -22.0, -21.5, -21.0 */
	0x0000182b,	0x0000199a,	0x00001b1e,	/* -20.5, -20.0, -19.5 */
	0x00001cb9,	0x00001e6d,	0x0000203a,	/* -19.0, -18.5, -18.0 */
	0x00002223,	0x00002429,	0x0000264e,	/* -17.5, -17.0, -16.5 */
	0x00002893,	0x00002afa,	0x00002d86,	/* -16.0, -15.5, -15.0 */
	0x00003039,	0x00003314,	0x0000361b,	/* -14.5, -14.0, -13.5 */
	0x00003950,	0x00003cb5,	0x0000404e,	/* -13.0, -12.5, -12.0 */
	0x0000441d,	0x00004827,	0x00004c6d,	/* -11.5, -11.0, -10.5 */
	0x000050f4,	0x000055c0,	0x00005ad5,	/* -10.0, -09.5, -09.0 */
	0x00006037,	0x000065ea,	0x00006bf4,	/* -08.5, -08.0, -07.5 */
	0x0000725a,	0x00007920,	0x0000804e,	/* -07.0, -06.5, -06.0 */
	0x000087e8,	0x00008ff6,	0x0000987d,	/* -05.5, -05.0, -04.5 */
	0x0000a186,	0x0000ab19,	0x0000b53c,	/* -04.0, -03.5, -03.0 */
	0x0000bff9,	0x0000cb59,	0x0000d766,	/* -02.5, -02.0, -01.5 */
	0x0000e429,	0x0000f1ae,	0x00010000,	/* -01.0, -00.5,  00.0 */
	0x00010f2b,	0x00011f3d,	0x00013042,	/* +00.5, +01.0, +01.5 */
	0x00014249,	0x00015562,	0x0001699c,	/* +02.0, +02.5, +03.0 */
	0x00017f09,	0x000195bc,	0x0001adc6,	/* +03.5, +04.0, +04.5 */
	0x0001c73d,	0x0001e237,	0x0001feca,	/* +05.0, +05.5, +06.0 */
	0x00021d0e,	0x00023d1d,	0x00025f12,	/* +06.5, +07.0, +07.5 */
	0x0002830b,	0x0002a925,	0x0002d182,	/* +08.0, +08.5, +09.0 */
	0x0002fc42,	0x0003298b,	0x00035983,	/* +09.5, +10.0, +10.5 */
	0x00038c53,	0x0003c225,	0x0003fb28,	/* +11.0, +11.5, +12.0 */
	0x0004378b,	0x00047783,	0x0004bb44,	/* +12.5, +13.0, +13.5 */
	0x0005030a,	0x00054f10,	0x00059f98,	/* +14.0, +14.5, +15.0 */
	0x0005f4e5,	0x00064f40,	0x0006aef6,	/* +15.5, +16.0, +16.5 */
	0x00071457,	0x00077fbb,	0x0007f17b	/* +17.0, +17.5, +18.0 */
};

#define I2C_DRIVERNAME_TAS3001C "TAS3001c driver V " TAS3001C_VERSION
#define I2C_DRIVERID_TAS3001C   (I2C_DRIVERID_TAS_BASE+0)
 * this one, but we use this instead due to lack of real math functions
 * in the kernel.
 */
static char tas_treble_table[] = {
	0x96,		0x95,		0x94,	/* -18.0, -17.5, -17.0 */
	0x93,		0x92,		0x91,	/* -16.5, -16.0, -15.5 */
	0x90,		0x8f,		0x8e,	/* -15.0, -14.5, -14.0 */
	0x8d,		0x8c,		0x8b,	/* -13.5, -13.0, -12.5 */
	0x8a,		0x89,		0x88,	/* -12.0, -11.5, -11.0 */
	0x87,		0x86,		0x85,	/* -10.5, -10.0, -09.5 */
	0x84,		0x83,		0x82,	/* -09.0, -08.5, -08.0 */
	0x81,		0x80,		0x7f,	/* -07.5, -07.0, -06.5 */
	0x7e,		0x7d,		0x7c,	/* -06.0, -05.5, -05.0 */
	0x7b,		0x7a,		0x79,	/* -04.5, -04.0, -03.5 */
	0x78,		0x77,		0x76,	/* -03.0, -02.5, -02.0 */
	0x75,		0x74,		0x73,	/* -01.5, -01.0, -00.5 */
	0x72,		0x71,		0x70,	/*  00.0, +00.5, +01.0 */
	0x6e,		0x6d,		0x6c,	/* +01.5, +02.0, +02.5 */
	0x6b,		0x69,		0x68,	/* +03.0, +03.5, +04.0 */
	0x66,		0x65,		0x63,	/* +04.5, +05.0, +05.5 */
	0x62,		0x60,		0x5e,	/* +06.0, +06.5, +07.0 */
	0x5c,		0x5a,		0x57,	/* +07.5, +08.0, +08.5 */
	0x55,		0x52,		0x4f,	/* +09.0, +09.5, +10.0 */
	0x4c,		0x49,		0x45,	/* +10.5, +11.0, +11.5 */
	0x42,		0x3e,		0x3a,	/* +12.0, +12.5, +13.0 */
	0x36,		0x32,		0x2d,	/* +13.5, +14.0, +14.5 */
	0x28,		0x22,		0x1c,	/* +15.0, +15.5, +16.0 */
	0x16,		0x10,		0x09,	/* +16.5, +17.0, +17.5 */
	0x01					/* +18.0	       */
};

extern  struct tas_driver_hooks_t tas3001c_hooks;
extern struct tas_gain_t tas3001c_gain;
extern struct tas_eq_pref_t *tas3001c_eq_prefs[];

enum tas3001c_reg_t {
  TAS3001C_REG_MCR                    = 0x01,
  TAS3001C_REG_DRC                    = 0x02,

  TAS3001C_REG_VOLUME                 = 0x04,
  TAS3001C_REG_TREBLE                 = 0x05,
  TAS3001C_REG_BASS                   = 0x06,
  TAS3001C_REG_MIXER1                 = 0x07,
  TAS3001C_REG_MIXER2                 = 0x08,

  TAS3001C_REG_LEFT_BIQUAD0           = 0x0a,
  TAS3001C_REG_LEFT_BIQUAD1           = 0x0b,
  TAS3001C_REG_LEFT_BIQUAD2           = 0x0c,
  TAS3001C_REG_LEFT_BIQUAD3           = 0x0d,
  TAS3001C_REG_LEFT_BIQUAD4           = 0x0e,
  TAS3001C_REG_LEFT_BIQUAD5           = 0x0f,
  TAS3001C_REG_LEFT_BIQUAD6           = 0x10,
  
  TAS3001C_REG_RIGHT_BIQUAD0          = 0x13,
  TAS3001C_REG_RIGHT_BIQUAD1          = 0x14,
  TAS3001C_REG_RIGHT_BIQUAD2          = 0x15,
  TAS3001C_REG_RIGHT_BIQUAD3          = 0x16,
  TAS3001C_REG_RIGHT_BIQUAD4          = 0x17,
  TAS3001C_REG_RIGHT_BIQUAD5          = 0x18,
  TAS3001C_REG_RIGHT_BIQUAD6          = 0x19,
	0x08,		0x06,		0x03,	/* +16.5, +17.0, +17.5 */
	0x01					/* +18.0	       */
};

  TAS3001C_REG_MAX                    = 0x20
 * the setting registers on the TAS for "mixers 1 & 2" (which are the input
 * lines).  Again, there is a formula for these, but we use this instead
 * due to lack of real math functions in the kernel.
 */
static unsigned int tas_input_table[] = {
	0x00014b,	0x00015f,	0x000174,	/* -70.0, -69.5, -69.0 */
	0x00018a,	0x0001a1,	0x0001ba,	/* -68.5, -68.0, -67.5 */
	0x0001d4,	0x0001f0,	0x00020d,	/* -67.0, -66.5, -66.0 */
	0x00022c,	0x00024d,	0x000270,	/* -65.5, -65.0, -64.5 */
	0x000295,	0x0002bc,	0x0002e6,	/* -64.0, -63.5, -63.0 */
	0x000312,	0x000340,	0x000372,	/* -62.5, -62.0, -61.5 */
	0x0003a6,	0x0003dd,	0x000418,	/* -61.0, -60.5, -60.0 */
	0x000456,	0x000498,	0x0004de,	/* -59.5, -59.0, -58.5 */
	0x000528,	0x000576,	0x0005c9,	/* -58.0, -57.5, -57.0 */
	0x000620,	0x00067d,	0x0006e0,	/* -56.5, -56.0, -55.5 */
	0x000748,	0x0007b7,	0x00082c,	/* -55.0, -54.5, -54.0 */
	0x0008a8,	0x00092b,	0x0009b6,	/* -53.5, -53.0, -52.5 */
	0x000a49,	0x000ae5,	0x000b8b,	/* -52.0, -51.5, -51.0 */
	0x000c3a,	0x000cf3,	0x000db8,	/* -50.5, -50.0, -49.5 */
	0x000e88,	0x000f64,	0x00104e,	/* -49.0, -48.5, -48.0 */
	0x001145,	0x00124b,	0x001361,	/* -47.5, -47.0, -46.5 */
	0x001487,	0x0015be,	0x001708,	/* -46.0, -45.5, -45.0 */
	0x001865,	0x0019d8,	0x001b60,	/* -44.5, -44.0, -43.5 */
	0x001cff,	0x001eb7,	0x002089,	/* -43.0, -42.5, -42.0 */
	0x002276,	0x002481,	0x0026ab,	/* -41.5, -41.0, -40.5 */
	0x0028f5,	0x002b63,	0x002df5,	/* -40.0, -39.5, -39.0 */
	0x0030ae,	0x003390,	0x00369e,	/* -38.5, -38.0, -37.5 */
	0x0039db,	0x003d49,	0x0040ea,	/* -37.0, -36.5, -36.0 */
	0x0044c3,	0x0048d6,	0x004d27,	/* -35.5, -35.0, -34.5 */
	0x0051b9,	0x005691,	0x005bb2,	/* -34.0, -33.5, -33.0 */
	0x006121,	0x0066e3,	0x006cfb,	/* -32.5, -32.0, -31.5 */
	0x007370,	0x007a48,	0x008186,	/* -31.0, -30.5, -30.0 */
	0x008933,	0x009154,	0x0099f1,	/* -29.5, -29.0, -28.5 */
	0x00a310,	0x00acba,	0x00b6f6,	/* -28.0, -27.5, -27.0 */
	0x00c1cd,	0x00cd49,	0x00d973,	/* -26.5, -26.0, -25.5 */
	0x00e655,	0x00f3fb,	0x010270,	/* -25.0, -24.5, -24.0 */
	0x0111c0,	0x0121f9,	0x013328,	/* -23.5, -23.0, -22.5 */
	0x01455b,	0x0158a2,	0x016d0e,	/* -22.0, -21.5, -21.0 */
	0x0182af,	0x019999,	0x01b1de,	/* -20.5, -20.0, -19.5 */
	0x01cb94,	0x01e6cf,	0x0203a7,	/* -19.0, -18.5, -18.0 */
	0x022235,	0x024293,	0x0264db,	/* -17.5, -17.0, -16.5 */
	0x02892c,	0x02afa3,	0x02d862,	/* -16.0, -15.5, -15.0 */
	0x03038a,	0x033142,	0x0361af,	/* -14.5, -14.0, -13.5 */
	0x0394fa,	0x03cb50,	0x0404de,	/* -13.0, -12.5, -12.0 */
	0x0441d5,	0x048268,	0x04c6d0,	/* -11.5, -11.0, -10.5 */
	0x050f44,	0x055c04,	0x05ad50,	/* -10.0, -09.5, -09.0 */
	0x06036e,	0x065ea5,	0x06bf44,	/* -08.5, -08.0, -07.5 */
	0x07259d,	0x079207,	0x0804dc,	/* -07.0, -06.5, -06.0 */
	0x087e80,	0x08ff59,	0x0987d5,	/* -05.5, -05.0, -04.5 */
	0x0a1866,	0x0ab189,	0x0b53be,	/* -04.0, -03.5, -03.0 */
	0x0bff91,	0x0cb591,	0x0d765a,	/* -02.5, -02.0, -01.5 */
	0x0e4290,	0x0f1adf,	0x100000,	/* -01.0, -00.5,  00.0 */
	0x10f2b4,	0x11f3c9,	0x13041a,	/* +00.5, +01.0, +01.5 */
	0x14248e,	0x15561a,	0x1699c0,	/* +02.0, +02.5, +03.0 */
	0x17f094,	0x195bb8,	0x1adc61,	/* +03.5, +04.0, +04.5 */
	0x1c73d5,	0x1e236d,	0x1fec98,	/* +05.0, +05.5, +06.0 */
	0x21d0d9,	0x23d1cd,	0x25f125,	/* +06.5, +07.0, +07.5 */
	0x2830af,	0x2a9254,	0x2d1818,	/* +08.0, +08.5, +09.0 */
	0x2fc420,	0x3298b0,	0x35982f,	/* +09.5, +10.0, +10.5 */
	0x38c528,	0x3c224c,	0x3fb278,	/* +11.0, +11.5, +12.0 */
	0x437880,	0x477828,	0x4bb446,	/* +12.5, +13.0, +13.5 */
	0x5030a1,	0x54f106,	0x59f980,	/* +14.0, +14.5, +15.0 */
	0x5f4e52,	0x64f403,	0x6aef5d,	/* +15.5, +16.0, +16.5 */
	0x714575,	0x77fbaa,	0x7f17af	/* +17.0, +17.5, +18.0 */
};

#endif /* _TAS3001C_H_ */




#include "tas_common.h"
#include "tas_eq_prefs.h"

static struct tas_drce_t eqp_0e_2_1_drce = {
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -15.33  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_0e_2_1_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0FCAD3, 0xE06A58, 0x0FCAD3, 0xE06B09, 0x0F9657 } } },
  { channel: 0, filter: 1, data: { coeff: { 0x041731, 0x082E63, 0x041731, 0xFD8D08, 0x02CFBD } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0FFDC7, 0xE0524C, 0x0FBFAA, 0xE0524C, 0x0FBD72 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0F3D35, 0xE228CA, 0x0EC7B2, 0xE228CA, 0x0E04E8 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0FCEBF, 0xE181C2, 0x0F2656, 0xE181C2, 0x0EF516 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0EC417, 0x073E22, 0x0B0633, 0x073E22, 0x09CA4A } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0FCAD3, 0xE06A58, 0x0FCAD3, 0xE06B09, 0x0F9657 } } },
  { channel: 1, filter: 1, data: { coeff: { 0x041731, 0x082E63, 0x041731, 0xFD8D08, 0x02CFBD } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0FFDC7, 0xE0524C, 0x0FBFAA, 0xE0524C, 0x0FBD72 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0F3D35, 0xE228CA, 0x0EC7B2, 0xE228CA, 0x0E04E8 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0FCEBF, 0xE181C2, 0x0F2656, 0xE181C2, 0x0EF516 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0EC417, 0x073E22, 0x0B0633, 0x073E22, 0x09CA4A } } },
};

static struct tas_eq_pref_t eqp_0e_2_1 = {
  sample_rate:  44100,
  device_id:    0x0e,
  output_id:    TAS_OUTPUT_EXTERNAL_SPKR,
  speaker_id:   0x01,

  drce:         &eqp_0e_2_1_drce,

  filter_count: 12,
  biquads:      eqp_0e_2_1_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_10_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -12.46  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_10_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0F4A12, 0xE16BDA, 0x0F4A12, 0xE173F0, 0x0E9C3A } } },
  { channel: 0, filter: 1, data: { coeff: { 0x02DD54, 0x05BAA8, 0x02DD54, 0xF8001D, 0x037532 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0E2FC7, 0xE4D5DC, 0x0D7477, 0xE4D5DC, 0x0BA43F } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0E7899, 0xE67CCA, 0x0D0E93, 0xE67CCA, 0x0B872D } } },
  { channel: 0, filter: 4, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0F4A12, 0xE16BDA, 0x0F4A12, 0xE173F0, 0x0E9C3A } } },
  { channel: 1, filter: 1, data: { coeff: { 0x02DD54, 0x05BAA8, 0x02DD54, 0xF8001D, 0x037532 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0E2FC7, 0xE4D5DC, 0x0D7477, 0xE4D5DC, 0x0BA43F } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0E7899, 0xE67CCA, 0x0D0E93, 0xE67CCA, 0x0B872D } } },
  { channel: 1, filter: 4, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } },
};

static struct tas_eq_pref_t eqp_10_1_0 = {
  sample_rate:  44100,
  device_id:    0x10,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_10_1_0_drce,

  filter_count: 12,
  biquads:      eqp_10_1_0_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_15_2_1_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -15.33  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_15_2_1_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0FE143, 0xE05204, 0x0FCCC5, 0xE05266, 0x0FAE6B } } },
  { channel: 0, filter: 1, data: { coeff: { 0x102383, 0xE03A03, 0x0FA325, 0xE03A03, 0x0FC6A8 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0FF2AB, 0xE06285, 0x0FB20A, 0xE06285, 0x0FA4B5 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0F544D, 0xE35971, 0x0D8F3A, 0xE35971, 0x0CE388 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x13E1D3, 0xF3ECB5, 0x042227, 0xF3ECB5, 0x0803FA } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0AC119, 0x034181, 0x078AB1, 0x034181, 0x024BCA } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0FE143, 0xE05204, 0x0FCCC5, 0xE05266, 0x0FAE6B } } },
  { channel: 1, filter: 1, data: { coeff: { 0x102383, 0xE03A03, 0x0FA325, 0xE03A03, 0x0FC6A8 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0FF2AB, 0xE06285, 0x0FB20A, 0xE06285, 0x0FA4B5 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0F544D, 0xE35971, 0x0D8F3A, 0xE35971, 0x0CE388 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x13E1D3, 0xF3ECB5, 0x042227, 0xF3ECB5, 0x0803FA } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0AC119, 0x034181, 0x078AB1, 0x034181, 0x024BCA } } },
};

static struct tas_eq_pref_t eqp_15_2_1 = {
  sample_rate:  44100,
  device_id:    0x15,
  output_id:    TAS_OUTPUT_EXTERNAL_SPKR,
  speaker_id:   0x01,

  drce:         &eqp_15_2_1_drce,

  filter_count: 12,
  biquads:      eqp_15_2_1_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_15_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: 0.0     * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_15_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0FAD08, 0xE0A5EF, 0x0FAD08, 0xE0A79D, 0x0F5BBE } } },
  { channel: 0, filter: 1, data: { coeff: { 0x04B38D, 0x09671B, 0x04B38D, 0x000F71, 0x02BEC5 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0FDD32, 0xE0A56F, 0x0F8A69, 0xE0A56F, 0x0F679C } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0FD284, 0xE135FB, 0x0F2161, 0xE135FB, 0x0EF3E5 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0E81B1, 0xE6283F, 0x0CE49D, 0xE6283F, 0x0B664F } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0F2D62, 0xE98797, 0x0D1E19, 0xE98797, 0x0C4B7B } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0FAD08, 0xE0A5EF, 0x0FAD08, 0xE0A79D, 0x0F5BBE } } },
  { channel: 1, filter: 1, data: { coeff: { 0x04B38D, 0x09671B, 0x04B38D, 0x000F71, 0x02BEC5 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0FDD32, 0xE0A56F, 0x0F8A69, 0xE0A56F, 0x0F679C } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0FD284, 0xE135FB, 0x0F2161, 0xE135FB, 0x0EF3E5 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0E81B1, 0xE6283F, 0x0CE49D, 0xE6283F, 0x0B664F } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0F2D62, 0xE98797, 0x0D1E19, 0xE98797, 0x0C4B7B } } },
};

static struct tas_eq_pref_t eqp_15_1_0 = {
  sample_rate:  44100,
  device_id:    0x15,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_15_1_0_drce,

  filter_count: 12,
  biquads:      eqp_15_1_0_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_0f_2_1_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -15.33  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_0f_2_1_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0FE143, 0xE05204, 0x0FCCC5, 0xE05266, 0x0FAE6B } } },
  { channel: 0, filter: 1, data: { coeff: { 0x102383, 0xE03A03, 0x0FA325, 0xE03A03, 0x0FC6A8 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0FF2AB, 0xE06285, 0x0FB20A, 0xE06285, 0x0FA4B5 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0F544D, 0xE35971, 0x0D8F3A, 0xE35971, 0x0CE388 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x13E1D3, 0xF3ECB5, 0x042227, 0xF3ECB5, 0x0803FA } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0AC119, 0x034181, 0x078AB1, 0x034181, 0x024BCA } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0FE143, 0xE05204, 0x0FCCC5, 0xE05266, 0x0FAE6B } } },
  { channel: 1, filter: 1, data: { coeff: { 0x102383, 0xE03A03, 0x0FA325, 0xE03A03, 0x0FC6A8 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0FF2AB, 0xE06285, 0x0FB20A, 0xE06285, 0x0FA4B5 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0F544D, 0xE35971, 0x0D8F3A, 0xE35971, 0x0CE388 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x13E1D3, 0xF3ECB5, 0x042227, 0xF3ECB5, 0x0803FA } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0AC119, 0x034181, 0x078AB1, 0x034181, 0x024BCA } } },
};

static struct tas_eq_pref_t eqp_0f_2_1 = {
  sample_rate:  44100,
  device_id:    0x0f,
  output_id:    TAS_OUTPUT_EXTERNAL_SPKR,
  speaker_id:   0x01,

  drce:         &eqp_0f_2_1_drce,

  filter_count: 12,
  biquads:      eqp_0f_2_1_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_0f_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -15.33  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_0f_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0FCAD3, 0xE06A58, 0x0FCAD3, 0xE06B09, 0x0F9657 } } },
  { channel: 0, filter: 1, data: { coeff: { 0x041731, 0x082E63, 0x041731, 0xFD8D08, 0x02CFBD } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0FFDC7, 0xE0524C, 0x0FBFAA, 0xE0524C, 0x0FBD72 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0F3D35, 0xE228CA, 0x0EC7B2, 0xE228CA, 0x0E04E8 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0FCEBF, 0xE181C2, 0x0F2656, 0xE181C2, 0x0EF516 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0EC417, 0x073E22, 0x0B0633, 0x073E22, 0x09CA4A } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0FCAD3, 0xE06A58, 0x0FCAD3, 0xE06B09, 0x0F9657 } } },
  { channel: 1, filter: 1, data: { coeff: { 0x041731, 0x082E63, 0x041731, 0xFD8D08, 0x02CFBD } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0FFDC7, 0xE0524C, 0x0FBFAA, 0xE0524C, 0x0FBD72 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0F3D35, 0xE228CA, 0x0EC7B2, 0xE228CA, 0x0E04E8 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0FCEBF, 0xE181C2, 0x0F2656, 0xE181C2, 0x0EF516 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0EC417, 0x073E22, 0x0B0633, 0x073E22, 0x09CA4A } } },
};

static struct tas_eq_pref_t eqp_0f_1_0 = {
  sample_rate:  44100,
  device_id:    0x0f,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_0f_1_0_drce,

  filter_count: 12,
  biquads:      eqp_0f_1_0_biquads
};

/* ======================================================================== */

static uint tas3001c_master_tab[]={
	       0x0,       0x75,       0x9c,       0xbb,
	      0xdb,       0xfb,      0x11e,      0x143,
	     0x16b,      0x196,      0x1c3,      0x1f5,
	     0x229,      0x263,      0x29f,      0x2e1,
	     0x328,      0x373,      0x3c5,      0x41b,
	     0x478,      0x4dc,      0x547,      0x5b8,
	     0x633,      0x6b5,      0x740,      0x7d5,
	     0x873,      0x91c,      0x9d2,      0xa92,
	     0xb5e,      0xc39,      0xd22,      0xe19,
	     0xf20,     0x1037,     0x1161,     0x129e,
	    0x13ed,     0x1551,     0x16ca,     0x185d,
	    0x1a08,     0x1bcc,     0x1dac,     0x1fa7,
	    0x21c1,     0x23fa,     0x2655,     0x28d6,
	    0x2b7c,     0x2e4a,     0x3141,     0x3464,
	    0x37b4,     0x3b35,     0x3ee9,     0x42d3,
	    0x46f6,     0x4b53,     0x4ff0,     0x54ce,
	    0x59f2,     0x5f5f,     0x6519,     0x6b24,
	    0x7183,     0x783c,     0x7f53,     0x86cc,
	    0x8ead,     0x96fa,     0x9fba,     0xa8f2,
	    0xb2a7,     0xbce1,     0xc7a5,     0xd2fa,
	    0xdee8,     0xeb75,     0xf8aa,    0x1068e,
	   0x1152a,    0x12487,    0x134ad,    0x145a5,
	   0x1577b,    0x16a37,    0x17df5,    0x192bd,
	   0x1a890,    0x1bf7b,    0x1d78d,    0x1f0d1,
	   0x20b55,    0x22727,    0x24456,    0x262f2,
	   0x2830b
};

static uint tas3001c_mixer_tab[]={
	       0x0,      0x748,      0x9be,      0xbaf,
	     0xda4,      0xfb1,     0x11de,     0x1431,
	    0x16ad,     0x1959,     0x1c37,     0x1f4b,
	    0x2298,     0x2628,     0x29fb,     0x2e12,
	    0x327d,     0x3734,     0x3c47,     0x41b4,
	    0x4787,     0x4dbe,     0x546d,     0x5b86,
	    0x632e,     0x6b52,     0x7400,     0x7d54,
	    0x873b,     0x91c6,     0x9d1a,     0xa920,
	    0xb5e5,     0xc38c,     0xd21b,     0xe18f,
	    0xf1f5,    0x1036a,    0x1160f,    0x129d6,
	   0x13ed0,    0x1550c,    0x16ca0,    0x185c9,
	   0x1a07b,    0x1bcc3,    0x1dab9,    0x1fa75,
	   0x21c0f,    0x23fa3,    0x26552,    0x28d64,
	   0x2b7c9,    0x2e4a2,    0x31411,    0x3463b,
	   0x37b44,    0x3b353,    0x3ee94,    0x42d30,
	   0x46f55,    0x4b533,    0x4fefc,    0x54ce5,
	   0x59f25,    0x5f5f6,    0x65193,    0x6b23c,
	   0x71835,    0x783c3,    0x7f52c,    0x86cc0,
	   0x8eacc,    0x96fa5,    0x9fba0,    0xa8f1a,
	   0xb2a71,    0xbce0a,    0xc7a4a,    0xd2fa0,
	   0xdee7b,    0xeb752,    0xf8a9f,   0x1068e4,
	  0x1152a3,   0x12486a,   0x134ac8,   0x145a55,
	  0x1577ac,   0x16a370,   0x17df51,   0x192bc2,
	  0x1a88f8,   0x1bf7b7,   0x1d78c9,   0x1f0d04,
	  0x20b542,   0x227268,   0x244564,   0x262f26,
	  0x2830af
};

static uint tas3001c_treble_tab[]={
	      0x96,       0x95,       0x95,       0x94,
	      0x93,       0x92,       0x92,       0x91,
	      0x90,       0x90,       0x8f,       0x8e,
	      0x8d,       0x8d,       0x8c,       0x8b,
	      0x8a,       0x8a,       0x89,       0x88,
	      0x88,       0x87,       0x86,       0x85,
	      0x85,       0x84,       0x83,       0x83,
	      0x82,       0x81,       0x80,       0x80,
	      0x7f,       0x7e,       0x7e,       0x7d,
	      0x7c,       0x7b,       0x7b,       0x7a,
	      0x79,       0x78,       0x78,       0x77,
	      0x76,       0x76,       0x75,       0x74,
	      0x73,       0x73,       0x72,       0x71,
	      0x71,       0x70,       0x6e,       0x6d,
	      0x6d,       0x6c,       0x6b,       0x6a,
	      0x69,       0x68,       0x67,       0x66,
	      0x65,       0x63,       0x62,       0x62,
	      0x60,       0x5f,       0x5d,       0x5c,
	      0x5a,       0x58,       0x56,       0x55,
	      0x53,       0x51,       0x4f,       0x4c,
	      0x4a,       0x48,       0x45,       0x43,
	      0x40,       0x3d,       0x3a,       0x37,
	      0x35,       0x32,       0x2e,       0x2a,
	      0x27,       0x22,       0x1e,       0x1a,
	      0x15,       0x11,        0xc,        0x7,
	       0x1
};

static uint tas3001c_bass_tab[]={
	      0x86,       0x83,       0x81,       0x7f,
	      0x7d,       0x7b,       0x79,       0x78,
	      0x76,       0x75,       0x74,       0x72,
	      0x71,       0x6f,       0x6e,       0x6d,
	      0x6c,       0x6b,       0x69,       0x67,
	      0x65,       0x64,       0x61,       0x60,
	      0x5e,       0x5d,       0x5c,       0x5b,
	      0x5a,       0x59,       0x58,       0x57,
	      0x56,       0x55,       0x55,       0x54,
	      0x53,       0x52,       0x50,       0x4f,
	      0x4d,       0x4c,       0x4b,       0x49,
	      0x47,       0x45,       0x44,       0x42,
	      0x41,       0x3f,       0x3e,       0x3d,
	      0x3c,       0x3b,       0x39,       0x38,
	      0x37,       0x36,       0x35,       0x34,
	      0x33,       0x31,       0x30,       0x2f,
	      0x2e,       0x2c,       0x2b,       0x2b,
	      0x29,       0x28,       0x27,       0x26,
	      0x25,       0x24,       0x22,       0x21,
	      0x20,       0x1e,       0x1c,       0x19,
	      0x18,       0x18,       0x17,       0x16,
	      0x15,       0x14,       0x13,       0x12,
	      0x11,       0x10,        0xf,        0xe,
	       0xd,        0xb,        0xa,        0x9,
	       0x8,        0x6,        0x4,        0x2,
	       0x1
};

struct tas_gain_t tas3001c_gain = {
  master: tas3001c_master_tab,
  treble: tas3001c_treble_tab,
  bass:   tas3001c_bass_tab,
  mixer:  tas3001c_mixer_tab
};

struct tas_eq_pref_t *tas3001c_eq_prefs[]={
  &eqp_0e_2_1,
  &eqp_10_1_0,
  &eqp_15_2_1,
  &eqp_15_1_0,
  &eqp_0f_2_1,
  &eqp_0f_1_0,
  NULL
};




/*
 * Driver for the i2c/i2s based TA3004 sound chip used
 * on some Apple hardware. Also known as "snapper".
 *
 * Tobias Sargeant <tobias.sargeant@bigpond.com>
 * Based upon tas3001c.c by Christopher C. Chimelis <chris@debian.org>:
 *
 *   TODO:
 *   -----
 *   * Enable control over input line 2 (is this connected?)
 *   * Implement sleep support (at least mute everything and
 *   * set gains to minimum during sleep)
 *
 */

#include <linux/version.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/proc_fs.h>
#include <linux/ioport.h>
#include <linux/sysctl.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/soundcard.h>
#include <linux/interrupt.h>

#include <asm/uaccess.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/prom.h>

#include "dmasound.h"
#include "tas_common.h"
#include "tas3004.h"

#include "tas_ioctl.h"

/* #define DEBUG_DRCE */

#define TAS3004_BIQUAD_FILTER_COUNT  7
#define TAS3004_BIQUAD_CHANNEL_COUNT 2

#define VOL_DEFAULT	(100 * 4 / 5)
#define INPUT_DEFAULT	(100 * 4 / 5)
#define BASS_DEFAULT	(100 / 2)
#define TREBLE_DEFAULT	(100 / 2)

struct tas3004_data_t {
	struct tas_data_t super;
	int device_id;
	int output_id;
	int speaker_id;
	struct tas_drce_t drce_state;
};

#define MAKE_TIME(sec,usec) (((sec)<<12) + (50000+(usec/10)*(1<<12))/100000)

#define MAKE_RATIO(i,f) (((i)<<8) + ((500+(f)*(1<<8))/1000))


static const union tas_biquad_t
tas3004_eq_unity={
	buf: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 }
};


static const struct tas_drce_t
tas3004_drce_min={
	enable:		1,
	above:		{ val: MAKE_RATIO(16,0),	expand:0 },
	below:		{ val: MAKE_RATIO(2,0),		expand:0 },
	threshold:	-0x59a0,
	energy:		MAKE_TIME(0,  1700),
	attack:		MAKE_TIME(0,  1700),
	decay:		MAKE_TIME(0,  1700)
};


static const struct tas_drce_t
tas3004_drce_max={
	enable:		1,
	above:		{ val: MAKE_RATIO(1,500),	expand:1 },
	below:		{ val: MAKE_RATIO(2,0),		expand:1 },
	threshold:	-0x0,
	energy:		MAKE_TIME(2,400000),
	attack:		MAKE_TIME(2,400000),
	decay:		MAKE_TIME(2,400000)
};


static const unsigned short time_constants[]={
	MAKE_TIME(0,  1700),
	MAKE_TIME(0,  3500),
	MAKE_TIME(0,  6700),
	MAKE_TIME(0, 13000),
	MAKE_TIME(0, 26000),
	MAKE_TIME(0, 53000),
	MAKE_TIME(0,106000),
	MAKE_TIME(0,212000),
	MAKE_TIME(0,425000),
	MAKE_TIME(0,850000),
	MAKE_TIME(1,700000),
	MAKE_TIME(2,400000),
};

static const unsigned short above_threshold_compression_ratio[]={
	MAKE_RATIO( 1, 70),
	MAKE_RATIO( 1,140),
	MAKE_RATIO( 1,230),
	MAKE_RATIO( 1,330),
	MAKE_RATIO( 1,450),
	MAKE_RATIO( 1,600),
	MAKE_RATIO( 1,780),
	MAKE_RATIO( 2,  0),
	MAKE_RATIO( 2,290),
	MAKE_RATIO( 2,670),
	MAKE_RATIO( 3,200),
	MAKE_RATIO( 4,  0),
	MAKE_RATIO( 5,330),
	MAKE_RATIO( 8,  0),
	MAKE_RATIO(16,  0),
};

static const unsigned short above_threshold_expansion_ratio[]={
	MAKE_RATIO(1, 60),
	MAKE_RATIO(1,130),
	MAKE_RATIO(1,190),
	MAKE_RATIO(1,250),
	MAKE_RATIO(1,310),
	MAKE_RATIO(1,380),
	MAKE_RATIO(1,440),
	MAKE_RATIO(1,500)
};

static const unsigned short below_threshold_compression_ratio[]={
	MAKE_RATIO(1, 70),
	MAKE_RATIO(1,140),
	MAKE_RATIO(1,230),
	MAKE_RATIO(1,330),
	MAKE_RATIO(1,450),
	MAKE_RATIO(1,600),
	MAKE_RATIO(1,780),
	MAKE_RATIO(2,  0)
};

static const unsigned short below_threshold_expansion_ratio[]={
	MAKE_RATIO(1, 60),
	MAKE_RATIO(1,130),
	MAKE_RATIO(1,190),
	MAKE_RATIO(1,250),
	MAKE_RATIO(1,310),
	MAKE_RATIO(1,380),
	MAKE_RATIO(1,440),
	MAKE_RATIO(1,500),
	MAKE_RATIO(1,560),
	MAKE_RATIO(1,630),
	MAKE_RATIO(1,690),
	MAKE_RATIO(1,750),
	MAKE_RATIO(1,810),
	MAKE_RATIO(1,880),
	MAKE_RATIO(1,940),
	MAKE_RATIO(2,  0)
};

static inline int
search(	unsigned short val,
	const unsigned short *arr,
	const int arrsize) {
	/*
	 * This could be a binary search, but for small tables,
	 * a linear search is likely to be faster
	 */

	int i;

	for (i=0; i < arrsize; i++)
		if (arr[i] >= val)
			goto _1;
	return arrsize-1;
 _1:
	if (i == 0)
		return 0;
	return (arr[i]-val < val-arr[i-1]) ? i : i-1;
}

#define SEARCH(a, b) search(a, b, ARRAY_SIZE(b))

static inline int
time_index(unsigned short time) {
	return SEARCH(time, time_constants);
}


static inline int
above_threshold_compression_index(unsigned short ratio) {
	return SEARCH(ratio, above_threshold_compression_ratio);
}


static inline int
above_threshold_expansion_index(unsigned short ratio) {
	return SEARCH(ratio, above_threshold_expansion_ratio);
}


static inline int
below_threshold_compression_index(unsigned short ratio) {
	return SEARCH(ratio, below_threshold_compression_ratio);
}


static inline int
below_threshold_expansion_index(unsigned short ratio) {
	return SEARCH(ratio, below_threshold_expansion_ratio);
}


static inline unsigned char db_to_regval(short db) {
	int r=0;

	r=(db+0x59a0) / 0x60;

	if (r < 0x91) return 0x91;
	if (r > 0xef) return 0xef;
	return r;
}


static inline short quantize_db(short db) {
	return db_to_regval(db) * 0x60 - 0x59a0;
}


static inline int
register_width(enum tas3004_reg_t r)
{
	switch(r) {
	case TAS3004_REG_MCR:
 	case TAS3004_REG_TREBLE:
	case TAS3004_REG_BASS:
	case TAS3004_REG_ANALOG_CTRL:
	case TAS3004_REG_TEST1:
	case TAS3004_REG_TEST2:
	case TAS3004_REG_MCR2:
		return 1;

	case TAS3004_REG_LEFT_LOUD_BIQUAD_GAIN:
	case TAS3004_REG_RIGHT_LOUD_BIQUAD_GAIN:
		return 3;

	case TAS3004_REG_DRC:
	case TAS3004_REG_VOLUME:
		return 6;

	case TAS3004_REG_LEFT_MIXER:
	case TAS3004_REG_RIGHT_MIXER:
		return 9;

	case TAS3004_REG_TEST:
		return 10;

	case TAS3004_REG_LEFT_BIQUAD0:
	case TAS3004_REG_LEFT_BIQUAD1:
	case TAS3004_REG_LEFT_BIQUAD2:
	case TAS3004_REG_LEFT_BIQUAD3:
	case TAS3004_REG_LEFT_BIQUAD4:
	case TAS3004_REG_LEFT_BIQUAD5:
	case TAS3004_REG_LEFT_BIQUAD6:

	case TAS3004_REG_RIGHT_BIQUAD0:
	case TAS3004_REG_RIGHT_BIQUAD1:
	case TAS3004_REG_RIGHT_BIQUAD2:
	case TAS3004_REG_RIGHT_BIQUAD3:
	case TAS3004_REG_RIGHT_BIQUAD4:
	case TAS3004_REG_RIGHT_BIQUAD5:
	case TAS3004_REG_RIGHT_BIQUAD6:

	case TAS3004_REG_LEFT_LOUD_BIQUAD:
	case TAS3004_REG_RIGHT_LOUD_BIQUAD:
		return 15;

	default:
		return 0;
	}
}


static int
tas3004_write_register(	struct tas3004_data_t *self,
			enum tas3004_reg_t reg_num,
			char *data,
			uint write_mode)
{
	if (reg_num==TAS3004_REG_MCR ||
	    reg_num==TAS3004_REG_BASS ||
	    reg_num==TAS3004_REG_TREBLE) {
		return tas_write_byte_register(&self->super,
					       (uint)reg_num,
					       *data,
					       write_mode);
	} else {
		return tas_write_register(&self->super,
					  (uint)reg_num,
					  register_width(reg_num),
					  data,
					  write_mode);
	}
}


static int
tas3004_sync_register(	struct tas3004_data_t *self,
			enum tas3004_reg_t reg_num)
{
	if (reg_num==TAS3004_REG_MCR ||
	    reg_num==TAS3004_REG_BASS ||
	    reg_num==TAS3004_REG_TREBLE) {
		return tas_sync_byte_register(&self->super,
					      (uint)reg_num,
					      register_width(reg_num));
	} else {
		return tas_sync_register(&self->super,
					 (uint)reg_num,
					 register_width(reg_num));
	}
}


static int
tas3004_read_register(	struct tas3004_data_t *self,
			enum tas3004_reg_t reg_num,
			char *data,
			uint write_mode)
{
	return tas_read_register(&self->super,
				 (uint)reg_num,
				 register_width(reg_num),
				 data);
}


static inline int
tas3004_fast_load(struct tas3004_data_t *self, int fast)
{
	if (fast)
		self->super.shadow[TAS3004_REG_MCR][0] |= 0x80;
	else
		self->super.shadow[TAS3004_REG_MCR][0] &= 0x7f;
	return tas3004_sync_register(self,TAS3004_REG_MCR);
}


static uint
tas3004_supported_mixers(struct tas3004_data_t *self)
{
	return SOUND_MASK_VOLUME |
		SOUND_MASK_PCM |
		SOUND_MASK_ALTPCM |
		SOUND_MASK_IMIX |
		SOUND_MASK_TREBLE |
		SOUND_MASK_BASS;
}


static int
tas3004_mixer_is_stereo(struct tas3004_data_t *self, int mixer)
{
	switch(mixer) {
	case SOUND_MIXER_VOLUME:
	case SOUND_MIXER_PCM:
	case SOUND_MIXER_ALTPCM:
	case SOUND_MIXER_IMIX:
		return 1;
	default:
		return 0;
	}
}


static uint
tas3004_stereo_mixers(struct tas3004_data_t *self)
{
	uint r = tas3004_supported_mixers(self);
	uint i;
	
	for (i=1; i<SOUND_MIXER_NRDEVICES; i++)
		if (r&(1<<i) && !tas3004_mixer_is_stereo(self,i))
			r &= ~(1<<i);
	return r;
}


static int
tas3004_get_mixer_level(struct tas3004_data_t *self, int mixer, uint *level)
{
	if (!self)
		return -1;

	*level = self->super.mixer[mixer];

	return 0;
}


static int
tas3004_set_mixer_level(struct tas3004_data_t *self, int mixer, uint level)
{
	int rc;
	tas_shadow_t *shadow;
	uint temp;
	uint offset=0;

	if (!self)
		return -1;

	shadow = self->super.shadow;

	if (!tas3004_mixer_is_stereo(self,mixer))
		level = tas_mono_to_stereo(level);
	switch(mixer) {
	case SOUND_MIXER_VOLUME:
		temp = tas3004_gain.master[level&0xff];
		SET_4_20(shadow[TAS3004_REG_VOLUME], 0, temp);
		temp = tas3004_gain.master[(level>>8)&0xff];
		SET_4_20(shadow[TAS3004_REG_VOLUME], 3, temp);
		rc = tas3004_sync_register(self,TAS3004_REG_VOLUME);
		break;
	case SOUND_MIXER_IMIX:
		offset += 3;
	case SOUND_MIXER_ALTPCM:
		offset += 3;
	case SOUND_MIXER_PCM:
		/*
		 * Don't load these in fast mode. The documentation
		 * says it can be done in either mode, but testing it
		 * shows that fast mode produces ugly clicking.
		*/
		/* tas3004_fast_load(self,1); */
		temp = tas3004_gain.mixer[level&0xff];
		SET_4_20(shadow[TAS3004_REG_LEFT_MIXER], offset, temp);
		temp = tas3004_gain.mixer[(level>>8)&0xff];
		SET_4_20(shadow[TAS3004_REG_RIGHT_MIXER], offset, temp);
		rc = tas3004_sync_register(self,TAS3004_REG_LEFT_MIXER);
		if (rc == 0)
			rc=tas3004_sync_register(self,TAS3004_REG_RIGHT_MIXER);
		/* tas3004_fast_load(self,0); */
		break;
	case SOUND_MIXER_TREBLE:
		temp = tas3004_gain.treble[level&0xff];
		shadow[TAS3004_REG_TREBLE][0]=temp&0xff;
		rc = tas3004_sync_register(self,TAS3004_REG_TREBLE);
		break;
	case SOUND_MIXER_BASS:
		temp = tas3004_gain.bass[level&0xff];
		shadow[TAS3004_REG_BASS][0]=temp&0xff;
		rc = tas3004_sync_register(self,TAS3004_REG_BASS);
		break;
	default:
		rc = -1;
		break;
	}
	if (rc < 0)
		return rc;
	self->super.mixer[mixer] = level;
	
	return 0;
}


static int
tas3004_leave_sleep(struct tas3004_data_t *self)
{
	unsigned char mcr = (1<<6)+(2<<4)+(2<<2);

	if (!self)
		return -1;

	/* Make sure something answers on the i2c bus */
	if (tas3004_write_register(self, TAS3004_REG_MCR, &mcr,
	    WRITE_NORMAL | FORCE_WRITE) < 0)
		return -1;

	tas3004_fast_load(self, 1);

	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD0);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD1);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD2);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD3);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD4);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD5);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD6);

	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD0);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD1);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD2);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD3);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD4);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD5);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD6);

	tas3004_fast_load(self, 0);

	(void)tas3004_sync_register(self,TAS3004_REG_VOLUME);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_MIXER);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_MIXER);
	(void)tas3004_sync_register(self,TAS3004_REG_TREBLE);
	(void)tas3004_sync_register(self,TAS3004_REG_BASS);

	return 0;
}


static int
tas3004_enter_sleep(struct tas3004_data_t *self)
{
	if (!self)
		return -1; 
	return 0;
}


static int
tas3004_sync_biquad(	struct tas3004_data_t *self,
			u_int channel,
			u_int filter)
{
	enum tas3004_reg_t reg;

	if (channel >= TAS3004_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3004_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3004_REG_RIGHT_BIQUAD0 : TAS3004_REG_LEFT_BIQUAD0 ) + filter;

	return tas3004_sync_register(self,reg);
}


static int
tas3004_write_biquad_shadow(	struct tas3004_data_t *self,
				u_int channel,
				u_int filter,
				const union tas_biquad_t *biquad)
{
	tas_shadow_t *shadow=self->super.shadow;
	enum tas3004_reg_t reg;

	if (channel >= TAS3004_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3004_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3004_REG_RIGHT_BIQUAD0 : TAS3004_REG_LEFT_BIQUAD0 ) + filter;

	SET_4_20(shadow[reg], 0,biquad->coeff.b0);
	SET_4_20(shadow[reg], 3,biquad->coeff.b1);
	SET_4_20(shadow[reg], 6,biquad->coeff.b2);
	SET_4_20(shadow[reg], 9,biquad->coeff.a1);
	SET_4_20(shadow[reg],12,biquad->coeff.a2);

	return 0;
}


static int
tas3004_write_biquad(	struct tas3004_data_t *self,
			u_int channel,
			u_int filter,
			const union tas_biquad_t *biquad)
{
	int rc;

	rc=tas3004_write_biquad_shadow(self, channel, filter, biquad);
	if (rc < 0) return rc;

	return tas3004_sync_biquad(self, channel, filter);
}


static int
tas3004_write_biquad_list(	struct tas3004_data_t *self,
				u_int filter_count,
				u_int flags,
				struct tas_biquad_ctrl_t *biquads)
{
	int i;
	int rc;

	if (flags & TAS_BIQUAD_FAST_LOAD) tas3004_fast_load(self,1);

	for (i=0; i<filter_count; i++) {
		rc=tas3004_write_biquad(self,
					biquads[i].channel,
					biquads[i].filter,
					&biquads[i].data);
		if (rc < 0) break;
	}

	if (flags & TAS_BIQUAD_FAST_LOAD) tas3004_fast_load(self,0);

	return rc;
}


static int
tas3004_read_biquad(	struct tas3004_data_t *self,
			u_int channel,
			u_int filter,
			union tas_biquad_t *biquad)
{
	tas_shadow_t *shadow=self->super.shadow;
	enum tas3004_reg_t reg;

	if (channel >= TAS3004_BIQUAD_CHANNEL_COUNT ||
	    filter  >= TAS3004_BIQUAD_FILTER_COUNT) return -EINVAL;

	reg=( channel ? TAS3004_REG_RIGHT_BIQUAD0 : TAS3004_REG_LEFT_BIQUAD0 ) + filter;

	biquad->coeff.b0=GET_4_20(shadow[reg], 0);
	biquad->coeff.b1=GET_4_20(shadow[reg], 3);
	biquad->coeff.b2=GET_4_20(shadow[reg], 6);
	biquad->coeff.a1=GET_4_20(shadow[reg], 9);
	biquad->coeff.a2=GET_4_20(shadow[reg],12);
	
	return 0;	
}


static int
tas3004_eq_rw(	struct tas3004_data_t *self,
		u_int cmd,
		u_long arg)
{
	int rc;
	struct tas_biquad_ctrl_t biquad;

	if (copy_from_user((void *)&biquad, (const void *)arg, sizeof(struct tas_biquad_ctrl_t))) {
		return -EFAULT;
	}

	if (cmd & SIOC_IN) {
		rc=tas3004_write_biquad(self, biquad.channel, biquad.filter, &biquad.data);
		if (rc != 0) return rc;
	}

	if (cmd & SIOC_OUT) {
		rc=tas3004_read_biquad(self, biquad.channel, biquad.filter, &biquad.data);
		if (rc != 0) return rc;

		if (copy_to_user((void *)arg, (const void *)&biquad, sizeof(struct tas_biquad_ctrl_t))) {
			return -EFAULT;
		}

	}
	return 0;
}


static int
tas3004_eq_list_rw(	struct tas3004_data_t *self,
			u_int cmd,
			u_long arg)
{
	int rc = 0;
	int filter_count;
	int flags;
	int i,j;
	char sync_required[TAS3004_BIQUAD_CHANNEL_COUNT][TAS3004_BIQUAD_FILTER_COUNT];
	struct tas_biquad_ctrl_t biquad;

	memset(sync_required,0,sizeof(sync_required));

	if (copy_from_user((void *)&filter_count,
			   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t,filter_count),
			   sizeof(int))) {
		return -EFAULT;
	}

	if (copy_from_user((void *)&flags,
			   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t,flags),
			   sizeof(int))) {
		return -EFAULT;
	}

	if (cmd & SIOC_IN) {
	}

	for (i=0; i < filter_count; i++) {
		if (copy_from_user((void *)&biquad,
				   (const void *)arg + offsetof(struct tas_biquad_ctrl_list_t, biquads[i]),
				   sizeof(struct tas_biquad_ctrl_t))) {
			return -EFAULT;
		}

		if (cmd & SIOC_IN) {
			sync_required[biquad.channel][biquad.filter]=1;
			rc=tas3004_write_biquad_shadow(self, biquad.channel, biquad.filter, &biquad.data);
			if (rc != 0) return rc;
		}

		if (cmd & SIOC_OUT) {
			rc=tas3004_read_biquad(self, biquad.channel, biquad.filter, &biquad.data);
			if (rc != 0) return rc;

			if (copy_to_user((void *)arg + offsetof(struct tas_biquad_ctrl_list_t, biquads[i]),
					 (const void *)&biquad,
					 sizeof(struct tas_biquad_ctrl_t))) {
				return -EFAULT;
			}
		}
	}

	if (cmd & SIOC_IN) {
		/*
		 * This is OK for the tas3004. For the
		 * tas3001c, going into fast load mode causes
		 * the treble and bass to be reset to 0dB, and
		 * volume controls to be muted.
		 */
		if (flags & TAS_BIQUAD_FAST_LOAD) tas3004_fast_load(self,1);
		for (i=0; i<TAS3004_BIQUAD_CHANNEL_COUNT; i++) {
			for (j=0; j<TAS3004_BIQUAD_FILTER_COUNT; j++) {
				if (sync_required[i][j]) {
					rc=tas3004_sync_biquad(self, i, j);
					if (rc < 0) goto out;
				}
			}
		}
	out:
		if (flags & TAS_BIQUAD_FAST_LOAD)
			tas3004_fast_load(self,0);
	}

	return rc;
}


static int
tas3004_update_drce(	struct tas3004_data_t *self,
			int flags,
			struct tas_drce_t *drce)
{
	tas_shadow_t *shadow;
	int i;
	shadow=self->super.shadow;

	if (flags & TAS_DRCE_ABOVE_RATIO) {
		self->drce_state.above.expand = drce->above.expand;
		if (drce->above.val == (1<<8)) {
			self->drce_state.above.val = 1<<8;
			shadow[TAS3004_REG_DRC][0] = 0x02;
					
		} else if (drce->above.expand) {
			i=above_threshold_expansion_index(drce->above.val);
			self->drce_state.above.val=above_threshold_expansion_ratio[i];
			shadow[TAS3004_REG_DRC][0] = 0x0a + (i<<3);
		} else {
			i=above_threshold_compression_index(drce->above.val);
			self->drce_state.above.val=above_threshold_compression_ratio[i];
			shadow[TAS3004_REG_DRC][0] = 0x08 + (i<<3);
		}
	}

	if (flags & TAS_DRCE_BELOW_RATIO) {
		self->drce_state.below.expand = drce->below.expand;
		if (drce->below.val == (1<<8)) {
			self->drce_state.below.val = 1<<8;
			shadow[TAS3004_REG_DRC][1] = 0x02;
					
		} else if (drce->below.expand) {
			i=below_threshold_expansion_index(drce->below.val);
			self->drce_state.below.val=below_threshold_expansion_ratio[i];
			shadow[TAS3004_REG_DRC][1] = 0x08 + (i<<3);
		} else {
			i=below_threshold_compression_index(drce->below.val);
			self->drce_state.below.val=below_threshold_compression_ratio[i];
			shadow[TAS3004_REG_DRC][1] = 0x0a + (i<<3);
		}
	}

	if (flags & TAS_DRCE_THRESHOLD) {
		self->drce_state.threshold=quantize_db(drce->threshold);
		shadow[TAS3004_REG_DRC][2] = db_to_regval(self->drce_state.threshold);
	}

	if (flags & TAS_DRCE_ENERGY) {
		i=time_index(drce->energy);
		self->drce_state.energy=time_constants[i];
		shadow[TAS3004_REG_DRC][3] = 0x40 + (i<<4);
	}

	if (flags & TAS_DRCE_ATTACK) {
		i=time_index(drce->attack);
		self->drce_state.attack=time_constants[i];
		shadow[TAS3004_REG_DRC][4] = 0x40 + (i<<4);
	}

	if (flags & TAS_DRCE_DECAY) {
		i=time_index(drce->decay);
		self->drce_state.decay=time_constants[i];
		shadow[TAS3004_REG_DRC][5] = 0x40 + (i<<4);
	}

	if (flags & TAS_DRCE_ENABLE) {
		self->drce_state.enable = drce->enable;
	}

	if (!self->drce_state.enable) {
		shadow[TAS3004_REG_DRC][0] |= 0x01;
	}

#ifdef DEBUG_DRCE
	printk("DRCE: set [ ENABLE:%x ABOVE:%x/%x BELOW:%x/%x THRESH:%x ENERGY:%x ATTACK:%x DECAY:%x\n",
	       self->drce_state.enable,
	       self->drce_state.above.expand,self->drce_state.above.val,
	       self->drce_state.below.expand,self->drce_state.below.val,
	       self->drce_state.threshold,
	       self->drce_state.energy,
	       self->drce_state.attack,
	       self->drce_state.decay);

	printk("DRCE: reg [ %02x %02x %02x %02x %02x %02x ]\n",
	       (unsigned char)shadow[TAS3004_REG_DRC][0],
	       (unsigned char)shadow[TAS3004_REG_DRC][1],
	       (unsigned char)shadow[TAS3004_REG_DRC][2],
	       (unsigned char)shadow[TAS3004_REG_DRC][3],
	       (unsigned char)shadow[TAS3004_REG_DRC][4],
	       (unsigned char)shadow[TAS3004_REG_DRC][5]);
#endif

	return tas3004_sync_register(self, TAS3004_REG_DRC);
}


static int
tas3004_drce_rw(	struct tas3004_data_t *self,
			u_int cmd,
			u_long arg)
{
	int rc;
	struct tas_drce_ctrl_t drce_ctrl;

	if (copy_from_user((void *)&drce_ctrl,
			   (const void *)arg,
			   sizeof(struct tas_drce_ctrl_t))) {
		return -EFAULT;
	}

#ifdef DEBUG_DRCE
	printk("DRCE: input [ FLAGS:%x ENABLE:%x ABOVE:%x/%x BELOW:%x/%x THRESH:%x ENERGY:%x ATTACK:%x DECAY:%x\n",
	       drce_ctrl.flags,
	       drce_ctrl.data.enable,
	       drce_ctrl.data.above.expand,drce_ctrl.data.above.val,
	       drce_ctrl.data.below.expand,drce_ctrl.data.below.val,
	       drce_ctrl.data.threshold,
	       drce_ctrl.data.energy,
	       drce_ctrl.data.attack,
	       drce_ctrl.data.decay);
#endif

	if (cmd & SIOC_IN) {
		rc = tas3004_update_drce(self, drce_ctrl.flags, &drce_ctrl.data);
		if (rc < 0) return rc;
	}

	if (cmd & SIOC_OUT) {
		if (drce_ctrl.flags & TAS_DRCE_ENABLE)
			drce_ctrl.data.enable = self->drce_state.enable;
		if (drce_ctrl.flags & TAS_DRCE_ABOVE_RATIO)
			drce_ctrl.data.above = self->drce_state.above;
		if (drce_ctrl.flags & TAS_DRCE_BELOW_RATIO)
			drce_ctrl.data.below = self->drce_state.below;
		if (drce_ctrl.flags & TAS_DRCE_THRESHOLD)
			drce_ctrl.data.threshold = self->drce_state.threshold;
		if (drce_ctrl.flags & TAS_DRCE_ENERGY)
			drce_ctrl.data.energy = self->drce_state.energy;
		if (drce_ctrl.flags & TAS_DRCE_ATTACK)
			drce_ctrl.data.attack = self->drce_state.attack;
		if (drce_ctrl.flags & TAS_DRCE_DECAY)
			drce_ctrl.data.decay = self->drce_state.decay;

		if (copy_to_user((void *)arg,
				 (const void *)&drce_ctrl,
				 sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}
	}

	return 0;
}


static void
tas3004_update_device_parameters(struct tas3004_data_t *self)
{
	char data;
	int i;

	if (!self) return;

	if (self->output_id == TAS_OUTPUT_HEADPHONES) {
		/* turn on allPass when headphones are plugged in */
		data = 0x02;
	} else {
		data = 0x00;
	}

	tas3004_write_register(self, TAS3004_REG_MCR2, &data, WRITE_NORMAL | FORCE_WRITE);

	for (i=0; tas3004_eq_prefs[i]; i++) {
		struct tas_eq_pref_t *eq = tas3004_eq_prefs[i];

		if (eq->device_id == self->device_id &&
		    (eq->output_id == 0 || eq->output_id == self->output_id) &&
		    (eq->speaker_id == 0 || eq->speaker_id == self->speaker_id)) {

			tas3004_update_drce(self, TAS_DRCE_ALL, eq->drce);
			tas3004_write_biquad_list(self, eq->filter_count, TAS_BIQUAD_FAST_LOAD, eq->biquads);

			break;
		}
	}
}

static void
tas3004_device_change_handler(void *self)
{
	if (!self) return;

	tas3004_update_device_parameters((struct tas3004_data_t *)self);
}

static struct tq_struct device_change_task;

static int
tas3004_output_device_change(	struct tas3004_data_t *self,
				int device_id,
				int output_id,
				int speaker_id)
{
	self->device_id=device_id;
	self->output_id=output_id;
	self->speaker_id=speaker_id;

	schedule_task(&device_change_task);

	return 0;
}


static int
tas3004_device_ioctl(	struct tas3004_data_t *self,
			u_int cmd,
			u_long arg)
{
	switch (cmd) {
	case TAS_READ_EQ:
	case TAS_WRITE_EQ:
		return tas3004_eq_rw(self, cmd, arg);

	case TAS_READ_EQ_LIST:
	case TAS_WRITE_EQ_LIST:
		return tas3004_eq_list_rw(self, cmd, arg);

	case TAS_READ_EQ_FILTER_COUNT:
		put_user(TAS3004_BIQUAD_FILTER_COUNT, (uint *)(arg));
		return 0;

	case TAS_READ_EQ_CHANNEL_COUNT:
		put_user(TAS3004_BIQUAD_CHANNEL_COUNT, (uint *)(arg));
		return 0;

	case TAS_READ_DRCE:
	case TAS_WRITE_DRCE:
		return tas3004_drce_rw(self, cmd, arg);

	case TAS_READ_DRCE_CAPS:
		put_user(TAS_DRCE_ENABLE         |
			 TAS_DRCE_ABOVE_RATIO    |
			 TAS_DRCE_BELOW_RATIO    |
			 TAS_DRCE_THRESHOLD      |
			 TAS_DRCE_ENERGY         |
			 TAS_DRCE_ATTACK         |
			 TAS_DRCE_DECAY,
			 (uint *)(arg));
		return 0;

	case TAS_READ_DRCE_MIN:
	case TAS_READ_DRCE_MAX: {
		struct tas_drce_ctrl_t drce_ctrl;
		const struct tas_drce_t *drce_copy;

		if (copy_from_user((void *)&drce_ctrl,
				   (const void *)arg,
				   sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}

		if (cmd == TAS_READ_DRCE_MIN) {
			drce_copy=&tas3004_drce_min;
		} else {
			drce_copy=&tas3004_drce_max;
		}

		if (drce_ctrl.flags & TAS_DRCE_ABOVE_RATIO) {
			drce_ctrl.data.above=drce_copy->above;
		}
		if (drce_ctrl.flags & TAS_DRCE_BELOW_RATIO) {
			drce_ctrl.data.below=drce_copy->below;
		}
		if (drce_ctrl.flags & TAS_DRCE_THRESHOLD) {
			drce_ctrl.data.threshold=drce_copy->threshold;
		}
		if (drce_ctrl.flags & TAS_DRCE_ENERGY) {
			drce_ctrl.data.energy=drce_copy->energy;
		}
		if (drce_ctrl.flags & TAS_DRCE_ATTACK) {
			drce_ctrl.data.attack=drce_copy->attack;
		}
		if (drce_ctrl.flags & TAS_DRCE_DECAY) {
			drce_ctrl.data.decay=drce_copy->decay;
		}

		if (copy_to_user((void *)arg,
				 (const void *)&drce_ctrl,
				 sizeof(struct tas_drce_ctrl_t))) {
			return -EFAULT;
		}
	}
	}

	return -EINVAL;
}


static int
tas3004_init_mixer(struct tas3004_data_t *self)
{
	unsigned char mcr = (1<<6)+(2<<4)+(2<<2);

	/* Make sure something answers on the i2c bus */
	if (tas3004_write_register(self, TAS3004_REG_MCR, &mcr,
	    WRITE_NORMAL | FORCE_WRITE) < 0)
		return -1;

	tas3004_fast_load(self, 1);

	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD0);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD1);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD2);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD3);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD4);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD5);
	(void)tas3004_sync_register(self,TAS3004_REG_RIGHT_BIQUAD6);

	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD0);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD1);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD2);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD3);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD4);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD5);
	(void)tas3004_sync_register(self,TAS3004_REG_LEFT_BIQUAD6);

	tas3004_sync_register(self, TAS3004_REG_DRC);

	tas3004_sync_register(self, TAS3004_REG_MCR2);

	tas3004_fast_load(self, 0);

	tas3004_set_mixer_level(self, SOUND_MIXER_VOLUME, VOL_DEFAULT<<8 | VOL_DEFAULT);
	tas3004_set_mixer_level(self, SOUND_MIXER_PCM, INPUT_DEFAULT<<8 | INPUT_DEFAULT);
	tas3004_set_mixer_level(self, SOUND_MIXER_ALTPCM, 0);
	tas3004_set_mixer_level(self, SOUND_MIXER_IMIX, 0);

	tas3004_set_mixer_level(self, SOUND_MIXER_BASS, BASS_DEFAULT);
	tas3004_set_mixer_level(self, SOUND_MIXER_TREBLE, TREBLE_DEFAULT);

	return 0;
}


static int
tas3004_uninit_mixer(struct tas3004_data_t *self)
{
	tas3004_set_mixer_level(self, SOUND_MIXER_VOLUME, 0);
	tas3004_set_mixer_level(self, SOUND_MIXER_PCM, 0);
	tas3004_set_mixer_level(self, SOUND_MIXER_ALTPCM, 0);
	tas3004_set_mixer_level(self, SOUND_MIXER_IMIX, 0);

	tas3004_set_mixer_level(self, SOUND_MIXER_BASS, 0);
	tas3004_set_mixer_level(self, SOUND_MIXER_TREBLE, 0);

	return 0;
}


static int
tas3004_init(struct i2c_client *client)
{
	char drce_init[]={ 0x69, 0x22, 0x9f, 0xb0, 0x60, 0xa0 };
	char mcr2 = 0;

	struct tas3004_data_t *self;
	int i, j;

	self = kmalloc(sizeof(struct tas3004_data_t) +
			TAS3004_REG_MAX * sizeof(tas_shadow_t),
			GFP_KERNEL);
	if (self == NULL)
		return -ENOMEM;

	memset(self,
	       0,
	       sizeof(struct tas3004_data_t) +
	       TAS3004_REG_MAX * sizeof(tas_shadow_t));

	client->data = (void *)self;

	self->super.client = client;
	self->super.shadow = (tas_shadow_t *)(self+1);

	self->output_id=TAS_OUTPUT_HEADPHONES;
	self->device_id=0;
	self->speaker_id=0;

	for (i=0; i<TAS3004_BIQUAD_CHANNEL_COUNT; i++) {
		for (j=0; j<TAS3004_BIQUAD_FILTER_COUNT; j++) {
			tas3004_write_biquad_shadow(self, i, j, &tas3004_eq_unity);
		}
	}

	tas3004_write_register(self, TAS3004_REG_MCR2, &mcr2, WRITE_SHADOW);
	tas3004_write_register(self, TAS3004_REG_DRC, drce_init, WRITE_SHADOW);

	INIT_TQUEUE(&device_change_task, tas3004_device_change_handler, (void *)self);

	return 0;
}


static void 
tas3004_uninit(struct tas3004_data_t *self)
{
	tas3004_uninit_mixer(self);
	kfree(self);
}


struct tas_driver_hooks_t tas3004_hooks = {
	init:                   (tas_hook_init_t)tas3004_init,
	post_init:              (tas_hook_post_init_t)tas3004_init_mixer,
	uninit:                 (tas_hook_uninit_t)tas3004_uninit,

	get_mixer_level:        (tas_hook_get_mixer_level_t)tas3004_get_mixer_level,
	set_mixer_level:        (tas_hook_set_mixer_level_t)tas3004_set_mixer_level,

	enter_sleep:            (tas_hook_enter_sleep_t)tas3004_enter_sleep,
	leave_sleep:            (tas_hook_leave_sleep_t)tas3004_leave_sleep,

	supported_mixers:       (tas_hook_supported_mixers_t)tas3004_supported_mixers,
	mixer_is_stereo:        (tas_hook_mixer_is_stereo_t)tas3004_mixer_is_stereo,
	stereo_mixers:          (tas_hook_stereo_mixers_t)tas3004_stereo_mixers,

	output_device_change:   (tas_hook_output_device_change_t)tas3004_output_device_change,

	device_ioctl:           (tas_hook_device_ioctl_t)tas3004_device_ioctl
};

/*
 * Local Variables:
 * tab-width: 8
 * indent-tabs-mode: t
 * c-basic-offset: 8
 * End:
 */




/*
 * Header file for the i2c/i2s based TA3004 sound chip used
 * on some Apple hardware. Also known as "tumbler".
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive
 *  for more details.
 *
 * Written by Christopher C. Chimelis <chris@debian.org>
 */

#ifndef _TAS3004_H_
#define _TAS3004_H_

#include <linux/types.h>

#include "tas_common.h"
#include "tas_eq_prefs.h"

/*
 * Macros that correspond to the registers that we write to
 * when setting the various values.
 */

#define TAS3004_VERSION	        "0.3"
#define TAS3004_DATE	        "20011214"

#define I2C_DRIVERNAME_TAS3004 "TAS3004 driver V " TAS3004_VERSION
#define I2C_DRIVERID_TAS3004    (I2C_DRIVERID_TAS_BASE+1)

extern  struct tas_driver_hooks_t tas3004_hooks;
extern struct tas_gain_t tas3004_gain;
extern struct tas_eq_pref_t *tas3004_eq_prefs[];

enum tas3004_reg_t {
  TAS3004_REG_MCR                    = 0x01,
  TAS3004_REG_DRC                    = 0x02,

  TAS3004_REG_VOLUME                 = 0x04,
  TAS3004_REG_TREBLE                 = 0x05,
  TAS3004_REG_BASS                   = 0x06,
  TAS3004_REG_LEFT_MIXER             = 0x07,
  TAS3004_REG_RIGHT_MIXER            = 0x08,

  TAS3004_REG_LEFT_BIQUAD0           = 0x0a,
  TAS3004_REG_LEFT_BIQUAD1           = 0x0b,
  TAS3004_REG_LEFT_BIQUAD2           = 0x0c,
  TAS3004_REG_LEFT_BIQUAD3           = 0x0d,
  TAS3004_REG_LEFT_BIQUAD4           = 0x0e,
  TAS3004_REG_LEFT_BIQUAD5           = 0x0f,
  TAS3004_REG_LEFT_BIQUAD6           = 0x10,
  
  TAS3004_REG_RIGHT_BIQUAD0          = 0x13,
  TAS3004_REG_RIGHT_BIQUAD1          = 0x14,
  TAS3004_REG_RIGHT_BIQUAD2          = 0x15,
  TAS3004_REG_RIGHT_BIQUAD3          = 0x16,
  TAS3004_REG_RIGHT_BIQUAD4          = 0x17,
  TAS3004_REG_RIGHT_BIQUAD5          = 0x18,
  TAS3004_REG_RIGHT_BIQUAD6          = 0x19,

  TAS3004_REG_LEFT_LOUD_BIQUAD       = 0x21,
  TAS3004_REG_RIGHT_LOUD_BIQUAD      = 0x22,

  TAS3004_REG_LEFT_LOUD_BIQUAD_GAIN  = 0x23,
  TAS3004_REG_RIGHT_LOUD_BIQUAD_GAIN = 0x24,

  TAS3004_REG_TEST                   = 0x29,

  TAS3004_REG_ANALOG_CTRL            = 0x40,
  TAS3004_REG_TEST1                  = 0x41,
  TAS3004_REG_TEST2                  = 0x42,
  TAS3004_REG_MCR2                   = 0x43,

  TAS3004_REG_MAX                    = 0x44
};

#endif /* _TAS3004_H_ */




#include "tas3004.h"
#include "tas_eq_prefs.h"

static struct tas_drce_t eqp_17_1_0_drce={
    enable:    1,
    above:     { val: 3.0 * (1<<8), expand: 0 },
    below:     { val: 1.0 * (1<<8), expand: 0 },
    threshold: -19.12  * (1<<8),
    energy:    2.4     * (1<<12),
    attack:    0.013   * (1<<12),
    decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_17_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0fd0d4, 0xe05e56, 0x0fd0d4, 0xe05ee1, 0x0fa234 } } },
  { channel: 0, filter: 1, data: { coeff: { 0x0910d7, 0x088e1a, 0x030651, 0x01dcb1, 0x02c892 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0ff895, 0xe0970b, 0x0f7f00, 0xe0970b, 0x0f7795 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0fd1c4, 0xe1ac22, 0x0ec8cf, 0xe1ac22, 0x0e9a94 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0f7c1c, 0xe3cc03, 0x0df786, 0xe3cc03, 0x0d73a2 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x11fb92, 0xf5a1a0, 0x073cd2, 0xf5a1a0, 0x093865 } } },
  { channel: 0, filter: 6, data: { coeff: { 0x0e17a9, 0x068b6c, 0x08a0e5, 0x068b6c, 0x06b88e } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0fd0d4, 0xe05e56, 0x0fd0d4, 0xe05ee1, 0x0fa234 } } },
  { channel: 1, filter: 1, data: { coeff: { 0x0910d7, 0x088e1a, 0x030651, 0x01dcb1, 0x02c892 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0ff895, 0xe0970b, 0x0f7f00, 0xe0970b, 0x0f7795 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0fd1c4, 0xe1ac22, 0x0ec8cf, 0xe1ac22, 0x0e9a94 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0f7c1c, 0xe3cc03, 0x0df786, 0xe3cc03, 0x0d73a2 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x11fb92, 0xf5a1a0, 0x073cd2, 0xf5a1a0, 0x093865 } } },
  { channel: 1, filter: 6, data: { coeff: { 0x0e17a9, 0x068b6c, 0x08a0e5, 0x068b6c, 0x06b88e } } }
};

static struct tas_eq_pref_t eqp_17_1_0 = {
  sample_rate:  44100,
  device_id:    0x17,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_17_1_0_drce,

  filter_count: 14,
  biquads:      eqp_17_1_0_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_18_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -13.14  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_18_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0f5514, 0xe155d7, 0x0f5514, 0xe15cfa, 0x0eb14b } } },
  { channel: 0, filter: 1, data: { coeff: { 0x06ec33, 0x02abe3, 0x015eef, 0xf764d9, 0x03922d } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0ef5f2, 0xe67d1f, 0x0bcf37, 0xe67d1f, 0x0ac529 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0db050, 0xe5be4d, 0x0d0c78, 0xe5be4d, 0x0abcc8 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0f1298, 0xe64ec6, 0x0cc03e, 0xe64ec6, 0x0bd2d7 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0c641a, 0x06537a, 0x08d155, 0x06537a, 0x053570 } } },
  { channel: 0, filter: 6, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0f5514, 0xe155d7, 0x0f5514, 0xe15cfa, 0x0eb14b } } },
  { channel: 1, filter: 1, data: { coeff: { 0x06ec33, 0x02abe3, 0x015eef, 0xf764d9, 0x03922d } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0ef5f2, 0xe67d1f, 0x0bcf37, 0xe67d1f, 0x0ac529 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0db050, 0xe5be4d, 0x0d0c78, 0xe5be4d, 0x0abcc8 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0f1298, 0xe64ec6, 0x0cc03e, 0xe64ec6, 0x0bd2d7 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0c641a, 0x06537a, 0x08d155, 0x06537a, 0x053570 } } },
  { channel: 1, filter: 6, data: { coeff: { 0x100000, 0x000000, 0x000000, 0x000000, 0x000000 } } }
};

static struct tas_eq_pref_t eqp_18_1_0 = {
  sample_rate:  44100,
  device_id:    0x18,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_18_1_0_drce,

  filter_count: 14,
  biquads:      eqp_18_1_0_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_1a_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -10.75  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_1a_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0fb8fd, 0xe08e04, 0x0fb8fd, 0xe08f40, 0x0f7336 } } },
  { channel: 0, filter: 1, data: { coeff: { 0x06371d, 0x0c6e3a, 0x06371d, 0x05bfd3, 0x031ca2 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0fa1c0, 0xe18692, 0x0f030e, 0xe18692, 0x0ea4ce } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0fe495, 0xe17eff, 0x0f0452, 0xe17eff, 0x0ee8e7 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x100857, 0xe7e71c, 0x0e9599, 0xe7e71c, 0x0e9df1 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0fb26e, 0x06a82c, 0x0db2b4, 0x06a82c, 0x0d6522 } } },
  { channel: 0, filter: 6, data: { coeff: { 0x11419d, 0xf06cbf, 0x0a4f6e, 0xf06cbf, 0x0b910c } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0fb8fd, 0xe08e04, 0x0fb8fd, 0xe08f40, 0x0f7336 } } },
  { channel: 1, filter: 1, data: { coeff: { 0x06371d, 0x0c6e3a, 0x06371d, 0x05bfd3, 0x031ca2 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0fa1c0, 0xe18692, 0x0f030e, 0xe18692, 0x0ea4ce } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0fe495, 0xe17eff, 0x0f0452, 0xe17eff, 0x0ee8e7 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x100857, 0xe7e71c, 0x0e9599, 0xe7e71c, 0x0e9df1 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0fb26e, 0x06a82c, 0x0db2b4, 0x06a82c, 0x0d6522 } } },
  { channel: 1, filter: 6, data: { coeff: { 0x11419d, 0xf06cbf, 0x0a4f6e, 0xf06cbf, 0x0b910c } } }
};

static struct tas_eq_pref_t eqp_1a_1_0 = {
  sample_rate:  44100,
  device_id:    0x1a,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_1a_1_0_drce,

  filter_count: 14,
  biquads:      eqp_1a_1_0_biquads
};

/* ======================================================================== */

static struct tas_drce_t eqp_1c_1_0_drce={
  enable:    1,
  above:     { val: 3.0 * (1<<8), expand: 0 },
  below:     { val: 1.0 * (1<<8), expand: 0 },
  threshold: -14.34  * (1<<8),
  energy:    2.4     * (1<<12),
  attack:    0.013   * (1<<12),
  decay:     0.212   * (1<<12),
};

static struct tas_biquad_ctrl_t eqp_1c_1_0_biquads[]={
  { channel: 0, filter: 0, data: { coeff: { 0x0f4f95, 0xe160d4, 0x0f4f95, 0xe1686e, 0x0ea6c5 } } },
  { channel: 0, filter: 1, data: { coeff: { 0x066b92, 0x0290d4, 0x0148a0, 0xf6853f, 0x03bfc7 } } },
  { channel: 0, filter: 2, data: { coeff: { 0x0f57dc, 0xe51c91, 0x0dd1cb, 0xe51c91, 0x0d29a8 } } },
  { channel: 0, filter: 3, data: { coeff: { 0x0df1cb, 0xe4fa84, 0x0d7cdc, 0xe4fa84, 0x0b6ea7 } } },
  { channel: 0, filter: 4, data: { coeff: { 0x0eba36, 0xe6aa48, 0x0b9f52, 0xe6aa48, 0x0a5989 } } },
  { channel: 0, filter: 5, data: { coeff: { 0x0caf02, 0x05ef9d, 0x084beb, 0x05ef9d, 0x04faee } } },
  { channel: 0, filter: 6, data: { coeff: { 0x0fc686, 0xe22947, 0x0e4b5d, 0xe22947, 0x0e11e4 } } },

  { channel: 1, filter: 0, data: { coeff: { 0x0f4f95, 0xe160d4, 0x0f4f95, 0xe1686e, 0x0ea6c5 } } },
  { channel: 1, filter: 1, data: { coeff: { 0x066b92, 0x0290d4, 0x0148a0, 0xf6853f, 0x03bfc7 } } },
  { channel: 1, filter: 2, data: { coeff: { 0x0f57dc, 0xe51c91, 0x0dd1cb, 0xe51c91, 0x0d29a8 } } },
  { channel: 1, filter: 3, data: { coeff: { 0x0df1cb, 0xe4fa84, 0x0d7cdc, 0xe4fa84, 0x0b6ea7 } } },
  { channel: 1, filter: 4, data: { coeff: { 0x0eba36, 0xe6aa48, 0x0b9f52, 0xe6aa48, 0x0a5989 } } },
  { channel: 1, filter: 5, data: { coeff: { 0x0caf02, 0x05ef9d, 0x084beb, 0x05ef9d, 0x04faee } } },
  { channel: 1, filter: 6, data: { coeff: { 0x0fc686, 0xe22947, 0x0e4b5d, 0xe22947, 0x0e11e4 } } }
};

static struct tas_eq_pref_t eqp_1c_1_0 = {
  sample_rate:  44100,
  device_id:    0x1c,
  output_id:    TAS_OUTPUT_INTERNAL_SPKR,
  speaker_id:   0x00,

  drce:         &eqp_1c_1_0_drce,

  filter_count: 14,
  biquads:      eqp_1c_1_0_biquads
};

/* ======================================================================== */

static uint tas3004_master_tab[]={
	       0x0,       0x75,       0x9c,       0xbb,
	      0xdb,       0xfb,      0x11e,      0x143,
	     0x16b,      0x196,      0x1c3,      0x1f5,
	     0x229,      0x263,      0x29f,      0x2e1,
	     0x328,      0x373,      0x3c5,      0x41b,
	     0x478,      0x4dc,      0x547,      0x5b8,
	     0x633,      0x6b5,      0x740,      0x7d5,
	     0x873,      0x91c,      0x9d2,      0xa92,
	     0xb5e,      0xc39,      0xd22,      0xe19,
	     0xf20,     0x1037,     0x1161,     0x129e,
	    0x13ed,     0x1551,     0x16ca,     0x185d,
	    0x1a08,     0x1bcc,     0x1dac,     0x1fa7,
	    0x21c1,     0x23fa,     0x2655,     0x28d6,
	    0x2b7c,     0x2e4a,     0x3141,     0x3464,
	    0x37b4,     0x3b35,     0x3ee9,     0x42d3,
	    0x46f6,     0x4b53,     0x4ff0,     0x54ce,
	    0x59f2,     0x5f5f,     0x6519,     0x6b24,
	    0x7183,     0x783c,     0x7f53,     0x86cc,
	    0x8ead,     0x96fa,     0x9fba,     0xa8f2,
	    0xb2a7,     0xbce1,     0xc7a5,     0xd2fa,
	    0xdee8,     0xeb75,     0xf8aa,    0x1068e,
	   0x1152a,    0x12487,    0x134ad,    0x145a5,
	   0x1577b,    0x16a37,    0x17df5,    0x192bd,
	   0x1a890,    0x1bf7b,    0x1d78d,    0x1f0d1,
	   0x20b55,    0x22727,    0x24456,    0x262f2,
	   0x2830b
};

static uint tas3004_mixer_tab[]={
	       0x0,      0x748,      0x9be,      0xbaf,
	     0xda4,      0xfb1,     0x11de,     0x1431,
	    0x16ad,     0x1959,     0x1c37,     0x1f4b,
	    0x2298,     0x2628,     0x29fb,     0x2e12,
	    0x327d,     0x3734,     0x3c47,     0x41b4,
	    0x4787,     0x4dbe,     0x546d,     0x5b86,
	    0x632e,     0x6b52,     0x7400,     0x7d54,
	    0x873b,     0x91c6,     0x9d1a,     0xa920,
	    0xb5e5,     0xc38c,     0xd21b,     0xe18f,
	    0xf1f5,    0x1036a,    0x1160f,    0x129d6,
	   0x13ed0,    0x1550c,    0x16ca0,    0x185c9,
	   0x1a07b,    0x1bcc3,    0x1dab9,    0x1fa75,
	   0x21c0f,    0x23fa3,    0x26552,    0x28d64,
	   0x2b7c9,    0x2e4a2,    0x31411,    0x3463b,
	   0x37b44,    0x3b353,    0x3ee94,    0x42d30,
	   0x46f55,    0x4b533,    0x4fefc,    0x54ce5,
	   0x59f25,    0x5f5f6,    0x65193,    0x6b23c,
	   0x71835,    0x783c3,    0x7f52c,    0x86cc0,
	   0x8eacc,    0x96fa5,    0x9fba0,    0xa8f1a,
	   0xb2a71,    0xbce0a,    0xc7a4a,    0xd2fa0,
	   0xdee7b,    0xeb752,    0xf8a9f,   0x1068e4,
	  0x1152a3,   0x12486a,   0x134ac8,   0x145a55,
	  0x1577ac,   0x16a370,   0x17df51,   0x192bc2,
	  0x1a88f8,   0x1bf7b7,   0x1d78c9,   0x1f0d04,
	  0x20b542,   0x227268,   0x244564,   0x262f26,
	  0x2830af
};

static uint tas3004_treble_tab[]={
	      0x96,       0x95,       0x95,       0x94,
	      0x93,       0x92,       0x92,       0x91,
	      0x90,       0x90,       0x8f,       0x8e,
	      0x8d,       0x8d,       0x8c,       0x8b,
	      0x8a,       0x8a,       0x89,       0x88,
	      0x88,       0x87,       0x86,       0x85,
	      0x85,       0x84,       0x83,       0x83,
	      0x82,       0x81,       0x80,       0x80,
	      0x7f,       0x7e,       0x7e,       0x7d,
	      0x7c,       0x7b,       0x7b,       0x7a,
	      0x79,       0x78,       0x78,       0x77,
	      0x76,       0x76,       0x75,       0x74,
	      0x73,       0x73,       0x72,       0x71,
	      0x71,       0x68,       0x45,       0x5b,
	      0x6d,       0x6c,       0x6b,       0x6a,
	      0x69,       0x68,       0x67,       0x66,
	      0x65,       0x63,       0x62,       0x62,
	      0x60,       0x5e,       0x5c,       0x5b,
	      0x59,       0x57,       0x55,       0x53,
	      0x52,       0x4f,       0x4d,       0x4a,
	      0x48,       0x46,       0x43,       0x40,
	      0x3d,       0x3a,       0x36,       0x33,
	      0x2f,       0x2c,       0x27,       0x23,
	      0x1f,       0x1a,       0x15,        0xf,
	       0x8,        0x5,        0x2,        0x1,
	       0x1
};

static uint tas3004_bass_tab[]={
	      0x96,       0x95,       0x95,       0x94,
	      0x93,       0x92,       0x92,       0x91,
	      0x90,       0x90,       0x8f,       0x8e,
	      0x8d,       0x8d,       0x8c,       0x8b,
	      0x8a,       0x8a,       0x89,       0x88,
	      0x88,       0x87,       0x86,       0x85,
	      0x85,       0x84,       0x83,       0x83,
	      0x82,       0x81,       0x80,       0x80,
	      0x7f,       0x7e,       0x7e,       0x7d,
	      0x7c,       0x7b,       0x7b,       0x7a,
	      0x79,       0x78,       0x78,       0x77,
	      0x76,       0x76,       0x75,       0x74,
	      0x73,       0x73,       0x72,       0x71,
	      0x70,       0x6f,       0x6e,       0x6d,
	      0x6c,       0x6b,       0x6a,       0x6a,
	      0x69,       0x67,       0x66,       0x66,
	      0x65,       0x63,       0x62,       0x62,
	      0x61,       0x60,       0x5e,       0x5d,
	      0x5b,       0x59,       0x57,       0x55,
	      0x53,       0x51,       0x4f,       0x4c,
	      0x4a,       0x48,       0x46,       0x44,
	      0x41,       0x3e,       0x3b,       0x38,
	      0x36,       0x33,       0x2f,       0x2b,
	      0x28,       0x24,       0x20,       0x1c,
	      0x17,       0x12,        0xd,        0x7,
	       0x1
};

struct tas_gain_t tas3004_gain={
  master: tas3004_master_tab,
  treble: tas3004_treble_tab,
  bass:   tas3004_bass_tab,
  mixer:  tas3004_mixer_tab
};

struct tas_eq_pref_t *tas3004_eq_prefs[]={
  &eqp_17_1_0,
  &eqp_18_1_0,
  &eqp_1a_1_0,
  &eqp_1c_1_0,
  NULL
};




#include <linux/version.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/proc_fs.h>
#include <linux/ioport.h>
#include <linux/sysctl.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/soundcard.h>
#include <asm/uaccess.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/prom.h>

#include "tas_common.h"

#define CALL0(proc)								\
	do {									\
		struct tas_data_t *self;					\
		if (!tas_client || driver_hooks == NULL)			\
			return -1;						\
		self = (struct tas_data_t *)tas_client->data;			\
		if (driver_hooks->proc)						\
			return driver_hooks->proc(self);			\
		else								\
			return -EINVAL;						\
	} while (0)

#define CALL(proc,arg...)							\
	do {									\
		struct tas_data_t *self;					\
		if (!tas_client || driver_hooks == NULL)			\
			return -1;						\
		self = (struct tas_data_t *)tas_client->data;			\
		if (driver_hooks->proc)						\
			return driver_hooks->proc(self, ## arg);		\
		else								\
			return -EINVAL;						\
	} while (0)


static u8 tas_i2c_address = 0x34;
static struct i2c_client * tas_client = NULL;

static int tas_initialized = 0;
static struct device_node* tas_node = NULL;

static int tas_attach_adapter(struct i2c_adapter *);
static int tas_detach_client(struct i2c_client *);

struct i2c_driver tas_driver = {
	name:		"",
	id:             0,
	flags:		I2C_DF_NOTIFY,
	attach_adapter:	&tas_attach_adapter,
	detach_client:	&tas_detach_client,
	command:	NULL,
	inc_use:	NULL,
	dec_use:	NULL
};

struct tas_driver_hooks_t *driver_hooks;

int
tas_register_driver(struct tas_driver_hooks_t *hooks)
{
	driver_hooks = hooks;
	return 0;
}

int
tas_get_mixer_level(int mixer, uint *level)
{
	CALL(get_mixer_level,mixer,level);
}

int
tas_set_mixer_level(int mixer,uint level)
{
	CALL(set_mixer_level,mixer,level);
}

int
tas_enter_sleep(void)
{
	CALL0(enter_sleep);
}

int
tas_leave_sleep(void)
{
	CALL0(leave_sleep);
}

int
tas_supported_mixers(void)
{
	CALL0(supported_mixers);
}

int
tas_mixer_is_stereo(int mixer)
{
	CALL(mixer_is_stereo,mixer);
}

int
tas_stereo_mixers(void)
{
	CALL0(stereo_mixers);
}

int
tas_output_device_change(int device_id,int layout_id,int speaker_id)
{
	CALL(output_device_change,device_id,layout_id,speaker_id);
}

int
tas_device_ioctl(u_int cmd, u_long arg)
{
	CALL(device_ioctl,cmd,arg);
}

int
tas_post_init(void)
{
	CALL0(post_init);
}

static int
tas_detect_client(struct i2c_adapter *adapter, int address)
{
	int rc = 0;
	struct i2c_client *new_client;
	struct tas_data_t *data;
	const char *client_name = "tas Digital Equalizer";

	if (driver_hooks == NULL) {
		printk(KERN_ERR "tas_detect_client called with no hooks !\n");
		return -ENODEV;
	}
	
	new_client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
	if (!new_client) {
		rc = -ENOMEM;
		goto bail;
	}

	new_client->data = NULL;

	new_client->addr = address;
	new_client->data = data;
	new_client->adapter = adapter;
	new_client->driver = &tas_driver;
	new_client->flags = 0;

	strcpy(new_client->name,client_name);

	new_client->id = 0; /* Only one instance supported */

        if (driver_hooks->init && driver_hooks->init(new_client)) {
		rc = -ENODEV;
		goto bail;
	}

	/* Tell the i2c layer a new client has arrived */
	if (i2c_attach_client(new_client)) {
        	if (driver_hooks->uninit)
			driver_hooks->uninit((struct tas_data_t *)new_client->data);
		rc = -ENODEV;
		goto bail;
	}

	tas_client = new_client;
bail:
	if (rc && new_client) {
		tas_client = NULL;
		kfree(new_client);
	}
	return rc;
}

static int
tas_attach_adapter(struct i2c_adapter *adapter)
{
	if (!strncmp(adapter->name, "mac-io", 6))
		return tas_detect_client(adapter, tas_i2c_address);
	return 0;
}

static int
tas_detach_client(struct i2c_client *client)
{
	if (client == tas_client) {
		driver_hooks->uninit((struct tas_data_t *)client->data);

		i2c_detach_client(client);
		kfree(client);
	}
	return 0;
}

int __init
tas_cleanup(void)
{
	if (!tas_initialized)
		return -ENODEV;
	i2c_del_driver(&tas_driver);
	tas_initialized = 0;

	return 0;
}

int __init
tas_init(int driver_id, const char *driver_name)
{
	int rc;
	u32* paddr;

	if (tas_initialized)
		return 0;

        strncpy(tas_driver.name,driver_name,31);
        tas_driver.name[31]=0;
        tas_driver.id=driver_id;

	tas_node = find_devices("deq");
	if (tas_node == NULL)
		return -ENODEV;

	printk(KERN_INFO "tas driver [%s])\n",tas_driver.name);
	paddr = (u32 *)get_property(tas_node, "i2c-address", NULL);
	if (paddr) {
		tas_i2c_address = (*paddr) >> 1;
		printk(KERN_INFO "using i2c address: 0x%x from device-tree\n",
		       tas_i2c_address);
	} else    
		printk(KERN_INFO "using i2c address: 0x%x (default)\n", tas_i2c_address);

	if ((rc = i2c_add_driver(&tas_driver))) {
		printk("tas: Driver registration failed, module not inserted.\n");
		tas_cleanup();
		return rc;
	}
	tas_initialized = 1;
	return 0;
}
/*
 * Local Variables:
 * tab-width: 8
 * indent-tabs-mode: t
 * c-basic-offset: 8
 * End:
 */




#ifndef _TAS_COMMON_H_
#define _TAS_COMMON_H_

#include <linux/i2c.h>
#include <linux/soundcard.h>
#include <asm/string.h>

#define I2C_DRIVERID_TAS_BASE   (0xFEBA)

#define SET_4_20(shadow, offset, val)                        \
	do {                                                 \
		(shadow)[(offset)+0] = ((val) >> 16) & 0xff; \
		(shadow)[(offset)+1] = ((val) >> 8)  & 0xff; \
		(shadow)[(offset)+2] = ((val) >> 0)  & 0xff; \
	} while (0)

#define GET_4_20(shadow, offset)                             \
	(((u_int)((shadow)[(offset)+0]) << 16) |             \
	 ((u_int)((shadow)[(offset)+1]) <<  8) |             \
	 ((u_int)((shadow)[(offset)+2]) <<  0))


#define TAS_BIQUAD_FAST_LOAD 0x01

#define TAS_DRCE_ENABLE           0x01
#define TAS_DRCE_ABOVE_RATIO      0x02
#define TAS_DRCE_BELOW_RATIO      0x04
#define TAS_DRCE_THRESHOLD        0x08
#define TAS_DRCE_ENERGY           0x10
#define TAS_DRCE_ATTACK           0x20
#define TAS_DRCE_DECAY            0x40

#define TAS_DRCE_ALL              0x7f


#define TAS_OUTPUT_HEADPHONES     0x00
#define TAS_OUTPUT_INTERNAL_SPKR  0x01
#define TAS_OUTPUT_EXTERNAL_SPKR  0x02


union tas_biquad_t {
	struct {
		int b0,b1,b2,a1,a2;
	} coeff;
	int buf[5];
};

struct tas_biquad_ctrl_t {
	u_int channel:4;
	u_int filter:4;

	union tas_biquad_t data;
};

struct tas_biquad_ctrl_list_t {
	int flags;
	int filter_count;
	struct tas_biquad_ctrl_t biquads[0];
};

struct tas_ratio_t {
	unsigned short val;    /* 8.8                        */
	unsigned short expand; /* 0 = compress, !0 = expand. */
};

struct tas_drce_t {
	unsigned short enable;
	struct tas_ratio_t above;
	struct tas_ratio_t below;
	short threshold;       /* dB,       8.8 signed    */
	unsigned short energy; /* seconds,  4.12 unsigned */
	unsigned short attack; /* seconds,  4.12 unsigned */
	unsigned short decay;  /* seconds,  4.12 unsigned */
};

struct tas_drce_ctrl_t {
	uint flags;

	struct tas_drce_t data;
};

struct tas_gain_t
{
  unsigned int *master;
  unsigned int *treble;
  unsigned int *bass;
  unsigned int *mixer;
};

typedef char tas_shadow_t[16];

struct tas_data_t
{
	struct i2c_client *client;
	tas_shadow_t *shadow;
	uint mixer[SOUND_MIXER_NRDEVICES];
};

typedef int (*tas_hook_init_t)(struct i2c_client *);
typedef int (*tas_hook_post_init_t)(struct tas_data_t *);
typedef void (*tas_hook_uninit_t)(struct tas_data_t *);

typedef int (*tas_hook_get_mixer_level_t)(struct tas_data_t *,int,uint *);
typedef int (*tas_hook_set_mixer_level_t)(struct tas_data_t *,int,uint);

typedef int (*tas_hook_enter_sleep_t)(struct tas_data_t *);
typedef int (*tas_hook_leave_sleep_t)(struct tas_data_t *);

typedef int (*tas_hook_supported_mixers_t)(struct tas_data_t *);
typedef int (*tas_hook_mixer_is_stereo_t)(struct tas_data_t *,int);
typedef int (*tas_hook_stereo_mixers_t)(struct tas_data_t *);

typedef int (*tas_hook_output_device_change_t)(struct tas_data_t *,int,int,int);
typedef int (*tas_hook_device_ioctl_t)(struct tas_data_t *,u_int,u_long);

struct tas_driver_hooks_t {
	/*
	 * All hardware initialisation must be performed in
	 * post_init(), as tas_dmasound_init() does a hardware reset.
	 *
	 * init() is called before tas_dmasound_init() so that
	 * ouput_device_change() is always called after i2c driver
	 * initialisation. The implication is that
	 * output_device_change() must cope with the fact that it
	 * may be called before post_init().
	 */

	tas_hook_init_t                   init;
	tas_hook_post_init_t              post_init;
	tas_hook_uninit_t                 uninit;

	tas_hook_get_mixer_level_t        get_mixer_level;
	tas_hook_set_mixer_level_t        set_mixer_level;

	tas_hook_enter_sleep_t            enter_sleep;
	tas_hook_leave_sleep_t            leave_sleep;

	tas_hook_supported_mixers_t       supported_mixers;
	tas_hook_mixer_is_stereo_t        mixer_is_stereo;
	tas_hook_stereo_mixers_t          stereo_mixers;

	tas_hook_output_device_change_t   output_device_change;
	tas_hook_device_ioctl_t           device_ioctl;
};

enum tas_write_mode_t {
	WRITE_HW     = 0x01,
	WRITE_SHADOW = 0x02,
	WRITE_NORMAL = 0x03,
	FORCE_WRITE  = 0x04
};

static inline uint
tas_mono_to_stereo(uint mono)
{
	mono &=0xff;
	return mono | (mono<<8);
}

/*
 * Todo: make these functions a bit more efficient !
 */
static inline int
tas_write_register(	struct tas_data_t *self,
			uint reg_num,
			uint reg_width,
			char *data,
			uint write_mode)
{
	int rc;

	if (reg_width==0 || data==NULL || self==NULL)
		return -EINVAL;
	if (!(write_mode & FORCE_WRITE) &&
	    !memcmp(data,self->shadow[reg_num],reg_width))
	    	return 0;

	if (write_mode & WRITE_SHADOW)
		memcpy(self->shadow[reg_num],data,reg_width);
	if (write_mode & WRITE_HW) {
		rc=i2c_smbus_write_block_data(self->client,
					      reg_num,
					      reg_width,
					      data);
		if (rc < 0) {
			printk("tas: I2C block write failed \n");  
			return rc; 
		}
	}
	return 0;
}

static inline int
tas_sync_register(	struct tas_data_t *self,
			uint reg_num,
			uint reg_width)
{
	int rc;

	if (reg_width==0 || self==NULL)
		return -EINVAL;
	rc=i2c_smbus_write_block_data(self->client,
				      reg_num,
				      reg_width,
				      self->shadow[reg_num]);
	if (rc < 0) {
		printk("tas: I2C block write failed \n");
		return rc;
	}
	return 0;
}

static inline int
tas_write_byte_register(	struct tas_data_t *self,
				uint reg_num,
				char data,
				uint write_mode)
{
	if (self==NULL)
		return -1;
	if (!(write_mode & FORCE_WRITE) && data != self->shadow[reg_num][0])
		return 0;
	if (write_mode & WRITE_SHADOW)
		self->shadow[reg_num][0]=data;
	if (write_mode & WRITE_HW) {
		if (i2c_smbus_write_byte_data(self->client, reg_num, data) < 0) {
			printk("tas: I2C byte write failed \n");  
			return -1; 
		}
	}
	return 0;
}

static inline int
tas_sync_byte_register(	struct tas_data_t *self,
			uint reg_num,
			uint reg_width)
{
	if (reg_width==0 || self==NULL)
		return -1;
	if (i2c_smbus_write_byte_data(
	    self->client, reg_num, self->shadow[reg_num][0]) < 0) {
		printk("tas: I2C byte write failed \n");
		return -1;
	}
	return 0;
}

static inline int
tas_read_register(	struct tas_data_t *self,
			uint reg_num,
			uint reg_width,
			char *data)
{
	if (reg_width==0 || data==NULL || self==NULL)
		return -1;
	memcpy(data,self->shadow[reg_num],reg_width);
	return 0;
}

extern int tas_register_driver(struct tas_driver_hooks_t *hooks);

extern int tas_get_mixer_level(int mixer,uint *level);
extern int tas_set_mixer_level(int mixer,uint level);
extern int tas_enter_sleep(void);
extern int tas_leave_sleep(void);
extern int tas_supported_mixers(void);
extern int tas_mixer_is_stereo(int mixer);
extern int tas_stereo_mixers(void);
extern int tas_output_device_change(int,int,int);
extern int tas_device_ioctl(u_int, u_long);

extern int tas_cleanup(void);
extern int tas_init(int driver_id,const char *driver_name);
extern int tas_post_init(void);

#endif /* _TAS_COMMON_H_ */
/*
 * Local Variables:
 * tab-width: 8
 * indent-tabs-mode: t
 * c-basic-offset: 8
 * End:
 */




#ifndef _TAS_EQ_PREFS_H_
#define _TAS_EQ_PREFS_H_

struct tas_eq_pref_t {
	u_int sample_rate;
	u_int device_id;
	u_int output_id;
	u_int speaker_id;

	struct tas_drce_t *drce;

	u_int filter_count;
	struct tas_biquad_ctrl_t *biquads;
};

#endif /* _TAS_EQ_PREFS_H_ */

/*
 * Local Variables:
 * tab-width: 8
 * indent-tabs-mode: t
 * c-basic-offset: 8
 * End:
 */




#ifndef _TAS_IOCTL_H_
#define _TAS_IOCTL_H_

#include <linux/i2c.h>
#include <linux/soundcard.h>


#define TAS_READ_EQ              _SIOR('t',0,struct tas_biquad_ctrl_t)
#define TAS_WRITE_EQ             _SIOW('t',0,struct tas_biquad_ctrl_t)

#define TAS_READ_EQ_LIST         _SIOR('t',1,struct tas_biquad_ctrl_t)
#define TAS_WRITE_EQ_LIST        _SIOW('t',1,struct tas_biquad_ctrl_t)

#define TAS_READ_EQ_FILTER_COUNT  _SIOR('t',2,int)
#define TAS_READ_EQ_CHANNEL_COUNT _SIOR('t',3,int)

#define TAS_READ_DRCE            _SIOR('t',4,struct tas_drce_ctrl_t)
#define TAS_WRITE_DRCE           _SIOW('t',4,struct tas_drce_ctrl_t)

#define TAS_READ_DRCE_CAPS       _SIOR('t',5,int)
#define TAS_READ_DRCE_MIN        _SIOR('t',6,int)
#define TAS_READ_DRCE_MAX        _SIOR('t',7,int)

#endif

Lines 714-721 Link Here

(-)linux-2.4.22/drivers/usb/host/usb-ohci.c (-13 / +41 lines)
714	list_add (&urb->urb_list, entry);	714	list_add (&urb->urb_list, entry);
715		715
716	/* drive timeouts by SF (messy, but works) */	716	/* drive timeouts by SF (messy, but works) */
717	writel (OHCI_INTR_SF, &ohci->regs->intrenable);	717	if (!ohci->sleeping) {
718	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */	718	writel (OHCI_INTR_SF, &ohci->regs->intrenable);
		719	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
		720	}
719	}	721	}
720	#endif	722	#endif
721		723
Lines 1010-1015 Link Here
1010	case PIPE_CONTROL:	1012	case PIPE_CONTROL:
1011	ed->hwNextED = 0;	1013	ed->hwNextED = 0;
1012	if (ohci->ed_controltail == NULL) {	1014	if (ohci->ed_controltail == NULL) {
		1015	io_barrier();
1013	writel (ed->dma, &ohci->regs->ed_controlhead);	1016	writel (ed->dma, &ohci->regs->ed_controlhead);
1014	} else {	1017	} else {
1015	ohci->ed_controltail->hwNextED = cpu_to_le32 (ed->dma);	1018	ohci->ed_controltail->hwNextED = cpu_to_le32 (ed->dma);
Lines 1018-1023 Link Here
1018	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&	1021	if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
1019	!ohci->ed_rm_list[1] && !ohci->sleeping) {	1022	!ohci->ed_rm_list[1] && !ohci->sleeping) {
1020	ohci->hc_control \|= OHCI_CTRL_CLE;	1023	ohci->hc_control \|= OHCI_CTRL_CLE;
		1024	io_barrier();
1021	writel (ohci->hc_control, &ohci->regs->control);	1025	writel (ohci->hc_control, &ohci->regs->control);
1022	}	1026	}
1023	ohci->ed_controltail = edi;	1027	ohci->ed_controltail = edi;
Lines 1026-1031 Link Here
1026	case PIPE_BULK:	1030	case PIPE_BULK:
1027	ed->hwNextED = 0;	1031	ed->hwNextED = 0;
1028	if (ohci->ed_bulktail == NULL) {	1032	if (ohci->ed_bulktail == NULL) {
		1033	io_barrier();
1029	writel (ed->dma, &ohci->regs->ed_bulkhead);	1034	writel (ed->dma, &ohci->regs->ed_bulkhead);
1030	} else {	1035	} else {
1031	ohci->ed_bulktail->hwNextED = cpu_to_le32 (ed->dma);	1036	ohci->ed_bulktail->hwNextED = cpu_to_le32 (ed->dma);
Lines 1034-1039 Link Here
1034	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&	1039	if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
1035	!ohci->ed_rm_list[1] && !ohci->sleeping) {	1040	!ohci->ed_rm_list[1] && !ohci->sleeping) {
1036	ohci->hc_control \|= OHCI_CTRL_BLE;	1041	ohci->hc_control \|= OHCI_CTRL_BLE;
		1042	io_barrier();
1037	writel (ohci->hc_control, &ohci->regs->control);	1043	writel (ohci->hc_control, &ohci->regs->control);
1038	}	1044	}
1039	ohci->ed_bulktail = edi;	1045	ohci->ed_bulktail = edi;
Lines 1126-1132 Link Here
1126	if (ed->ed_prev == NULL) {	1132	if (ed->ed_prev == NULL) {
1127	if (!ed->hwNextED) {	1133	if (!ed->hwNextED) {
1128	ohci->hc_control &= ~OHCI_CTRL_CLE;	1134	ohci->hc_control &= ~OHCI_CTRL_CLE;
1129	writel (ohci->hc_control, &ohci->regs->control);	1135	if (!ohci->sleeping)
		1136	writel (ohci->hc_control, &ohci->regs->control);
1130	}	1137	}
1131	writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_controlhead);	1138	writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_controlhead);
1132	} else {	1139	} else {
Lines 1143-1149 Link Here
1143	if (ed->ed_prev == NULL) {	1150	if (ed->ed_prev == NULL) {
1144	if (!ed->hwNextED) {	1151	if (!ed->hwNextED) {
1145	ohci->hc_control &= ~OHCI_CTRL_BLE;	1152	ohci->hc_control &= ~OHCI_CTRL_BLE;
1146	writel (ohci->hc_control, &ohci->regs->control);	1153	if (!ohci->sleeping)
		1154	writel (ohci->hc_control, &ohci->regs->control);
1147	}	1155	}
1148	writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_bulkhead);	1156	writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_bulkhead);
1149	} else {	1157	} else {
Lines 1272-1287 Link Here
1272	return;	1280	return;
1273		1281
1274	ed->hwINFO \|= cpu_to_le32 (OHCI_ED_SKIP);	1282	ed->hwINFO \|= cpu_to_le32 (OHCI_ED_SKIP);
		1283	io_barrier();
1275		1284
1276	if (!ohci->disabled) {	1285	if (!ohci->disabled) {
1277	switch (ed->type) {	1286	switch (ed->type) {
1278	case PIPE_CONTROL: /* stop control list */	1287	case PIPE_CONTROL: /* stop control list */
1279	ohci->hc_control &= ~OHCI_CTRL_CLE;	1288	ohci->hc_control &= ~OHCI_CTRL_CLE;
1280	writel (ohci->hc_control, &ohci->regs->control);	1289	if (!ohci->sleeping)
		1290	writel (ohci->hc_control, &ohci->regs->control);
1281	break;	1291	break;
1282	case PIPE_BULK: /* stop bulk list */	1292	case PIPE_BULK: /* stop bulk list */
1283	ohci->hc_control &= ~OHCI_CTRL_BLE;	1293	ohci->hc_control &= ~OHCI_CTRL_BLE;
1284	writel (ohci->hc_control, &ohci->regs->control);	1294	if (!ohci->sleeping)
		1295	writel (ohci->hc_control, &ohci->regs->control);
1285	break;	1296	break;
1286	}	1297	}
1287	}	1298	}
Lines 1413-1419 Link Here
1413	}	1424	}
1414		1425
1415	if (!ohci->sleeping) {	1426	if (!ohci->sleeping) {
1416	wmb();	1427	io_barrier();
1417	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */	1428	writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
1418	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */	1429	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
1419	}	1430	}
Lines 1442-1448 Link Here
1442	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;	1453	TD_CC \| TD_DP_IN \| TD_T_DATA1: TD_CC \| TD_DP_OUT \| TD_T_DATA1;
1443	td_fill (ohci, info, data, 0, urb, cnt++);	1454	td_fill (ohci, info, data, 0, urb, cnt++);
1444	if (!ohci->sleeping) {	1455	if (!ohci->sleeping) {
1445	wmb();	1456	io_barrier();
1446	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */	1457	writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
1447	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */	1458	(void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
1448	}	1459	}
Lines 1550-1555 Link Here
1550		1561
1551	td_list_hc = le32_to_cpup (&ohci->hcca->done_head) & 0xfffffff0;	1562	td_list_hc = le32_to_cpup (&ohci->hcca->done_head) & 0xfffffff0;
1552	ohci->hcca->done_head = 0;	1563	ohci->hcca->done_head = 0;
		1564	wmb();
1553		1565
1554	while (td_list_hc) {	1566	while (td_list_hc) {
1555	td_list = dma_to_td (ohci, td_list_hc);	1567	td_list = dma_to_td (ohci, td_list_hc);
Lines 1658-1663 Link Here
1658		1670
1659	/* maybe reenable control and bulk lists */	1671	/* maybe reenable control and bulk lists */
1660	if (!ohci->disabled) {	1672	if (!ohci->disabled) {
		1673	io_barrier();
1661	if (ctrl) /* reset control list */	1674	if (ctrl) /* reset control list */
1662	writel (0, &ohci->regs->ed_controlcurrent);	1675	writel (0, &ohci->regs->ed_controlcurrent);
1663	if (bulk) /* reset bulk list */	1676	if (bulk) /* reset bulk list */
Lines 2318-2323 Link Here
2318	struct ohci_regs * regs = ohci->regs;	2331	struct ohci_regs * regs = ohci->regs;
2319	int ints;	2332	int ints;
2320		2333
		2334	/* Sanity check */
		2335	if (ohci->sleeping)
		2336	return;
		2337
2321	/* avoid (slow) readl if only WDH happened */	2338	/* avoid (slow) readl if only WDH happened */
2322	if ((ohci->hcca->done_head != 0)	2339	if ((ohci->hcca->done_head != 0)
2323	&& !(le32_to_cpup (&ohci->hcca->done_head) & 0x01)) {	2340	&& !(le32_to_cpup (&ohci->hcca->done_head) & 0x01)) {
Lines 2624-2629 Link Here
2624	if (pci_enable_device(dev) < 0)	2641	if (pci_enable_device(dev) < 0)
2625	return -ENODEV;	2642	return -ENODEV;
2626		2643
		2644	#ifdef CONFIG_PMAC_PBOOK
		2645	{
		2646	struct device_node *of_node;
		2647
		2648	/* Re-enable USB PAD & cell clock */
		2649	of_node = pci_device_to_OF_node (dev);
		2650	if (of_node)
		2651	pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 1);
		2652	}
		2653	#endif
2627	if (!dev->irq) {	2654	if (!dev->irq) {
2628	err("found OHCI device with no IRQ assigned. check BIOS settings!");	2655	err("found OHCI device with no IRQ assigned. check BIOS settings!");
2629	pci_disable_device (dev);	2656	pci_disable_device (dev);
Lines 2719-2724 Link Here
2719	info ("USB suspend: usb-%s", dev->slot_name);	2746	info ("USB suspend: usb-%s", dev->slot_name);
2720	ohci->sleeping = 1;	2747	ohci->sleeping = 1;
2721		2748
		2749	#ifdef CONFIG_PMAC_PBOOK
		2750	if (_machine == _MACH_Pmac)
		2751	disable_irq (ohci->irq);
		2752	/* else, 2.4 assumes shared irqs -- don't disable */
		2753	#endif
		2754
2722	/* First stop processing */	2755	/* First stop processing */
2723	spin_lock_irqsave (&usb_ed_lock, flags);	2756	spin_lock_irqsave (&usb_ed_lock, flags);
2724	ohci->hc_control &= ~(OHCI_CTRL_PLE\|OHCI_CTRL_CLE\|OHCI_CTRL_BLE\|OHCI_CTRL_IE);	2757	ohci->hc_control &= ~(OHCI_CTRL_PLE\|OHCI_CTRL_CLE\|OHCI_CTRL_BLE\|OHCI_CTRL_IE);
Lines 2732-2742 Link Here
2732	if (!readl (&ohci->regs->intrstatus) & OHCI_INTR_SF)	2765	if (!readl (&ohci->regs->intrstatus) & OHCI_INTR_SF)
2733	mdelay (1);	2766	mdelay (1);
2734		2767
2735	#ifdef CONFIG_PMAC_PBOOK
2736	if (_machine == _MACH_Pmac)
2737	disable_irq (ohci->irq);
2738	/* else, 2.4 assumes shared irqs -- don't disable */
2739	#endif
2740	/* Enable remote wakeup */	2768	/* Enable remote wakeup */
2741	writel (readl(&ohci->regs->intrenable) \| OHCI_INTR_RD, &ohci->regs->intrenable);	2769	writel (readl(&ohci->regs->intrenable) \| OHCI_INTR_RD, &ohci->regs->intrenable);
2742		2770

Lines 58-64 Link Here

(-)linux-2.4.22/drivers/usb/host/usb-ohci.h (-2 / +2 lines)
58		58
59	dma_addr_t dma;	59	dma_addr_t dma;
60	__u32 unused[3];	60	__u32 unused[3];
61	} __attribute((aligned(16)));	61	} __attribute((aligned(32)));
62	typedef struct ed ed_t;	62	typedef struct ed ed_t;
63		63
64		64
Lines 567-573 Link Here
567	return -ENOMEM;	567	return -ENOMEM;
568	ohci->dev_cache = pci_pool_create ("ohci_dev", ohci->ohci_dev,	568	ohci->dev_cache = pci_pool_create ("ohci_dev", ohci->ohci_dev,
569	sizeof (struct ohci_device),	569	sizeof (struct ohci_device),
570	16 /* byte alignment */,	570	32 /* byte alignment */,
571	0 /* no page-crossing issues */,	571	0 /* no page-crossing issues */,
572	GFP_KERNEL \| OHCI_MEM_FLAGS);	572	GFP_KERNEL \| OHCI_MEM_FLAGS);
573	if (!ohci->dev_cache)	573	if (!ohci->dev_cache)




{
	struct us_data *us;
	char local_name[32];
	spin_unlock_irq(&io_request_lock);
	
	/* This is not nice at all, but how else are we to get the
	 * data here? */
	us = (struct us_data *)sht->proc_dir;

	/* set up the name of our subdirectory under /proc/scsi/ */
	sprintf(local_name, "usb-storage-%d", us->host_number);
	sht->proc_name = kmalloc (strlen(local_name) + 1, GFP_KERNEL);
	if (!sht->proc_name) {
		spin_lock_irq(&io_request_lock);
		return 0;
	}
	strcpy(sht->proc_name, local_name);

	/* we start with no /proc directory entry */

	if (us->host) {
		us->host->hostdata[0] = (unsigned long)us;
		us->host_no = us->host->host_no;
		spin_lock_irq(&io_request_lock);
		return 1;
	}

	/* odd... didn't register properly.  Abort and free pointers */
	kfree(sht->proc_name);
	sht->proc_name = NULL;
	spin_lock_irq(&io_request_lock);
	return 0;
}


Lines 73-79 Link Here

(-)linux-2.4.22/drivers/video/Config.in (-1 / +1 lines)
73	dep_bool ' Apple "valkyrie" display support' CONFIG_FB_VALKYRIE $CONFIG_ALL_PPC	73	dep_bool ' Apple "valkyrie" display support' CONFIG_FB_VALKYRIE $CONFIG_ALL_PPC
74	bool ' Chips 65550 display support' CONFIG_FB_CT65550	74	bool ' Chips 65550 display support' CONFIG_FB_CT65550
75	bool ' IMS Twin Turbo display support' CONFIG_FB_IMSTT	75	bool ' IMS Twin Turbo display support' CONFIG_FB_IMSTT
76	bool ' S3 Trio display support' CONFIG_FB_S3TRIO	76	dep_bool ' S3 Trio display support' CONFIG_FB_S3TRIO $CONFIG_ALL_PPC
77	tristate ' VGA 16-color graphics console' CONFIG_FB_VGA16	77	tristate ' VGA 16-color graphics console' CONFIG_FB_VGA16
78	fi	78	fi
79	if [ "$CONFIG_PARISC" = "y" ]; then	79	if [ "$CONFIG_PARISC" = "y" ]; then

Lines 124-129 Link Here

(-)linux-2.4.22/drivers/video/aty/atyfb.h (+1 lines)
124	#endif	124	#endif
125	} fbcon_cmap;	125	} fbcon_cmap;
126	u8 blitter_may_be_busy;	126	u8 blitter_may_be_busy;
		127	int asleep;
127	#ifdef __sparc__	128	#ifdef __sparc__
128	u8 mmaped;	129	u8 mmaped;
129	int open;	130	int open;

Lines 748-753 Link Here

(-)linux-2.4.22/drivers/video/aty/atyfb_base.c (-14 / +38 lines)
748		748
749	info->current_par = *par;	749	info->current_par = *par;
750		750
		751	if (info->asleep)
		752	return;
751	if (info->blitter_may_be_busy)	753	if (info->blitter_may_be_busy)
752	wait_for_idle(info);	754	wait_for_idle(info);
753	tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);	755	tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
Lines 1192-1197 Link Here
1192	return -EINVAL;	1194	return -EINVAL;
1193	par->crtc.xoffset = xoffset;	1195	par->crtc.xoffset = xoffset;
1194	par->crtc.yoffset = yoffset;	1196	par->crtc.yoffset = yoffset;
		1197
		1198	if (info->asleep)
		1199	return 0;
		1200
1195	set_off_pitch(par, info);	1201	set_off_pitch(par, info);
1196	return 0;	1202	return 0;
1197	}	1203	}
Lines 1660-1665 Link Here
1660	}	1666	}
1661	break;	1667	break;
1662	case PBOOK_SLEEP_NOW:	1668	case PBOOK_SLEEP_NOW:
		1669	acquire_console_sem();
1663	if (currcon >= 0)	1670	if (currcon >= 0)
1664	fb_display[currcon].dispsw = &fbcon_dummy;	1671	fb_display[currcon].dispsw = &fbcon_dummy;
1665	if (info->blitter_may_be_busy)	1672	if (info->blitter_may_be_busy)
Lines 1675-1685 Link Here
1675		1682
1676	/* Blank display and LCD */	1683	/* Blank display and LCD */
1677	atyfbcon_blank(VESA_POWERDOWN+1, (struct fb_info *)info);	1684	atyfbcon_blank(VESA_POWERDOWN+1, (struct fb_info *)info);
		1685	info->asleep = 1;
1678		1686
1679	/* Set chip to "suspend" mode */	1687	/* Set chip to "suspend" mode */
1680	result = aty_power_mgmt(1, info);	1688	result = aty_power_mgmt(1, info);
		1689	release_console_sem();
1681	break;	1690	break;
1682	case PBOOK_WAKE:	1691	case PBOOK_WAKE:
		1692	acquire_console_sem();
1683	/* Wakeup chip */	1693	/* Wakeup chip */
1684	result = aty_power_mgmt(0, info);	1694	result = aty_power_mgmt(0, info);
1685		1695
Lines 1690-1695 Link Here
1690	vfree(info->save_framebuffer);	1700	vfree(info->save_framebuffer);
1691	info->save_framebuffer = 0;	1701	info->save_framebuffer = 0;
1692	}	1702	}
		1703	info->asleep = 0;
1693	/* Restore display */	1704	/* Restore display */
1694	if (currcon >= 0) {	1705	if (currcon >= 0) {
1695	atyfb_set_dispsw(&fb_display[currcon],	1706	atyfb_set_dispsw(&fb_display[currcon],
Lines 1697-1702 Link Here
1697	info->current_par.accel_flags & FB_ACCELF_TEXT);	1708	info->current_par.accel_flags & FB_ACCELF_TEXT);
1698	}	1709	}
1699	atyfbcon_blank(0, (struct fb_info *)info);	1710	atyfbcon_blank(0, (struct fb_info *)info);
		1711	/* XXX We may want to re-call atyfb_set_par and make
		1712	* sure panning & cursor & palette are correct as we
		1713	* skipped any change to these during suspend.
		1714	*/
		1715	release_console_sem();
1700	break;	1716	break;
1701	}	1717	}
1702	}	1718	}
Lines 2720-2725 Link Here
2720	struct fb_info_aty info = (struct fb_info_aty )fb;	2736	struct fb_info_aty info = (struct fb_info_aty )fb;
2721	u8 gen_cntl;	2737	u8 gen_cntl;
2722		2738
		2739	if (info->asleep)
		2740	return;
		2741
2723	#ifdef CONFIG_PMAC_BACKLIGHT	2742	#ifdef CONFIG_PMAC_BACKLIGHT
2724	if ((_machine == _MACH_Pmac) && blank)	2743	if ((_machine == _MACH_Pmac) && blank)
2725	set_backlight_enable(0);	2744	set_backlight_enable(0);
Lines 2792-2814 Link Here
2792	info->palette[regno].red = red;	2811	info->palette[regno].red = red;
2793	info->palette[regno].green = green;	2812	info->palette[regno].green = green;
2794	info->palette[regno].blue = blue;	2813	info->palette[regno].blue = blue;
2795	i = aty_ld_8(DAC_CNTL, info) & 0xfc;	2814	if (!info->asleep) {
2796	if (M64_HAS(EXTRA_BRIGHT))	2815	i = aty_ld_8(DAC_CNTL, info) & 0xfc;
2797	i \|= 0x2; /DAC_CNTL\|0x2 turns off the extra brightness for gt/	2816	if (M64_HAS(EXTRA_BRIGHT))
2798	aty_st_8(DAC_CNTL, i, info);	2817	i \|= 0x2; /DAC_CNTL\|0x2 turns off the extra brightness for gt/
2799	aty_st_8(DAC_MASK, 0xff, info);	2818	aty_st_8(DAC_CNTL, i, info);
2800	scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;	2819	aty_st_8(DAC_MASK, 0xff, info);
		2820	scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
2801	#ifdef CONFIG_ATARI	2821	#ifdef CONFIG_ATARI
2802	out_8(&info->aty_cmap_regs->windex, regno << scale);	2822	out_8(&info->aty_cmap_regs->windex, regno << scale);
2803	out_8(&info->aty_cmap_regs->lut, red);	2823	out_8(&info->aty_cmap_regs->lut, red);
2804	out_8(&info->aty_cmap_regs->lut, green);	2824	out_8(&info->aty_cmap_regs->lut, green);
2805	out_8(&info->aty_cmap_regs->lut, blue);	2825	out_8(&info->aty_cmap_regs->lut, blue);
2806	#else	2826	#else
2807	writeb(regno << scale, &info->aty_cmap_regs->windex);	2827	writeb(regno << scale, &info->aty_cmap_regs->windex);
2808	writeb(red, &info->aty_cmap_regs->lut);	2828	writeb(red, &info->aty_cmap_regs->lut);
2809	writeb(green, &info->aty_cmap_regs->lut);	2829	writeb(green, &info->aty_cmap_regs->lut);
2810	writeb(blue, &info->aty_cmap_regs->lut);	2830	writeb(blue, &info->aty_cmap_regs->lut);
2811	#endif	2831	#endif
		2832	}
2812	if (regno < 16)	2833	if (regno < 16)
2813	switch (info->current_par.crtc.bpp) {	2834	switch (info->current_par.crtc.bpp) {
2814	#ifdef FBCON_HAS_CFB16	2835	#ifdef FBCON_HAS_CFB16
Lines 2859-2864 Link Here
2859	struct vc_data *conp = p->conp;	2880	struct vc_data *conp = p->conp;
2860	u32 yres, yoffset, sy, height;	2881	u32 yres, yoffset, sy, height;
2861		2882
		2883	if (info->asleep)
		2884	return 0;
		2885
2862	yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;	2886	yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
2863	yoffset = fb_display[con].var.yoffset;	2887	yoffset = fb_display[con].var.yoffset;
2864		2888




	const u8 *blue = cursor_color_map;
	int i;

	if (!c || fb->asleep)
		return;

#ifdef __sparc__

	u8 *ram, m, b;
	int x, y;

	if (!c || fb->asleep)
		return;

#ifdef __sparc__

	u16 xoff, yoff;
	int x, y;

	if (!c || fb->asleep)
		return;

#ifdef __sparc__

	    c->mask[i][height-1] = (j >= 8) ? 0xff : (0xff << (8 - j));
	}

	if (!fb->asleep) {
		aty_set_cursor_color(fb);
		aty_set_cursor_shape(fb);
	}
    }
    return 1;
}




#include <linux/ioport.h>
#include <asm/io.h>

#ifdef CONFIG_ALL_PPC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <video/macmodes.h>

#define DBG(fmt, args...)
#endif

#ifndef CONFIG_ALL_PPC
/* default mode */
static struct fb_var_screeninfo default_var __initdata = {
    /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */

    0, FB_VMODE_NONINTERLACED
};

#else /* CONFIG_ALL_PPC */
/* default to 1024x768 at 75Hz on PPC - this will work
 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
static struct fb_var_screeninfo default_var = {

    0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
    FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
};
#endif /* CONFIG_ALL_PPC */

/* default modedb mode */
/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */

 };

/* packed BIOS settings */
#ifndef CONFIG_ALL_PPC
typedef struct {
	u8 clock_chip_type;
	u8 struct_size;

	u32 XCLK_min_freq;
	u32 XCLK_max_freq;
} __attribute__ ((packed)) PLL_BLOCK;
#endif /* !CONFIG_ALL_PPC */

/* onboard memory information */
struct aty128_meminfo {


static char *mode_option __initdata = NULL;

#ifdef CONFIG_ALL_PPC
static int default_vmode __initdata = VMODE_1024_768_60;
static int default_cmode __initdata = CMODE_8;
#endif

                               const struct aty128_chip_info *aci);
static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
				*board_list, struct fb_info_aty128 *new_node);
#if !defined(CONFIG_ALL_PPC) && !defined(__sparc__)
static void __init aty128_get_pllinfo(struct fb_info_aty128 *info,
			char *bios_seg);
static char __init *aty128find_ROM(struct fb_info_aty128 *info);

            mtrr = 0;
        }
#endif
#ifdef CONFIG_ALL_PPC
        /* vmode and cmode depreciated */
	else if (!strncmp(this_opt, "vmode:", 6)) {
            unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);

		break;
            }
        }
#endif /* CONFIG_ALL_PPC */
        else
            mode_option = this_opt;
    }

#endif
    
    var = default_var;
#ifdef CONFIG_ALL_PPC
    if (_machine == _MACH_Pmac) {
        if (mode_option) {
            if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))

                var = default_var;
        }
    } else
#endif /* CONFIG_ALL_PPC */
    {
        if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
                          &defaultmode, 8) == 0)

	struct fb_info_aty128 *info = NULL;
	unsigned long fb_addr, reg_addr;
	int err;
#if !defined(CONFIG_ALL_PPC) && !defined(__sparc__)
	char *bios_seg = NULL;
#endif


		goto err_out;
	}

#if !defined(CONFIG_ALL_PPC) && !defined(__sparc__)
	if (!(bios_seg = aty128find_ROM(info)))
		printk(KERN_INFO "aty128fb: Rage128 BIOS not located. "
					"Guessing...\n");



/* PPC and Sparc cannot read video ROM */
#if !defined(CONFIG_ALL_PPC) && !defined(__sparc__)
static char __init
*aty128find_ROM(struct fb_info_aty128 *info)
{

			info->constants.dotclock);

}           
#endif /* !CONFIG_ALL_PPC */


/* fill in known card constants if pll_block is not available */
static void __init
aty128_timings(struct fb_info_aty128 *info)
{
#ifdef CONFIG_ALL_PPC
    /* instead of a table lookup, assume OF has properly
     * setup the PLL registers and use their values
     * to set the XCLK values and reference divider values */

    if (!info->constants.dotclock)
        info->constants.dotclock = 2950;

#ifdef CONFIG_ALL_PPC
    x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
    xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
    Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;

#define ATY_MIRROR_CRT_ON	0x00000002

/* out param: u32*	backlight value: 0 to 15 */
#define FBIO_ATY128_GET_MIRROR	_IOR('@', 1, __u32)
/* in param: u32*	backlight value: 0 to 15 */
#define FBIO_ATY128_SET_MIRROR	_IOW('@', 2, __u32)

static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
		       u_long arg, int con, struct fb_info *info)

Lines 448-453 Link Here

(-)linux-2.4.22/drivers/video/offb.c (+4 lines)
448	unsigned long regbase = dp->addrs[1].address;	448	unsigned long regbase = dp->addrs[1].address;
449	info->cmap_adr = ioremap(regbase, 0x1FFF);	449	info->cmap_adr = ioremap(regbase, 0x1FFF);
450	info->cmap_type = cmap_radeon;	450	info->cmap_type = cmap_radeon;
		451	} else if (dp && !strncmp(name, "ATY,BlueStar", 12)) {
		452	unsigned long regbase = dp->addrs[2].address;
		453	info->cmap_adr = ioremap(regbase, 0x1FFF);
		454	info->cmap_type = cmap_radeon;
451	} else if (!strncmp(name, "ATY,", 4)) {	455	} else if (!strncmp(name, "ATY,", 4)) {
452	/* Hrm... this is bad... any recent ATI not covered	456	/* Hrm... this is bad... any recent ATI not covered
453	* by the previous cases will get there, while this	457	* by the previous cases will get there, while this

Lines 368-373 Link Here

(-)linux-2.4.22/drivers/video/radeon.h (+9 lines)
368	#define DST_PITCH_OFFSET 0x142C	368	#define DST_PITCH_OFFSET 0x142C
369	#define DEFAULT_PITCH_OFFSET 0x16E0	369	#define DEFAULT_PITCH_OFFSET 0x16E0
370	#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8	370	#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
		371	#define SRC_PITCH_OFFSET 0x1428
		372	#define DST_PITCH_OFFSET 0x142C
371	#define DP_GUI_MASTER_CNTL 0x146C	373	#define DP_GUI_MASTER_CNTL 0x146C
372	#define SC_TOP_LEFT 0x16EC	374	#define SC_TOP_LEFT 0x16EC
373	#define SC_BOTTOM_RIGHT 0x16F0	375	#define SC_BOTTOM_RIGHT 0x16F0
Lines 376-381 Link Here
376	#define RB2D_DSTCACHE_CTLSTAT 0x342C	378	#define RB2D_DSTCACHE_CTLSTAT 0x342C
377	#define LVDS_GEN_CNTL 0x02d0	379	#define LVDS_GEN_CNTL 0x02d0
378	#define LVDS_PLL_CNTL 0x02d4	380	#define LVDS_PLL_CNTL 0x02d4
		381	#define FP2_GEN_CNTL 0x0288
379	#define TMDS_CNTL 0x0294	382	#define TMDS_CNTL 0x0294
380	#define TMDS_CRC 0x02a0	383	#define TMDS_CRC 0x02a0
381	#define TMDS_TRANSMITTER_CNTL 0x02a4	384	#define TMDS_TRANSMITTER_CNTL 0x02a4
Lines 801-806 Link Here
801	/* MPLL_CNTL bit constants */	804	/* MPLL_CNTL bit constants */
802	#define MPLL_RESET 0x00000001	805	#define MPLL_RESET 0x00000001
803		806
		807	/* MDLL_CKO bit constants */
		808	#define MCKOA_SLEEP 0x00000001
		809	#define MCKOA_RESET 0x00000002
		810	#define MCKOA_REF_SKEW_MASK 0x00000700
		811	#define MCKOA_FB_SKEW_MASK 0x00007000
		812
804	/* MDLL_RDCKA bit constants */	813	/* MDLL_RDCKA bit constants */
805	#define MRDCKA0_SLEEP 0x00000001	814	#define MRDCKA0_SLEEP 0x00000001
806	#define MRDCKA0_RESET 0x00000002	815	#define MRDCKA0_RESET 0x00000002

Lines 9-15 Link Here

(-)linux-2.4.22/drivers/video/riva/Makefile (-1 / +1 lines)
9		9
10	O_TARGET := rivafb.o	10	O_TARGET := rivafb.o
11		11
12	obj-y := fbdev.o riva_hw.o accel.o	12	obj-y := fbdev.o nv_setup.o riva_hw.o accel.o
13	obj-m := $(O_TARGET)	13	obj-m := $(O_TARGET)
14		14
15	include $(TOPDIR)/Rules.make	15	include $(TOPDIR)/Rules.make





inline void wait_for_idle(struct rivafb_info *rinfo)
{
	mb();
	while (rinfo->riva.Busy(&rinfo->riva));
}



	RIVA_FIFO_FREE(rinfo->riva, Bitmap, 2);
	rinfo->riva.Bitmap->UnclippedRectangle[0].TopLeft     = (sx << 16) | sy; 
	wmb();
	rinfo->riva.Bitmap->UnclippedRectangle[0].WidthHeight = (width << 16) | height;
	wmb();
}

static void fbcon_riva_bmove(struct display *p, int sy, int sx, int dy, int dx,

	RIVA_FIFO_FREE(rinfo->riva, Blt, 3);
	rinfo->riva.Blt->TopLeftSrc  = (sy << 16) | sx;
	rinfo->riva.Blt->TopLeftDst  = (dy << 16) | dx;
	wmb();
	rinfo->riva.Blt->WidthHeight = (height  << 16) | width;

	wait_for_idle(rinfo);

        rinfo->riva.Bitmap->Color1E           = fgx;
        rinfo->riva.Bitmap->WidthHeightInE  = (h << 16) | 32;
        rinfo->riva.Bitmap->WidthHeightOutE = (h << 16) | 32;
	wmb();
        rinfo->riva.Bitmap->PointE          = (yy << 16) | (xx & 0xFFFF);
	wmb();
	
	d = &rinfo->riva.Bitmap->MonochromeData01E;
	for (i = h; i > 0; i-=16) {

			cnt = i;
		RIVA_FIFO_FREE(rinfo->riva, Bitmap, cnt);
		for (j = 0; j < cnt; j++) {
			if (w <= 8) {
#ifdef __BIG_ENDIAN
				cdat2 = (*cdat++) << 24;
#else
				cdat2 = *cdat++;
#endif				
			} else {
#ifdef __BIG_ENDIAN
				cdat2 = *((u16*)cdat)++;
#else
				cdat2 = (*((u16*)cdat)++) << 16;
#endif			
			}
			fbcon_reverse_order(&cdat2);
			d[j] = cdat2;
		}


	RIVA_FIFO_FREE(rinfo->riva, Rop, 1);
	rinfo->riva.Rop->Rop3 = 0x66; // XOR
	wmb();
	riva_rectfill(rinfo, yy, xx, fontheight(p), fontwidth(p), 0x0f);
	RIVA_FIFO_FREE(rinfo->riva, Rop, 1);
	rinfo->riva.Rop->Rop3 = 0xCC; // back to COPY
	wmb();
}

static void fbcon_riva8_clear_margins(struct vc_data *conp, struct display *p,

	setup:		fbcon_riva8_setup,
	bmove:		fbcon_riva_bmove,
	clear:		fbcon_riva8_clear,
#ifdef __BIG_ENDIAN
	putc:		fbcon_cfb8_putc,
	putcs:		fbcon_cfb8_putcs,
	revc:		fbcon_cfb8_revc,
	clear_margins:	fbcon_cfb8_clear_margins,
#else
	putc:		fbcon_riva8_putc,
	putcs:		fbcon_riva8_putcs,
	revc:		fbcon_riva8_revc,
	clear_margins:	fbcon_riva8_clear_margins,
#endif	
	fontwidthmask:	FONTWIDTHRANGE(4, 16)
};
#endif


	RIVA_FIFO_FREE(rinfo->riva, Rop, 1);
	rinfo->riva.Rop->Rop3 = 0x66; // XOR
	wmb();
	riva_rectfill(rinfo, yy, xx, fontheight(p), fontwidth(p), 0xffffffff);
	RIVA_FIFO_FREE(rinfo->riva, Rop, 1);
	rinfo->riva.Rop->Rop3 = 0xCC; // back to COPY
	wmb();
}
#endif


	setup:		fbcon_riva16_setup,
	bmove:		fbcon_riva_bmove,
	clear:		fbcon_riva16_clear,
#ifdef __BIG_ENDIAN
	putc:		fbcon_cfb16_putc,
	putcs:		fbcon_cfb16_putcs,
	revc:		fbcon_cfb16_revc,
	clear_margins:	fbcon_cfb16_clear_margins,
#else
	putc:		fbcon_riva16_putc,
	putcs:		fbcon_riva16_putcs,
	revc:		fbcon_riva1632_revc,
	clear_margins:	fbcon_riva16_clear_margins,
#endif
	fontwidthmask:	FONTWIDTHRANGE(4, 16)
};
#endif

	setup:		fbcon_riva32_setup,
	bmove:		fbcon_riva_bmove,
	clear:		fbcon_riva32_clear,
#ifdef __BIG_ENDIAN
	putc:		fbcon_cfb32_putc,
	putcs:		fbcon_cfb32_putcs,
	revc:		fbcon_cfb32_revc,
	clear_margins:	fbcon_cfb32_clear_margins,
#else
	putc:		fbcon_riva32_putc,
	putcs:		fbcon_riva32_putcs,
	revc:		fbcon_riva1632_revc,
	clear_margins:	fbcon_riva32_clear_margins,
#endif
	fontwidthmask:	FONTWIDTHRANGE(4, 16)
};
#endif

Lines 1-12 Link Here

(-)linux-2.4.22/drivers/video/riva/fbdev.c (-193 / +416 lines)
1	/*	1	/*
2	* linux/drivers/video/riva/fbdev.c	2	* linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3	*	3	*
4	* nVidia RIVA 128/TNT/TNT2/GeForce2/3 fb driver	4	* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5	*
6	* Maintained by Ani Joshi <ajoshi@kernel.crashing.org>
7	*	5	*
8	* Copyright 1999-2000 Jeff Garzik	6	* Copyright 1999-2000 Jeff Garzik
9	* Copyright 2000-2003 Ani Joshi
10	*	7	*
11	* Contributors:	8	* Contributors:
12	*	9	*
Lines 17-22 Link Here
17	*	14	*
18	* Jindrich Makovicka: Accel code help, hw cursor, mtrr	15	* Jindrich Makovicka: Accel code help, hw cursor, mtrr
19	*	16	*
		17	* Paul Richards: Bug fixes, updates
		18	*
		19	* Benjamin Herrenschmidt: Fix accel on big endian, PPC fixes
		20	*
20	* Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven	21	* Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
21	* Includes riva_hw.c from nVidia, see copyright below.	22	* Includes riva_hw.c from nVidia, see copyright below.
22	* KGI code provided the basis for state storage, init, and mode switching.	23	* KGI code provided the basis for state storage, init, and mode switching.
Lines 55-64 Link Here
55	#error This driver requires PCI support.	56	#error This driver requires PCI support.
56	#endif	57	#endif
57		58
58		59	#include <linux/adb.h>
		60	#include <linux/pmu.h>
		61	#include <asm/prom.h>
		62	#include <asm/pci-bridge.h>
59		63
60	/* version number of this driver */	64	/* version number of this driver */
61	#define RIVAFB_VERSION "0.9.4"	65	#define RIVAFB_VERSION "0.9.4b"
62		66
63		67
64		68
Lines 131-153 Link Here
131	CH_RIVA_128 = 0,	135	CH_RIVA_128 = 0,
132	CH_RIVA_TNT,	136	CH_RIVA_TNT,
133	CH_RIVA_TNT2,	137	CH_RIVA_TNT2,
134	CH_RIVA_UTNT2, /* UTNT2 */	138	CH_RIVA_UTNT2,
135	CH_RIVA_VTNT2, /* VTNT2 */	139	CH_RIVA_VTNT2,
136	CH_RIVA_UVTNT2, /* VTNT2 */	140	CH_RIVA_UVTNT2,
137	CH_RIVA_ITNT2, /* ITNT2 */	141	CH_RIVA_ITNT2,
138	CH_GEFORCE_SDR,	142	CH_GEFORCE_SDR,
139	CH_GEFORCE_DDR,	143	CH_GEFORCE_DDR,
140	CH_QUADRO,	144	CH_QUADRO,
141	CH_GEFORCE2_MX,	145	CH_GEFORCE2_MX,
		146	CH_GEFORCE2_MX2,
		147	CH_GEFORCE2_GO,
142	CH_QUADRO2_MXR,	148	CH_QUADRO2_MXR,
143	CH_GEFORCE2_GTS,	149	CH_GEFORCE2_GTS,
		150	CH_GEFORCE2_GTS2,
144	CH_GEFORCE2_ULTRA,	151	CH_GEFORCE2_ULTRA,
145	CH_QUADRO2_PRO,	152	CH_QUADRO2_PRO,
146	CH_GEFORCE2_GO,	153	CH_GEFORCE4_MX_460,
147	CH_GEFORCE3,	154	CH_GEFORCE4_MX_440,
148	CH_GEFORCE3_1,	155	CH_GEFORCE4_MX_420,
149	CH_GEFORCE3_2,	156	CH_GEFORCE4_440_GO,
150	CH_QUADRO_DDC	157	CH_GEFORCE4_420_GO,
		158	CH_GEFORCE4_420_GO_M32,
		159	CH_QUADRO4_500XGL,
		160	CH_GEFORCE4_440_GO_M64,
		161	CH_QUADRO4_200,
		162	CH_QUADRO4_550XGL,
		163	CH_QUADRO4_500_GOGL,
		164	CH_IGEFORCE2,
		165	CH_GEFORCE3,
		166	CH_GEFORCE3_1,
		167	CH_GEFORCE3_2,
		168	CH_QUADRO_DDC,
		169	CH_GEFORCE4_TI_4600,
		170	CH_GEFORCE4_TI_4400,
		171	CH_GEFORCE4_TI_4200,
		172	CH_QUADRO4_900XGL,
		173	CH_QUADRO4_750XGL,
		174	CH_QUADRO4_700XGL
151	};	175	};
152		176
153	/* directly indexed by riva_chips enum, above */	177	/* directly indexed by riva_chips enum, above */
Lines 162-180 Link Here
162	{ "RIVA-VTNT2", NV_ARCH_04 },	186	{ "RIVA-VTNT2", NV_ARCH_04 },
163	{ "RIVA-UVTNT2", NV_ARCH_04 },	187	{ "RIVA-UVTNT2", NV_ARCH_04 },
164	{ "RIVA-ITNT2", NV_ARCH_04 },	188	{ "RIVA-ITNT2", NV_ARCH_04 },
165	{ "GeForce-SDR", NV_ARCH_10},	189	{ "GeForce-SDR", NV_ARCH_10 },
166	{ "GeForce-DDR", NV_ARCH_10},	190	{ "GeForce-DDR", NV_ARCH_10 },
167	{ "Quadro", NV_ARCH_10},	191	{ "Quadro", NV_ARCH_10 },
168	{ "GeForce2-MX", NV_ARCH_10},	192	{ "GeForce2-MX", NV_ARCH_10 },
169	{ "Quadro2-MXR", NV_ARCH_10},	193	{ "GeForce2-MX", NV_ARCH_10 },
170	{ "GeForce2-GTS", NV_ARCH_10},	194	{ "GeForce2-GO", NV_ARCH_10 },
171	{ "GeForce2-ULTRA", NV_ARCH_10},	195	{ "Quadro2-MXR", NV_ARCH_10 },
172	{ "Quadro2-PRO", NV_ARCH_10},	196	{ "GeForce2-GTS", NV_ARCH_10 },
173	{ "GeForce2-Go", NV_ARCH_10},	197	{ "GeForce2-GTS", NV_ARCH_10 },
174	{ "GeForce3", NV_ARCH_20},	198	{ "GeForce2-ULTRA", NV_ARCH_10 },
175	{ "GeForce3 Ti 200", NV_ARCH_20},	199	{ "Quadro2-PRO", NV_ARCH_10 },
176	{ "GeForce3 Ti 500", NV_ARCH_20},	200	{ "GeForce4-MX-460", NV_ARCH_20 },
177	{ "Quadro DDC", NV_ARCH_20}	201	{ "GeForce4-MX-440", NV_ARCH_20 },
		202	{ "GeForce4-MX-420", NV_ARCH_20 },
		203	{ "GeForce4-440-GO", NV_ARCH_20 },
		204	{ "GeForce4-420-GO", NV_ARCH_20 },
		205	{ "GeForce4-420-GO-M32", NV_ARCH_20 },
		206	{ "Quadro4-500-XGL", NV_ARCH_20 },
		207	{ "GeForce4-440-GO-M64", NV_ARCH_20 },
		208	{ "Quadro4-200", NV_ARCH_20 },
		209	{ "Quadro4-550-XGL", NV_ARCH_20 },
		210	{ "Quadro4-500-GOGL", NV_ARCH_20 },
		211	{ "GeForce2", NV_ARCH_20 },
		212	{ "GeForce3", NV_ARCH_20 },
		213	{ "GeForce3 Ti 200", NV_ARCH_20 },
		214	{ "GeForce3 Ti 500", NV_ARCH_20 },
		215	{ "Quadro DDC", NV_ARCH_20 },
		216	{ "GeForce4 Ti 4600", NV_ARCH_20 },
		217	{ "GeForce4 Ti 4400", NV_ARCH_20 },
		218	{ "GeForce4 Ti 4200", NV_ARCH_20 },
		219	{ "Quadro4-900-XGL", NV_ARCH_20 },
		220	{ "Quadro4-750-XGL", NV_ARCH_20 },
		221	{ "Quadro4-700-XGL", NV_ARCH_20 }
178	};	222	};
179		223
180	static struct pci_device_id rivafb_pci_tbl[] __devinitdata = {	224	static struct pci_device_id rivafb_pci_tbl[] __devinitdata = {
Lines 201-227 Link Here
201	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,	245	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
202	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },	246	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
203	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,	247	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
204	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },	248	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
		249	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
		250	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
205	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,	251	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
206	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },	252	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
207	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,	253	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
208	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },	254	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
209	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,	255	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
210	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },	256	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
211	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,	257	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
212	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },	258	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
213	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,	259	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
214	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },	260	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
215	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,	261	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
216	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },	262	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
217	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,	263	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
218	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },	264	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
219	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,	265	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
220	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },	266	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
221	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,	267	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
222	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },	268	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
223	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,	269	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
224	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },	270	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
		271	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
		272	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
		273	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
		274	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
		275	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
		276	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
		277	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
		278	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
		279	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
		280	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
		281	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
		282	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
		283	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
		284	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
		285	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
		286	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
		287	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
		288	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
		289	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
		290	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
		291	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
		292	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
		293	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
		294	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
		295	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
		296	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
		297	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
		298	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
		299	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
		300	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
		301	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
		302	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
		303	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
		304	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
225	{ 0, } /* terminate list */	305	{ 0, } /* terminate list */
226	};	306	};
227	MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);	307	MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
Lines 278-289 Link Here
278		358
279	/* command line data, set in rivafb_setup() */	359	/* command line data, set in rivafb_setup() */
280	static char fontname[40] __initdata = { 0 };	360	static char fontname[40] __initdata = { 0 };
281	static char noaccel __initdata = 0;	361	static int noaccel __initdata = 0;
282	static char nomove = 0;	362	static int nomove = 0;
283	static char nohwcursor __initdata = 0;	363	static int nohwcursor __initdata = 0;
284	static char noblink = 0;	364	static int noblink = 0;
		365	static int flatpanel __initdata = -1; /* Autodetect later */
		366	static int forceCRTC __initdata = -1;
285	#ifdef CONFIG_MTRR	367	#ifdef CONFIG_MTRR
286	static char nomtrr __initdata = 0;	368	static int nomtrr __initdata = 0;
287	#endif	369	#endif
288		370
289	#ifndef MODULE	371	#ifndef MODULE
Lines 342-348 Link Here
342	0xEB /* MISC */	424	0xEB /* MISC */
343	};	425	};
344		426
		427	/*
		428	* Here is some specific support for the eMac machine
		429	*
		430	* This machine is "special" because of it's ivad2 display
		431	* controller and fixed horizontal timing requirements.
		432	*
		433	* Right now, all I do is to set a fixed working 1024x768
		434	* mode at boot (I also have a 1280x960 at hand, if you
		435	* prefer...).
		436	*
		437	* I expect to do things better in a future 2.5 version
		438	* though.
		439	*
		440	* I also turn off the screen during blanking using IVAD
		441	* i2c accesses, that's the basis we can use to later
		442	* implement full IVAD support (geometry setting,
		443	* brightness, ...).
		444	*/
		445	#if defined(CONFIG_ALL_PPC) && defined(CONFIG_ADB_PMU)
		446
		447	static int ivad_iic_addr = -1;
		448
		449	/* Default mode for eMac */
		450	static struct fb_var_screeninfo emac_default_var = {
		451	xres: 1024,
		452	yres: 768,
		453	xres_virtual: 1024,
		454	yres_virtual: 768,
		455	xoffset: 0,
		456	yoffset: 0,
		457	bits_per_pixel: 8,
		458	grayscale: 0,
		459	red: {0, 6, 0},
		460	green: {0, 6, 0},
		461	blue: {0, 6, 0},
		462	transp: {0, 0, 0},
		463	nonstd: 0,
		464	activate: 0,
		465	height: -1,
		466	width: -1,
		467	accel_flags: 0,
		468	pixclock: 10081,
		469	left_margin: 208,
		470	right_margin: 48,
		471	upper_margin: 31,
		472	lower_margin: 1,
		473	hsync_len: 96,
		474	vsync_len: 3,
		475	sync: FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
		476	vmode: FB_VMODE_NONINTERLACED
		477	};
		478
		479	static void
		480	init_ivad(void)
		481	{
		482	if (machine_is_compatible("PowerMac4,4")) {
		483	struct device_node* np = find_devices("ivad2");
		484	unsigned int* prop;
		485
		486	if (np == NULL)
		487	return;
		488	prop = (unsigned int*)get_property(np, "iic-address", NULL);
		489	if (np == NULL) {
		490	printk(KERN_INFO "IVAD2 found but has no iic-address property !\n");
491	return;
492	}
493	ivad_iic_addr = *prop;
494	printk(KERN_INFO "Found IVAD2, iic address is: 0x%02x\n", ivad_iic_addr);
495	rivafb_default_var = emac_default_var;
496	}
497	}
498
499	#define IVAD_CONTRAST_REG 0x00
500
501	static void
502	set_ivad_contrast(u8 contrast)
503	{
504	int rc;
505
506	if (ivad_iic_addr < 0)
507	return;
508	rc = pmu_i2c_stdsub_write(PMU_I2C_BUS_POWER, ivad_iic_addr, IVAD_CONTRAST_REG, &contrast, 1);
509	if (rc < 0)
510	printk(KERN_ERR "IVAD2: Can't set contrast !\n");
511	}
345		512
		513	#endif /* defined(CONFIG_ALL_PPC) && defined(CONFIG_ADB_PMU) */
346		514
347	/* ------------------------------------------------------------------------- *	515	/* ------------------------------------------------------------------------- *
348	*	516	*
Lines 445-451 Link Here
445	if (rinfo->cursor->vbl_cnt && --rinfo->cursor->vbl_cnt == 0) {	613	if (rinfo->cursor->vbl_cnt && --rinfo->cursor->vbl_cnt == 0) {
446	rinfo->cursor->on ^= 1;	614	rinfo->cursor->on ^= 1;
447	if (rinfo->cursor->on)	615	if (rinfo->cursor->on)
448	*(rinfo->riva.CURSORPOS) = (rinfo->cursor->pos.x & 0xFFFF)	616	rinfo->riva.PRAMDAC[0x0000300/4] = (rinfo->cursor->pos.x & 0xFFFF)
449	\| (rinfo->cursor->pos.y << 16);	617	\| (rinfo->cursor->pos.y << 16);
450	rinfo->riva.ShowHideCursor(&rinfo->riva, rinfo->cursor->on);	618	rinfo->riva.ShowHideCursor(&rinfo->riva, rinfo->cursor->on);
451	if (!noblink)	619	if (!noblink)
Lines 646-652 Link Here
646	if (c->last_move_delay <= 1) { /* rapid cursor movement */	814	if (c->last_move_delay <= 1) { /* rapid cursor movement */
647	c->vbl_cnt = CURSOR_SHOW_DELAY;	815	c->vbl_cnt = CURSOR_SHOW_DELAY;
648	} else {	816	} else {
649	*(rinfo->riva.CURSORPOS) = (x & 0xFFFF) \| (y << 16);	817	rinfo->riva.PRAMDAC[0x0000300/4] = (x & 0xFFFF) \| (y << 16);
650	rinfo->riva.ShowHideCursor(&rinfo->riva, 1);	818	rinfo->riva.ShowHideCursor(&rinfo->riva, 1);
651	if (!noblink) c->vbl_cnt = CURSOR_HIDE_DELAY;	819	if (!noblink) c->vbl_cnt = CURSOR_HIDE_DELAY;
652	c->on = 1;	820	c->on = 1;
Lines 886-894 Link Here
886	hEnd = (hDisplaySize + video_mode->right_margin +	1054	hEnd = (hDisplaySize + video_mode->right_margin +
887	video_mode->hsync_len) / 8 - 1;	1055	video_mode->hsync_len) / 8 - 1;
888	hTotal = (hDisplaySize + video_mode->right_margin +	1056	hTotal = (hDisplaySize + video_mode->right_margin +
889	video_mode->hsync_len + video_mode->left_margin) / 8 - 1;	1057	video_mode->hsync_len + video_mode->left_margin) / 8 - 5;
890	hBlankStart = hDisplay;	1058	hBlankStart = hDisplay;
891	hBlankEnd = hTotal;	1059	hBlankEnd = hTotal + 4;
		1060
892	height = video_mode->yres_virtual;	1061	height = video_mode->yres_virtual;
893	vDisplay = video_mode->yres - 1;	1062	vDisplay = video_mode->yres - 1;
894	vStart = video_mode->yres + video_mode->lower_margin - 1;	1063	vStart = video_mode->yres + video_mode->lower_margin - 1;
Lines 897-924 Link Here
897	vTotal = video_mode->yres + video_mode->lower_margin +	1066	vTotal = video_mode->yres + video_mode->lower_margin +
898	video_mode->vsync_len + video_mode->upper_margin + 2;	1067	video_mode->vsync_len + video_mode->upper_margin + 2;
899	vBlankStart = vDisplay;	1068	vBlankStart = vDisplay;
900	vBlankEnd = vTotal;	1069	vBlankEnd = vTotal + 1;
901	dotClock = 1000000000 / video_mode->pixclock;	1070	dotClock = 1000000000 / video_mode->pixclock;
902		1071
903	memcpy(&newmode, &reg_template, sizeof(struct riva_regs));	1072	memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
904		1073
905	newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)	1074	if (rinfo->FlatPanel) {
906	\| SetBitField(vBlankStart,10:10,3:3)
907	\| SetBitField(vStart,10:10,2:2)
908	\| SetBitField(vDisplay,10:10,1:1)
909	\| SetBitField(vTotal,10:10,0:0);
910
911	newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
912	\| SetBitField(hDisplay,8:8,1:1)
913	\| SetBitField(hBlankStart,8:8,2:2)
914	\| SetBitField(hStart,8:8,3:3);
915
916	newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
917	\| SetBitField(vDisplay,11:11,2:2)
918	\| SetBitField(vStart,11:11,4:4)
919	\| SetBitField(vBlankStart,11:11,6:6);
920
921	if (rinfo->riva.flatPanel) {
922	vStart = vTotal - 3;	1075	vStart = vTotal - 3;
923	vEnd = vTotal - 2;	1076	vEnd = vTotal - 2;
924	vBlankStart = vStart;	1077	vBlankStart = vStart;
Lines 927-940 Link Here
927	hBlankEnd = hTotal + 4;	1080	hBlankEnd = hTotal + 4;
928	}	1081	}
929		1082
930	newmode.crtc[0x0] = Set8Bits (hTotal - 4);	1083	newmode.crtc[0x0] = Set8Bits (hTotal);
931	newmode.crtc[0x1] = Set8Bits (hDisplay);	1084	newmode.crtc[0x1] = Set8Bits (hDisplay);
932	newmode.crtc[0x2] = Set8Bits (hBlankStart);	1085	newmode.crtc[0x2] = Set8Bits (hBlankStart);
933	newmode.crtc[0x3] = SetBitField(hBlankEnd,4:0,4:0)	1086	newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) \| SetBit (7);
934	\| SetBit(7);
935	newmode.crtc[0x4] = Set8Bits (hStart);	1087	newmode.crtc[0x4] = Set8Bits (hStart);
936	newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)	1088	newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
937	\| SetBitField (hEnd, 4: 0, 4:0);	1089	\| SetBitField (hEnd, 4: 0, 4:0);
938	newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);	1090	newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
939	newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)	1091	newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
940	\| SetBitField (vDisplay, 8: 8, 1:1)	1092	\| SetBitField (vDisplay, 8: 8, 1:1)
Lines 950-986 Link Here
950	newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)	1102	newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
951	\| SetBit (5);	1103	\| SetBit (5);
952	newmode.crtc[0x12] = Set8Bits (vDisplay);	1104	newmode.crtc[0x12] = Set8Bits (vDisplay);
953	newmode.crtc[0x13] = ((width / 8) * ((bpp + 1) / 8)) & 0xFF;	1105	newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
954	newmode.crtc[0x15] = Set8Bits (vBlankStart);	1106	newmode.crtc[0x15] = Set8Bits (vBlankStart);
955	newmode.crtc[0x16] = Set8Bits (vBlankEnd);	1107	newmode.crtc[0x16] = Set8Bits (vBlankEnd);
956		1108
		1109	newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
		1110	\| SetBitField(vBlankStart,10:10,3:3)
		1111	\| SetBitField(vStart,10:10,2:2)
		1112	\| SetBitField(vDisplay,10:10,1:1)
		1113	\| SetBitField(vTotal,10:10,0:0);
		1114	newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
		1115	\| SetBitField(hDisplay,8:8,1:1)
		1116	\| SetBitField(hBlankStart,8:8,2:2)
		1117	\| SetBitField(hStart,8:8,3:3);
		1118	newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
		1119	\| SetBitField(vDisplay,11:11,2:2)
		1120	\| SetBitField(vStart,11:11,4:4)
		1121	\| SetBitField(vBlankStart,11:11,6:6);
		1122
		1123	/* CalcStateExt does this already */
		1124	/*
957	newmode.ext.bpp = bpp;	1125	newmode.ext.bpp = bpp;
958	newmode.ext.width = width;	1126	newmode.ext.width = width;
959	newmode.ext.height = height;	1127	newmode.ext.height = height;
		1128	*/
		1129	newmode.ext.interlace = 0xff; /* interlace off */
		1130
		1131	if(rinfo->riva.Architecture >= NV_ARCH_10)
		1132	rinfo->riva.CURSOR = (U032 *)(rinfo->fb_base + rinfo->riva.CursorStart);
960		1133
961	rinfo->riva.CalcStateExt(&rinfo->riva, &newmode.ext, bpp, width,	1134	rinfo->riva.CalcStateExt(&rinfo->riva, &newmode.ext, bpp, width,
962	hDisplaySize, hDisplay, hStart, hEnd,	1135	hDisplaySize, height, dotClock);
963	hTotal, height, vDisplay, vStart, vEnd,
964	vTotal, dotClock);
965		1136
966	newmode.ext.scale = rinfo->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;	1137	newmode.ext.scale = rinfo->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
967		1138	if(rinfo->FlatPanel == 1) {
968	if (rinfo->riva.flatPanel) {
969	newmode.ext.pixel \|= (1 << 7);	1139	newmode.ext.pixel \|= (1 << 7);
970	newmode.ext.scale \|= (1 << 8);	1140	newmode.ext.scale \|= (1 << 8) ;
971	}	1141	}
972		1142	if(rinfo->SecondCRTC) {
973	newmode.ext.vpll2 = rinfo->riva.PRAMDAC[0x00000520/4];	1143	newmode.ext.head = rinfo->riva.PCRTC0[0x00000860/4] & ~0x00001000;
974		1144	newmode.ext.head2 = rinfo->riva.PCRTC0[0x00002860/4] \| 0x00001000;
975	#if defined(__powerpc__)	1145	newmode.ext.crtcOwner = 3;
976	/*
977	* XXX only Mac cards use second DAC for flat panel
978	*/
979	if (rinfo->riva.flatPanel) {
980	newmode.ext.pllsel \|= 0x20000800;	1146	newmode.ext.pllsel \|= 0x20000800;
981	newmode.ext.vpll2 = newmode.ext.vpll;	1147	newmode.ext.vpll2 = newmode.ext.vpll;
		1148	} else if(rinfo->riva.twoHeads) {
		1149	newmode.ext.head = rinfo->riva.PCRTC0[0x00000860/4] \| 0x00001000;
		1150	newmode.ext.head2 = rinfo->riva.PCRTC0[0x00002860/4] & ~0x00001000;
		1151	newmode.ext.crtcOwner = 0;
		1152	newmode.ext.vpll2 = rinfo->riva.PRAMDAC0[0x00000520/4];
982	}	1153	}
983	#endif	1154
		1155	newmode.ext.cursorConfig = 0x02000100;
		1156
		1157	newmode.misc_output &= 0x3f;
		1158	if ((video_mode->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
		1159	newmode.misc_output \|= 0x40;
		1160	if ((video_mode->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
		1161	newmode.misc_output \|= 0x80;
		1162
984	rinfo->current_state = newmode;	1163	rinfo->current_state = newmode;
985	riva_load_state(rinfo, &rinfo->current_state);	1164	riva_load_state(rinfo, &rinfo->current_state);
986		1165
Lines 1463-1468 Link Here
1463		1642
1464	accel = v.accel_flags & FB_ACCELF_TEXT;	1643	accel = v.accel_flags & FB_ACCELF_TEXT;
1465		1644
		1645	/* Accel seem to not work properly on GeForce4's yet...*/
		1646	if (rivainfo->riva.Architecture == NV_ARCH_20) {
		1647	v.accel_flags &= ~FB_ACCELF_TEXT;
		1648	accel = 0;
		1649	}
		1650
1466	switch (v.bits_per_pixel) {	1651	switch (v.bits_per_pixel) {
1467	#ifdef FBCON_HAS_CFB8	1652	#ifdef FBCON_HAS_CFB8
1468	case 1 ... 8:	1653	case 1 ... 8:
Lines 1802-1807 Link Here
1802	vesa \|= 0xc0;	1987	vesa \|= 0xc0;
1803	break;	1988	break;
1804	}	1989	}
		1990	#if defined(CONFIG_ALL_PPC) && defined(CONFIG_ADB_PMU)
		1991	set_ivad_contrast(0);
		1992	#endif
		1993	} else {
		1994	#if defined(CONFIG_ALL_PPC) && defined(CONFIG_ADB_PMU)
		1995	set_ivad_contrast(0xff);
		1996	#endif
1805	}	1997	}
1806		1998
1807	SEQout(rinfo, 0x01, tmp);	1999	SEQout(rinfo, 0x01, tmp);
Lines 1841-1847 Link Here
1841	if (rinfo->use_default_var)	2033	if (rinfo->use_default_var)
1842	/* We will use the modified default var */	2034	/* We will use the modified default var */
1843	rinfo->disp.var = rivafb_default_var;	2035	rinfo->disp.var = rivafb_default_var;
1844		2036
1845	return 0;	2037	return 0;
1846	}	2038	}
1847		2039
Lines 1877-1882 Link Here
1877		2069
1878	riva_set_dispsw(rinfo, disp);	2070	riva_set_dispsw(rinfo, disp);
1879		2071
		2072	if (disp->var.accel_flags & FB_ACCELF_TEXT) {
		2073	if (nomove)
		2074	disp->scrollmode = SCROLL_YNOMOVE;
		2075	else
		2076	disp->scrollmode = 0;
		2077	} else
		2078	disp->scrollmode = SCROLL_YREDRAW;
		2079
1880	DPRINTK("EXIT, returning 0\n");	2080	DPRINTK("EXIT, returning 0\n");
1881	return 0;	2081	return 0;
1882		2082
Lines 1913-1931 Link Here
1913	}	2113	}
1914		2114
1915	#ifdef CONFIG_ALL_PPC	2115	#ifdef CONFIG_ALL_PPC
		2116	/*
		2117	* For now we only retreive EDID for flat panels, we'll fix that
		2118	* once we know what to do of non-flat panel EDIDs, that is typically
		2119	* in 2.5 --BenH.
		2120	*/
1916	static int riva_get_EDID_OF(struct rivafb_info *rinfo)	2121	static int riva_get_EDID_OF(struct rivafb_info *rinfo)
1917	{	2122	{
1918	struct device_node *dp;	2123	struct device_node *dp;
1919	unsigned char *pedid = NULL;	2124	unsigned char *pedid = NULL;
1920		2125	unsigned char *disptype = NULL;
1921	dp = pci_device_to_OF_node(rinfo->pd);	2126	static char *propnames[] = {
1922	pedid = (unsigned char *)get_property(dp, "EDID,B", 0);	2127	"DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1923		2128	int i;
1924	if (pedid) {	2129
1925	rinfo->EDID = pedid;	2130	dp = pci_device_to_OF_node(rinfo->pd);
1926	return 1;	2131	for (; dp != NULL; dp = dp->child) {
1927	} else	2132	disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1928	return 0;	2133	if (disptype == NULL)
		2134	continue;
		2135	if (strncmp(disptype, "LCD", 3) != 0)
		2136	continue;
		2137	for (i = 0; propnames[i] != NULL; ++i) {
		2138	pedid = (unsigned char *)
		2139	get_property(dp, propnames[i], NULL);
		2140	if (pedid != NULL) {
		2141	rinfo->EDID = pedid;
		2142	return 1;
		2143	}
		2144	}
		2145	}
		2146	return 0;
1929	}	2147	}
1930	#endif /* CONFIG_ALL_PPC */	2148	#endif /* CONFIG_ALL_PPC */
1931		2149
Lines 1939-1966 Link Here
1939	/* jump to detailed timing block section */	2157	/* jump to detailed timing block section */
1940	block += 54;	2158	block += 54;
1941		2159
1942	rinfo->clock = (block[0] + (block[1] << 8));	2160	rinfo->clock = (block[0] + (block[1] << 8));
1943	rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));	2161	rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1944	rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));	2162	rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1945	rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));	2163	rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1946	rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));	2164	rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1947	rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));	2165	rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1948	rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));	2166	rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1949	rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));	2167	rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1950	rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));	2168	rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1951	rinfo->interlaced = ((block[17] & 0x80) >> 7);	2169	rinfo->interlaced = ((block[17] & 0x80) >> 7);
1952	rinfo->synct = ((block[17] & 0x18) >> 3);	2170	rinfo->synct = ((block[17] & 0x18) >> 3);
1953	rinfo->misc = ((block[17] & 0x06) >> 1);	2171	rinfo->misc = ((block[17] & 0x06) >> 1);
1954	rinfo->hAct_high = rinfo->vAct_high = 0;	2172	rinfo->hAct_high = rinfo->vAct_high = 0;
1955	if (rinfo->synct == 3) {	2173	if (rinfo->synct == 3) {
1956	if (rinfo->misc & 2)	2174	if (rinfo->misc & 2)
1957	rinfo->hAct_high = 1;	2175	rinfo->hAct_high = 1;
1958	if (rinfo->misc & 1)	2176	if (rinfo->misc & 1)
1959	rinfo->vAct_high = 1;	2177	rinfo->vAct_high = 1;
1960	}	2178	}
1961		2179
1962	printk("rivafb: detected DFP panel size from EDID: %dx%d\n",	2180	printk(KERN_INFO PFX
1963	rinfo->panel_xres, rinfo->panel_yres);	2181	"detected DFP panel size from EDID: %dx%d\n",
		2182	rinfo->panel_xres, rinfo->panel_yres);
1964		2183
1965	rinfo->got_dfpinfo = 1;	2184	rinfo->got_dfpinfo = 1;
1966		2185
Lines 2020-2026 Link Here
2020	if (riva_dfp_parse_EDID(rinfo))	2239	if (riva_dfp_parse_EDID(rinfo))
2021	riva_update_default_var(rinfo);	2240	riva_update_default_var(rinfo);
2022		2241
2023	rinfo->riva.flatPanel = rinfo->got_dfpinfo;	2242	if (rinfo->FlatPanel == -1 && rinfo->got_dfpinfo == 1) /* if user specified flatpanel, we respect that */
		2243	rinfo->FlatPanel = 1;
2024	}	2244	}
2025		2245
2026		2246
Lines 2049-2054 Link Here
2049	rinfo->drvr_name = rci->name;	2269	rinfo->drvr_name = rci->name;
2050	rinfo->riva.Architecture = rci->arch_rev;	2270	rinfo->riva.Architecture = rci->arch_rev;
2051		2271
		2272	rinfo->Chipset = (pd->vendor << 16) \| pd->device;
		2273	printk(KERN_INFO PFX "nVidia device/chipset %X\n", rinfo->Chipset);
		2274
		2275	rinfo->FlatPanel = flatpanel;
		2276	if (flatpanel == 1)
		2277	printk(KERN_INFO PFX "flatpanel support enabled\n");
		2278	rinfo->forceCRTC = forceCRTC;
		2279
2052	rinfo->pd = pd;	2280	rinfo->pd = pd;
2053	rinfo->base0_region_size = pci_resource_len(pd, 0);	2281	rinfo->base0_region_size = pci_resource_len(pd, 0);
2054	rinfo->base1_region_size = pci_resource_len(pd, 1);	2282	rinfo->base1_region_size = pci_resource_len(pd, 1);
Lines 2061-2164 Link Here
2061	cmd \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);	2289	cmd \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
2062	pci_write_config_word(pd, PCI_COMMAND, cmd);	2290	pci_write_config_word(pd, PCI_COMMAND, cmd);
2063	}	2291	}
2064		2292
2065	rinfo->ctrl_base_phys = pci_resource_start(rinfo->pd, 0);	2293	rinfo->ctrl_base_phys = pci_resource_start(rinfo->pd, 0);
2066	rinfo->fb_base_phys = pci_resource_start(rinfo->pd, 1);	2294	rinfo->fb_base_phys = pci_resource_start(rinfo->pd, 1);
2067		2295
		2296	if (!request_mem_region(rinfo->ctrl_base_phys,
		2297	rinfo->base0_region_size, "rivafb")) {
		2298	printk(KERN_ERR PFX "cannot reserve MMIO region\n");
		2299	goto err_out_kfree;
		2300	}
		2301
2068	rinfo->ctrl_base = ioremap(rinfo->ctrl_base_phys,	2302	rinfo->ctrl_base = ioremap(rinfo->ctrl_base_phys,
2069	rinfo->base0_region_size);	2303	rinfo->base0_region_size);
2070	if (!rinfo->ctrl_base) {	2304	if (!rinfo->ctrl_base) {
2071	printk(KERN_ERR PFX "cannot ioremap MMIO base\n");	2305	printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2072	goto err_out_free_base1;	2306	goto err_out_free_base0;
2073	}	2307	}
2074		2308
2075	riva_get_EDID(rinfo);	2309	riva_get_EDID(rinfo);
2076		2310
2077	riva_get_dfpinfo(rinfo);	2311	riva_get_dfpinfo(rinfo);
2078		2312
2079	rinfo->riva.EnableIRQ = 0;	2313	switch (rinfo->riva.Architecture) {
2080	rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base + 0x00680000);	2314	case NV_ARCH_03:
2081	rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base + 0x00100000);	2315	/* Riva128's PRAMIN is in the "framebuffer" space
2082	rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base + 0x00002000);	2316	* Since these cards were never made with more than 8 megabytes
2083	rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base + 0x00400000);	2317	* we can safely allocate this seperately.
2084	rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base + 0x00101000);
2085	rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base + 0x00009000);
2086	rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base + 0x00000000);
2087	rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base + 0x00800000);
2088
2089	rinfo->riva.PCIO = (U008 *)(rinfo->ctrl_base + 0x00601000);
2090	rinfo->riva.PDIO = (U008 *)(rinfo->ctrl_base + 0x00681000);
2091	rinfo->riva.PVIO = (U008 *)(rinfo->ctrl_base + 0x000C0000);
2092
2093	rinfo->riva.IO = (MISCin(rinfo) & 0x01) ? 0x3D0 : 0x3B0;
2094
2095	if (rinfo->riva.Architecture == NV_ARCH_03) {
2096	/*
2097	* We have to map the full BASE_1 aperture for Riva128's
2098	* because they use the PRAMIN set in "framebuffer" space
2099	*/	2318	*/
2100	if (!request_mem_region(rinfo->fb_base_phys,	2319	if (!request_mem_region(rinfo->fb_base_phys + 0x00C00000,
2101	rinfo->base1_region_size, "rivafb")) {	2320	0x00008000, "rivafb")) {
2102	printk(KERN_ERR PFX "cannot reserve FB region\n");	2321	printk(KERN_ERR PFX "cannot reserve PRAMIN region\n");
2103	goto err_out_free_base0;
2104	}
2105
2106	rinfo->fb_base = ioremap(rinfo->fb_base_phys,
2107	rinfo->base1_region_size);
2108	if (!rinfo->fb_base) {
2109	printk(KERN_ERR PFX "cannot ioremap FB base\n");
2110	goto err_out_iounmap_ctrl;	2322	goto err_out_iounmap_ctrl;
2111	}	2323	}
2112	}	2324	rinfo->riva.PRAMIN = ioremap(rinfo->fb_base_phys + 0x00C00000,
2113		2325	0x00008000);
2114		2326	if (!rinfo->riva.PRAMIN) {
2115	switch (rinfo->riva.Architecture) {	2327	printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2116	case NV_ARCH_03:	2328	goto err_out_free_nv3_pramin;
2117	rinfo->riva.PRAMIN = (unsigned *)(rinfo->fb_base + 0x00C00000);	2329	}
2118	break;	2330	break;
2119	case NV_ARCH_04:	2331	case NV_ARCH_04:
2120	case NV_ARCH_10:	2332	case NV_ARCH_10:
2121	case NV_ARCH_20:	2333	case NV_ARCH_20:
2122	rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base + 0x00600000);	2334	rinfo->riva.PCRTC0 = (unsigned *)(rinfo->ctrl_base + 0x00600000);
2123	rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base + 0x00710000);	2335	rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base + 0x00710000);
2124	break;	2336	break;
2125	}	2337	}
2126		2338
2127	#if defined(__powerpc__)	2339	riva_common_setup(rinfo);
2128	/*
2129	* XXX Mac cards use the second DAC for the panel
2130	*/
2131	if (rinfo->riva.flatPanel) {
2132	printk("rivafb: using second CRTC\n");
2133	rinfo->riva.PCIO = rinfo->riva.PCIO + 0x2000;
2134	rinfo->riva.PCRTC = rinfo->riva.PCRTC + 0x800;
2135	rinfo->riva.PRAMDAC = rinfo->riva.PRAMDAC + 0x800;
2136	rinfo->riva.PDIO = rinfo->riva.PDIO + 0x2000;
2137	}
2138	#endif
2139
2140	RivaGetConfig(&rinfo->riva);
2141		2340
2142	rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024;	2341	rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024;
2143	rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000;	2342	rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000;
2144		2343
2145	if (rinfo->riva.Architecture != NV_ARCH_03) {	2344	if (!request_mem_region(rinfo->fb_base_phys,
2146	/*	2345	rinfo->ram_amount, "rivafb")) {
2147	* Now the _normal_ chipsets can just map the amount of	2346	printk(KERN_ERR PFX "cannot reserve FB region\n");
2148	* real physical ram instead of the whole aperture	2347	goto err_out_iounmap_nv3_pramin;
2149	*/	2348	}
2150	if (!request_mem_region(rinfo->fb_base_phys,
2151	rinfo->ram_amount, "rivafb")) {
2152	printk(KERN_ERR PFX "cannot reserve FB region\n");
2153	goto err_out_free_base0;
2154	}
2155		2349
2156	rinfo->fb_base = ioremap(rinfo->fb_base_phys,	2350	rinfo->fb_base = ioremap(rinfo->fb_base_phys,
2157	rinfo->ram_amount);	2351	rinfo->ram_amount);
2158	if (!rinfo->fb_base) {	2352	if (!rinfo->fb_base) {
2159	printk(KERN_ERR PFX "cannot ioremap FB base\n");	2353	printk(KERN_ERR PFX "cannot ioremap FB base\n");
2160	goto err_out_iounmap_ctrl;	2354	goto err_out_free_base1;
2161	}
2162	}	2355	}
2163		2356
2164	#ifdef CONFIG_MTRR	2357	#ifdef CONFIG_MTRR
Lines 2215-2224 Link Here
2215	rivafb_exit_cursor(rinfo);	2408	rivafb_exit_cursor(rinfo);
2216	/* err_out_iounmap_fb: */	2409	/* err_out_iounmap_fb: */
2217	iounmap(rinfo->fb_base);	2410	iounmap(rinfo->fb_base);
		2411	err_out_free_base1:
		2412	release_mem_region(rinfo->fb_base_phys, rinfo->ram_amount);
		2413	err_out_iounmap_nv3_pramin:
		2414	if (rinfo->riva.Architecture == NV_ARCH_03)
		2415	iounmap((caddr_t)rinfo->riva.PRAMIN);
		2416	err_out_free_nv3_pramin:
		2417	if (rinfo->riva.Architecture == NV_ARCH_03)
		2418	release_mem_region(rinfo->fb_base_phys + 0x00C00000, 0x00008000);
2218	err_out_iounmap_ctrl:	2419	err_out_iounmap_ctrl:
2219	iounmap(rinfo->ctrl_base);	2420	iounmap(rinfo->ctrl_base);
2220	err_out_free_base1:
2221	release_mem_region(rinfo->fb_base_phys, rinfo->base1_region_size);
2222	err_out_free_base0:	2421	err_out_free_base0:
2223	release_mem_region(rinfo->ctrl_base_phys, rinfo->base0_region_size);	2422	release_mem_region(rinfo->ctrl_base_phys, rinfo->base0_region_size);
2224	err_out_kfree:	2423	err_out_kfree:
Lines 2256-2261 Link Here
2256	release_mem_region(board->fb_base_phys,	2455	release_mem_region(board->fb_base_phys,
2257	board->ram_amount);	2456	board->ram_amount);
2258		2457
		2458	if (board->riva.Architecture == NV_ARCH_03) {
		2459	iounmap((caddr_t)board->riva.PRAMIN);
		2460	release_mem_region(board->fb_base_phys + 0x00C00000, 0x00008000);
		2461	}
		2462
2259	kfree(board);	2463	kfree(board);
2260		2464
2261	pci_set_drvdata(pd, NULL);	2465	pci_set_drvdata(pd, NULL);
Lines 2301-2306 Link Here
2301	} else if (!strncmp(this_opt, "nomtrr", 6)) {	2505	} else if (!strncmp(this_opt, "nomtrr", 6)) {
2302	nomtrr = 1;	2506	nomtrr = 1;
2303	#endif	2507	#endif
		2508	} else if (!strncmp(this_opt, "forceCRTC", 9)) {
		2509	char *p;
		2510
		2511	p = this_opt + 9;
		2512	if (!p \|\| !(++p)) continue;
		2513	forceCRTC = *p - '0';
		2514	if (forceCRTC < 0 \|\| forceCRTC > 1)
		2515	forceCRTC = -1;
		2516	} else if (!strncmp(this_opt, "flatpanel", 9)) {
		2517	flatpanel = 1;
2304	} else if (!strncmp(this_opt, "nohwcursor", 10)) {	2518	} else if (!strncmp(this_opt, "nohwcursor", 10)) {
2305	nohwcursor = 1;	2519	nohwcursor = 1;
2306	} else	2520	} else
Lines 2331-2339 Link Here
2331	#ifdef MODULE	2545	#ifdef MODULE
2332	if (font) strncpy(fontname, font, sizeof(fontname)-1);	2546	if (font) strncpy(fontname, font, sizeof(fontname)-1);
2333	#endif	2547	#endif
		2548	#if defined(CONFIG_ALL_PPC) && defined(CONFIG_ADB_PMU)
		2549	init_ivad();
		2550	#endif
2334	err = pci_module_init(&rivafb_driver);	2551	err = pci_module_init(&rivafb_driver);
2335	if (err)	2552	if (err)
2336	return err;	2553	return err;
		2554	pci_register_driver(&rivafb_driver);
2337	return 0;	2555	return 0;
2338	}	2556	}
2339		2557
Lines 2357-2362 Link Here
2357	MODULE_PARM_DESC(nohwcursor, "Disables hardware cursor (0 or 1=disabled) (default=0)");	2575	MODULE_PARM_DESC(nohwcursor, "Disables hardware cursor (0 or 1=disabled) (default=0)");
2358	MODULE_PARM(noblink, "i");	2576	MODULE_PARM(noblink, "i");
2359	MODULE_PARM_DESC(noblink, "Disables hardware cursor blinking (0 or 1=disabled) (default=0)");	2577	MODULE_PARM_DESC(noblink, "Disables hardware cursor blinking (0 or 1=disabled) (default=0)");
		2578	MODULE_PARM(flatpanel, "i");
		2579	MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
		2580	MODULE_PARM(forceCRTC, "i");
		2581	MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
		2582
2360	#ifdef CONFIG_MTRR	2583	#ifdef CONFIG_MTRR
2361	MODULE_PARM(nomtrr, "i");	2584	MODULE_PARM(nomtrr, "i");
2362	MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");	2585	MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
Lines 2364-2368 Link Here
2364	#endif /* MODULE */	2587	#endif /* MODULE */
2365		2588
2366	MODULE_AUTHOR("Ani Joshi, maintainer");	2589	MODULE_AUTHOR("Ani Joshi, maintainer");
2367	MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2");	2590	MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2368	MODULE_LICENSE("GPL");	2591	MODULE_LICENSE("GPL");

Lines 41-47 Link Here

(-)linux-2.4.22/drivers/video/riva/nv4ref.h (-1 / +1 lines)
41	* GPL licensing note -- nVidia is allowing a liberal interpretation of	41	* GPL licensing note -- nVidia is allowing a liberal interpretation of
42	* the documentation restriction above, to merely say that this nVidia's	42	* the documentation restriction above, to merely say that this nVidia's
43	* copyright and disclaimer should be included with all code derived	43	* copyright and disclaimer should be included with all code derived
44	* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99	44	* from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
45	*/	45	*/
46		46
47	/***************************************************************************\	47	/***************************************************************************\




/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
/*
 * Copyright 1996-1997  David J. McKay
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/*
 * GPL licensing note -- nVidia is allowing a liberal interpretation of
 * the documentation restriction above, to merely say that this nVidia's
 * copyright and disclaimer should be included with all code derived
 * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 
 */

/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
   <jpaana@s2.org> */

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
5 20:47:06 mvojkovi Exp $ */

#include <linux/delay.h>
#include <linux/pci_ids.h>
#include "nv_type.h"
#include "rivafb.h"
#include "nvreg.h"


#ifndef CONFIG_PCI		/* sanity check */
#error This driver requires PCI support.
#endif

#define PFX "rivafb: "

static inline unsigned char MISCin(struct rivafb_info *rinfo)
{
	return (VGA_RD08(rinfo->riva.PVIO, 0x3cc));
}

static Bool 
riva_is_connected(struct rivafb_info *rinfo, Bool second)
{
	volatile U032 *PRAMDAC = rinfo->riva.PRAMDAC0;
	U032 reg52C, reg608;
	Bool present;

	if(second) PRAMDAC += 0x800;

	reg52C = PRAMDAC[0x052C/4];
	reg608 = PRAMDAC[0x0608/4];

	PRAMDAC[0x0608/4] = reg608 & ~0x00010000;

	PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE;
	mdelay(1); 
	PRAMDAC[0x052C/4] |= 1;

	rinfo->riva.PRAMDAC0[0x0610/4] = 0x94050140;
	rinfo->riva.PRAMDAC0[0x0608/4] |= 0x00001000;

	mdelay(1);

	present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE;

	rinfo->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF;

	PRAMDAC[0x052C/4] = reg52C;
	PRAMDAC[0x0608/4] = reg608;

	return present;
}

static void
riva_override_CRTC(struct rivafb_info *rinfo)
{
	printk(KERN_INFO PFX
		"Detected CRTC controller %i being used\n",
		rinfo->SecondCRTC ? 1 : 0);

	if(rinfo->forceCRTC != -1) {
		printk(KERN_INFO PFX
			"Forcing usage of CRTC %i\n", rinfo->forceCRTC);
		rinfo->SecondCRTC = rinfo->forceCRTC;
	}
}

static void
riva_is_second(struct rivafb_info *rinfo)
{
	if(rinfo->FlatPanel == 1) {
		switch(rinfo->Chipset & 0xffff) {
		case 0x0174:
		case 0x0175:
		case 0x0176:
		case 0x0177:
		case 0x0179:
		case 0x017C:
		case 0x017D:
		case 0x0186:
		case 0x0187:
		/* this might not be a good default for the chips below */
		case 0x0286:
		case 0x028C:
		case 0x0316:
		case 0x0317:
		case 0x031A:
		case 0x031B:
		case 0x031C:
		case 0x031D:
		case 0x031E:
		case 0x031F:
		case 0x0324:
		case 0x0325:
		case 0x0328:
		case 0x0329:
		case 0x032C:
		case 0x032D:
			rinfo->SecondCRTC = TRUE;
			break;
		default:
			rinfo->SecondCRTC = FALSE;
			break;
		}
	} else {
		if(riva_is_connected(rinfo, 0)) {
			if(rinfo->riva.PRAMDAC0[0x0000052C/4] & 0x100)
				rinfo->SecondCRTC = TRUE;
			else
				rinfo->SecondCRTC = FALSE;
		} else 
		if (riva_is_connected(rinfo, 1)) {
			if(rinfo->riva.PRAMDAC0[0x0000252C/4] & 0x100)
				rinfo->SecondCRTC = TRUE;
			else
				rinfo->SecondCRTC = FALSE;
		} else /* default */
			rinfo->SecondCRTC = FALSE;
	}

	riva_override_CRTC(rinfo);
}

void
riva_common_setup(struct rivafb_info *rinfo)
{
	rinfo->riva.EnableIRQ = 0;
	rinfo->riva.PRAMDAC0 = (unsigned *)(rinfo->ctrl_base + 0x00680000);
	rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base + 0x00100000);
	rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base + 0x00002000);
	rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base + 0x00400000);
	rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base + 0x00101000);
	rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base + 0x00009000);
	rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base + 0x00000000);
	rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base + 0x00800000);
	rinfo->riva.PCIO0 = (U008 *)(rinfo->ctrl_base + 0x00601000);
	rinfo->riva.PDIO0 = (U008 *)(rinfo->ctrl_base + 0x00681000);
	rinfo->riva.PVIO = (U008 *)(rinfo->ctrl_base + 0x000C0000);

	rinfo->riva.IO = (MISCin(rinfo) & 0x01) ? 0x3D0 : 0x3B0;
	
	if(rinfo->FlatPanel == -1) {
		switch(rinfo->Chipset) {
		case 0x0112:   /* known laptop chips */
		case 0x0174:
		case 0x0175:
		case 0x0176:
		case 0x0177:
		case 0x0179:
		case 0x017C:
		case 0x017D:
		case 0x0186:
		case 0x0187:
		case 0x0286:
		case 0x028C:
		case 0x0316:
		case 0x0317:
		case 0x031A:
		case 0x031B:
		case 0x031C:
		case 0x031D:
		case 0x031E:
		case 0x031F:
		case 0x0324:
		case 0x0325:
		case 0x0328:
		case 0x0329:
		case 0x032C:
		case 0x032D:
			printk(KERN_INFO PFX 
				"On a laptop.  Assuming Digital Flat Panel\n");
			rinfo->FlatPanel = 1;
			break;
		default:
			break;
		}
	}
	
	switch (rinfo->Chipset & 0x0ff0) {
	case 0x0110:
		if (rinfo->Chipset == NV_CHIP_GEFORCE2_GO)
			rinfo->SecondCRTC = TRUE; 
#if defined(__powerpc__)
		if (rinfo->FlatPanel == 1)
			rinfo->SecondCRTC = TRUE;
#endif
		riva_override_CRTC(rinfo);
		break;
	case 0x0170:
	case 0x0180:
	case 0x01F0:
	case 0x0250:
	case 0x0280:
	case 0x0300:
	case 0x0310:
	case 0x0320:
	case 0x0330:
	case 0x0340:
		riva_is_second(rinfo);
		break;
	default:
		break;
	}

	if (rinfo->riva.Architecture == NV_ARCH_03)
		rinfo->riva.PCRTC = rinfo->riva.PCRTC0 = rinfo->riva.PGRAPH;

	if (rinfo->SecondCRTC) {
		rinfo->riva.PCIO = rinfo->riva.PCIO0 + 0x2000;
		rinfo->riva.PCRTC = rinfo->riva.PCRTC0 + 0x800;
		rinfo->riva.PRAMDAC = rinfo->riva.PRAMDAC0 + 0x800;
		rinfo->riva.PDIO = rinfo->riva.PDIO0 + 0x2000;
	} else {
		rinfo->riva.PCIO = rinfo->riva.PCIO0;
		rinfo->riva.PCRTC = rinfo->riva.PCRTC0;
		rinfo->riva.PRAMDAC = rinfo->riva.PRAMDAC0;
		rinfo->riva.PDIO = rinfo->riva.PDIO0;
	}

	RivaGetConfig(&rinfo->riva, rinfo->Chipset);

	if (rinfo->FlatPanel == -1) {
		/* Fix me, need x86 DDC code */
		rinfo->FlatPanel = 0;
	}
	rinfo->riva.flatPanel = (rinfo->FlatPanel > 0) ? TRUE : FALSE;
}





/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */

#ifndef __NV_STRUCT_H__
#define __NV_STRUCT_H__

#define NV_CHIP_RIVA_128            ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
#define NV_CHIP_TNT                 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
#define NV_CHIP_TNT2                ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
#define NV_CHIP_UTNT2               ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
#define NV_CHIP_VTNT2               ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
#define NV_CHIP_UVTNT2              ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
#define NV_CHIP_ITNT2               ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
#define NV_CHIP_GEFORCE_256         ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
#define NV_CHIP_GEFORCE_DDR         ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
#define NV_CHIP_QUADRO              ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
#define NV_CHIP_GEFORCE2_MX         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
#define NV_CHIP_GEFORCE2_MX_100     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
#define NV_CHIP_QUADRO2_MXR         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
#define NV_CHIP_GEFORCE2_GO         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
#define NV_CHIP_GEFORCE2_GTS        ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
#define NV_CHIP_GEFORCE2_TI         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
#define NV_CHIP_GEFORCE2_ULTRA      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
#define NV_CHIP_QUADRO2_PRO         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
#define NV_CHIP_GEFORCE4_MX_460     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
#define NV_CHIP_GEFORCE4_MX_440     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
#define NV_CHIP_GEFORCE4_MX_420     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
#define NV_CHIP_GEFORCE4_440_GO     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
#define NV_CHIP_GEFORCE4_420_GO     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
#define NV_CHIP_QUADRO4_500XGL      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
#define NV_CHIP_QUADRO4_200         ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
#define NV_CHIP_QUADRO4_550XGL      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
#define NV_CHIP_QUADRO4_500_GOGL    ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
#define NV_CHIP_0x0180              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
#define NV_CHIP_0x0181              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
#define NV_CHIP_0x0182              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
#define NV_CHIP_0x0188              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
#define NV_CHIP_0x018A              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
#define NV_CHIP_0x018B              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
#define NV_CHIP_IGEFORCE2           ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
#define NV_CHIP_0x01F0              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
#define NV_CHIP_GEFORCE3            ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
#define NV_CHIP_GEFORCE3_TI_200     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
#define NV_CHIP_GEFORCE3_TI_500     ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
#define NV_CHIP_QUADRO_DCC          ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
#define NV_CHIP_GEFORCE4_TI_4600    ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
#define NV_CHIP_GEFORCE4_TI_4400    ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
#define NV_CHIP_GEFORCE4_TI_4200    ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
#define NV_CHIP_QUADRO4_900XGL      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
#define NV_CHIP_QUADRO4_750XGL      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
#define NV_CHIP_QUADRO4_700XGL      ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
#define NV_CHIP_0x0280              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
#define NV_CHIP_0x0281              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
#define NV_CHIP_0x0288              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
#define NV_CHIP_0x0289              ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)

#endif /* __NV_STRUCT_H__ */

Lines 41-53 Link Here

(-)linux-2.4.22/drivers/video/riva/riva_hw.c (-166 / +334 lines)
41	* GPL licensing note -- nVidia is allowing a liberal interpretation of	41	* GPL licensing note -- nVidia is allowing a liberal interpretation of
42	* the documentation restriction above, to merely say that this nVidia's	42	* the documentation restriction above, to merely say that this nVidia's
43	* copyright and disclaimer should be included with all code derived	43	* copyright and disclaimer should be included with all code derived
44	* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99	44	* from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
45	*/	45	*/
46		46
47	/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.8 2000/02/08 17:19:11 dawes Exp $ */	47	/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */
48		48
		49	#include <linux/pci_ids.h>
		50	#include <linux/pci.h>
49	#include "riva_hw.h"	51	#include "riva_hw.h"
50	#include "riva_tbl.h"	52	#include "riva_tbl.h"
		53	#include "nv_type.h"
		54
51	/*	55	/*
52	* This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT	56	* This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
53	* operate identically (except TNT has more memory and better 3D quality.	57	* operate identically (except TNT has more memory and better 3D quality.
Lines 73-104 Link Here
73	{	77	{
74	return ((chip->Rop->FifoFree < chip->FifoEmptyCount) \|\| (chip->PGRAPH[0x00000700/4] & 0x01));	78	return ((chip->Rop->FifoFree < chip->FifoEmptyCount) \|\| (chip->PGRAPH[0x00000700/4] & 0x01));
75	}	79	}
76	static void nv3LockUnlock	80
		81	static void vgaLockUnlock
77	(	82	(
78	RIVA_HW_INST *chip,	83	RIVA_HW_INST *chip,
79	int LockUnlock	84	int Lock
80	)	85	)
81	{	86	{
82	VGA_WR08(chip->PVIO, 0x3C4, 0x06);	87	U008 cr11;
83	VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);	88	VGA_WR08(chip->PCIO, 0x3D4, 0x11);
		89	cr11 = VGA_RD08(chip->PCIO, 0x3D5);
		90	if(Lock) cr11 \|= 0x80;
		91	else cr11 &= ~0x80;
		92	VGA_WR08(chip->PCIO, 0x3D5, cr11);
84	}	93	}
85	static void nv4LockUnlock	94	static void nv3LockUnlock
86	(	95	(
87	RIVA_HW_INST *chip,	96	RIVA_HW_INST *chip,
88	int LockUnlock	97	int Lock
89	)	98	)
90	{	99	{
91	VGA_WR08(chip->PCIO, 0x3D4, 0x1F);	100	VGA_WR08(chip->PVIO, 0x3C4, 0x06);
92	VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);	101	VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
		102	vgaLockUnlock(chip, Lock);
93	}	103	}
94	static void nv10LockUnlock	104	static void nv4LockUnlock
95	(	105	(
96	RIVA_HW_INST *chip,	106	RIVA_HW_INST *chip,
97	int LockUnlock	107	int Lock
98	)	108	)
99	{	109	{
100	VGA_WR08(chip->PCIO, 0x3D4, 0x1F);	110	VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
101	VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);	111	VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
		112	vgaLockUnlock(chip, Lock);
102	}	113	}
103		114
104	static int ShowHideCursor	115	static int ShowHideCursor
Lines 107-119 Link Here
107	int ShowHide	118	int ShowHide
108	)	119	)
109	{	120	{
110	int current;	121	int cursor;
111	current = chip->CurrentState->cursor1;	122	cursor = chip->CurrentState->cursor1;
112	chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) \|	123	chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) \|
113	(ShowHide & 0x01);	124	(ShowHide & 0x01);
114	VGA_WR08(chip->PCIO, 0x3D4, 0x31);	125	VGA_WR08(chip->PCIO, 0x3D4, 0x31);
115	VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);	126	VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
116	return (current & 0x01);	127	return (cursor & 0x01);
117	}	128	}
118		129
119	/****************************************************************************\	130	/****************************************************************************\
Lines 604-610 Link Here
604	nv3_sim_state sim_data;	615	nv3_sim_state sim_data;
605	unsigned int M, N, P, pll, MClk;	616	unsigned int M, N, P, pll, MClk;
606		617
607	pll = chip->PRAMDAC[0x00000504/4];	618	pll = chip->PRAMDAC0[0x00000504/4];
608	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;	619	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
609	MClk = (N * chip->CrystalFreqKHz / M) >> P;	620	MClk = (N * chip->CrystalFreqKHz / M) >> P;
610	sim_data.pix_bpp = (char)pixelDepth;	621	sim_data.pix_bpp = (char)pixelDepth;
Lines 791-800 Link Here
791	nv4_sim_state sim_data;	802	nv4_sim_state sim_data;
792	unsigned int M, N, P, pll, MClk, NVClk, cfg1;	803	unsigned int M, N, P, pll, MClk, NVClk, cfg1;
793		804
794	pll = chip->PRAMDAC[0x00000504/4];	805	pll = chip->PRAMDAC0[0x00000504/4];
795	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;	806	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
796	MClk = (N * chip->CrystalFreqKHz / M) >> P;	807	MClk = (N * chip->CrystalFreqKHz / M) >> P;
797	pll = chip->PRAMDAC[0x00000500/4];	808	pll = chip->PRAMDAC0[0x00000500/4];
798	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;	809	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
799	NVClk = (N * chip->CrystalFreqKHz / M) >> P;	810	NVClk = (N * chip->CrystalFreqKHz / M) >> P;
800	cfg1 = chip->PFB[0x00000204/4];	811	cfg1 = chip->PFB[0x00000204/4];
Lines 1052-1061 Link Here
1052	nv10_sim_state sim_data;	1063	nv10_sim_state sim_data;
1053	unsigned int M, N, P, pll, MClk, NVClk, cfg1;	1064	unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1054		1065
1055	pll = chip->PRAMDAC[0x00000504/4];	1066	pll = chip->PRAMDAC0[0x00000504/4];
1056	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;	1067	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1057	MClk = (N * chip->CrystalFreqKHz / M) >> P;	1068	MClk = (N * chip->CrystalFreqKHz / M) >> P;
1058	pll = chip->PRAMDAC[0x00000500/4];	1069	pll = chip->PRAMDAC0[0x00000500/4];
1059	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;	1070	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1060	NVClk = (N * chip->CrystalFreqKHz / M) >> P;	1071	NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1061	cfg1 = chip->PFB[0x00000204/4];	1072	cfg1 = chip->PFB[0x00000204/4];
Lines 1081-1086 Link Here
1081	}	1092	}
1082	}	1093	}
1083		1094
		1095	static void nForceUpdateArbitrationSettings
		1096	(
		1097	unsigned VClk,
		1098	unsigned pixelDepth,
		1099	unsigned *burst,
		1100	unsigned *lwm,
		1101	RIVA_HW_INST *chip
		1102	)
		1103	{
		1104	nv10_fifo_info fifo_data;
		1105	nv10_sim_state sim_data;
		1106	unsigned int M, N, P, pll, MClk, NVClk;
		1107	unsigned int uMClkPostDiv;
		1108	struct pci_dev *dev;
		1109
		1110	dev = pci_find_slot(0, 3);
		1111	pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
		1112	uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
		1113
		1114	if(!uMClkPostDiv) uMClkPostDiv = 4;
		1115	MClk = 400000 / uMClkPostDiv;
		1116
		1117	pll = chip->PRAMDAC0[0x00000500/4];
		1118	M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
		1119	NVClk = (N * chip->CrystalFreqKHz / M) >> P;
		1120	sim_data.pix_bpp = (char)pixelDepth;
		1121	sim_data.enable_video = 0;
		1122	sim_data.enable_mp = 0;
		1123
		1124	dev = pci_find_slot(0, 1);
		1125	pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
		1126	sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
		1127
		1128	sim_data.memory_width = 64;
		1129	sim_data.mem_latency = 3;
		1130	sim_data.mem_aligned = 1;
		1131	sim_data.mem_page_miss = 10;
		1132	sim_data.gr_during_vid = 0;
		1133	sim_data.pclk_khz = VClk;
		1134	sim_data.mclk_khz = MClk;
		1135	sim_data.nvclk_khz = NVClk;
		1136	nv10CalcArbitration(&fifo_data, &sim_data);
		1137	if (fifo_data.valid)
		1138	{
		1139	int b = fifo_data.graphics_burst_size >> 4;
		1140	*burst = 0;
		1141	while (b >>= 1) (*burst)++;
		1142	*lwm = fifo_data.graphics_lwm >> 3;
		1143	}
		1144	}
		1145
1084	/****************************************************************************\	1146	/****************************************************************************\
1085	* *	1147	* *
1086	* RIVA Mode State Routines *	1148	* RIVA Mode State Routines *
Lines 1093-1099 Link Here
1093	static int CalcVClock	1155	static int CalcVClock
1094	(	1156	(
1095	int clockIn,	1157	int clockIn,
1096	int double_scan,
1097	int *clockOut,	1158	int *clockOut,
1098	int *mOut,	1159	int *mOut,
1099	int *nOut,	1160	int *nOut,
Lines 1109-1126 Link Here
1109	DeltaOld = 0xFFFFFFFF;	1170	DeltaOld = 0xFFFFFFFF;
1110		1171
1111	VClk = (unsigned)clockIn;	1172	VClk = (unsigned)clockIn;
1112	if (double_scan)
1113	VClk *= 2;
1114		1173
1115	if (chip->CrystalFreqKHz == 14318)	1174	if (chip->CrystalFreqKHz == 13500)
1116	{	1175	{
1117	lowM = 8;	1176	lowM = 7;
1118	highM = 14 - (chip->Architecture == NV_ARCH_03);	1177	highM = 13 - (chip->Architecture == NV_ARCH_03);
1119	}	1178	}
1120	else	1179	else
1121	{	1180	{
1122	lowM = 7;	1181	lowM = 8;
1123	highM = 13 - (chip->Architecture == NV_ARCH_03);	1182	highM = 14 - (chip->Architecture == NV_ARCH_03);
1124	}	1183	}
1125		1184
1126	highP = 4 - (chip->Architecture == NV_ARCH_03);	1185	highP = 4 - (chip->Architecture == NV_ARCH_03);
Lines 1131-1137 Link Here
1131	{	1190	{
1132	for (M = lowM; M <= highM; M++)	1191	for (M = lowM; M <= highM; M++)
1133	{	1192	{
1134	N = (VClk * M / chip->CrystalFreqKHz) << P;	1193	N = (VClk << P) * M / chip->CrystalFreqKHz;
		1194	if(N <= 255) {
1135	Freq = (chip->CrystalFreqKHz * N / M) >> P;	1195	Freq = (chip->CrystalFreqKHz * N / M) >> P;
1136	if (Freq > VClk)	1196	if (Freq > VClk)
1137	DeltaNew = Freq - VClk;	1197	DeltaNew = Freq - VClk;
Lines 1148-1153 Link Here
1148	}	1208	}
1149	}	1209	}
1150	}	1210	}
		1211	}
1151	return (DeltaOld != 0xFFFFFFFF);	1212	return (DeltaOld != 0xFFFFFFFF);
1152	}	1213	}
1153	/*	1214	/*
Lines 1161-1175 Link Here
1161	int bpp,	1222	int bpp,
1162	int width,	1223	int width,
1163	int hDisplaySize,	1224	int hDisplaySize,
1164	int hDisplay,
1165	int hStart,
1166	int hEnd,
1167	int hTotal,
1168	int height,	1225	int height,
1169	int vDisplay,
1170	int vStart,
1171	int vEnd,
1172	int vTotal,
1173	int dotClock	1226	int dotClock
1174	)	1227	)
1175	{	1228	{
Lines 1177-1191 Link Here
1177	/*	1230	/*
1178	* Save mode parameters.	1231	* Save mode parameters.
1179	*/	1232	*/
1180	state->bpp = bpp;	1233	state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1181	state->width = width;	1234	state->width = width;
1182	state->height = height;	1235	state->height = height;
1183	/*	1236	/*
1184	* Extended RIVA registers.	1237	* Extended RIVA registers.
1185	*/	1238	*/
1186	pixelDepth = (bpp + 1)/8;	1239	pixelDepth = (bpp + 1)/8;
1187	CalcVClock(dotClock, hDisplaySize < 512, /* double scan? */	1240	CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
1188	&VClk, &m, &n, &p, chip);
1189		1241
1190	switch (chip->Architecture)	1242	switch (chip->Architecture)
1191	{	1243	{
Lines 1220-1248 Link Here
1220	state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;	1272	state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1221	break;	1273	break;
1222	case NV_ARCH_10:	1274	case NV_ARCH_10:
1223	case NV_ARCH_20:	1275	case NV_ARCH_20:
1224	nv10UpdateArbitrationSettings(VClk,	1276	if((chip->Chipset == NV_CHIP_IGEFORCE2) \|\|
		1277	(chip->Chipset == NV_CHIP_0x01F0))
		1278	{
		1279	nForceUpdateArbitrationSettings(VClk,
		1280	pixelDepth * 8,
		1281	&(state->arbitration0),
		1282	&(state->arbitration1),
		1283	chip);
		1284	} else {
		1285	nv10UpdateArbitrationSettings(VClk,
1225	pixelDepth * 8,	1286	pixelDepth * 8,
1226	&(state->arbitration0),	1287	&(state->arbitration0),
1227	&(state->arbitration1),	1288	&(state->arbitration1),
1228	chip);	1289	chip);
1229	state->cursor0 = 0x00;	1290	}
1230	state->cursor1 = 0xFC;	1291	state->cursor0 = 0x80 \| (chip->CursorStart >> 17);
1231	state->cursor2 = 0x00000000;	1292	state->cursor1 = (chip->CursorStart >> 11) << 2;
		1293	state->cursor2 = chip->CursorStart >> 24;
1232	state->pllsel = 0x10000700;	1294	state->pllsel = 0x10000700;
1233	state->config = chip->PFB[0x00000200/4];	1295	state->config = chip->PFB[0x00000200/4];
1234	state->general = bpp == 16 ? 0x00101100 : 0x00100100;	1296	state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1235	state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;	1297	state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1236	break;	1298	break;
1237	}	1299	}
		1300
		1301	/* Paul Richards: below if block borks things in kernel for some reason */
		1302	/* if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
		1303	state->general \|= 0x00000030; */
		1304
1238	state->vpll = (p << 16) \| (n << 8) \| m;	1305	state->vpll = (p << 16) \| (n << 8) \| m;
1239	state->screen = ((hTotal & 0x040) >> 2)
1240	\| ((vDisplay & 0x400) >> 7)
1241	\| ((vStart & 0x400) >> 8)
1242	\| ((vDisplay & 0x400) >> 9)
1243	\| ((vTotal & 0x400) >> 10);
1244	state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;	1306	state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1245	state->horiz = hTotal < 260 ? 0x00 : 0x01;
1246	state->pixel = pixelDepth > 2 ? 3 : pixelDepth;	1307	state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1247	state->offset0 =	1308	state->offset0 =
1248	state->offset1 =	1309	state->offset1 =
Lines 1286-1292 Link Here
1286	chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);	1347	chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
1287	break;	1348	break;
1288	case NV_ARCH_10:	1349	case NV_ARCH_10:
1289	case NV_ARCH_20:	1350	case NV_ARCH_20:
1290	/*	1351	/*
1291	* Initialize state for the RivaTriangle3D05 routines.	1352	* Initialize state for the RivaTriangle3D05 routines.
1292	*/	1353	*/
Lines 1395-1401 Link Here
1395	chip->PGRAPH[0x0000067C/4] = state->pitch3;	1456	chip->PGRAPH[0x0000067C/4] = state->pitch3;
1396	break;	1457	break;
1397	case NV_ARCH_10:	1458	case NV_ARCH_10:
1398	case NV_ARCH_20:	1459	case NV_ARCH_20:
		1460	if(chip->twoHeads) {
		1461	VGA_WR08(chip->PCIO, 0x03D4, 0x44);
		1462	VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
		1463	chip->LockUnlock(chip, 0);
		1464	}
		1465
1399	LOAD_FIXED_STATE(nv10,PFIFO);	1466	LOAD_FIXED_STATE(nv10,PFIFO);
1400	LOAD_FIXED_STATE(nv10,PRAMIN);	1467	LOAD_FIXED_STATE(nv10,PRAMIN);
1401	LOAD_FIXED_STATE(nv10,PGRAPH);	1468	LOAD_FIXED_STATE(nv10,PGRAPH);
Lines 1425-1463 Link Here
1425	break;	1492	break;
1426	}	1493	}
1427		1494
1428	if (chip->Architecture == NV_ARCH_10) {	1495	if(chip->Architecture == NV_ARCH_10) {
1429	chip->PGRAPH[0x00000640/4] = state->offset0;	1496	chip->PGRAPH[0x00000640/4] = state->offset0;
1430	chip->PGRAPH[0x00000644/4] = state->offset1;	1497	chip->PGRAPH[0x00000644/4] = state->offset1;
1431	chip->PGRAPH[0x00000648/4] = state->offset2;	1498	chip->PGRAPH[0x00000648/4] = state->offset2;
1432	chip->PGRAPH[0x0000064C/4] = state->offset3;	1499	chip->PGRAPH[0x0000064C/4] = state->offset3;
1433	chip->PGRAPH[0x00000670/4] = state->pitch0;	1500	chip->PGRAPH[0x00000670/4] = state->pitch0;
1434	chip->PGRAPH[0x00000674/4] = state->pitch1;	1501	chip->PGRAPH[0x00000674/4] = state->pitch1;
1435	chip->PGRAPH[0x00000678/4] = state->pitch2;	1502	chip->PGRAPH[0x00000678/4] = state->pitch2;
1436	chip->PGRAPH[0x0000067C/4] = state->pitch3;	1503	chip->PGRAPH[0x0000067C/4] = state->pitch3;
1437	chip->PGRAPH[0x00000680/4] = state->pitch3;	1504	chip->PGRAPH[0x00000680/4] = state->pitch3;
1438	} else {	1505	} else {
1439	chip->PGRAPH[0x00000820/4] = state->offset0;	1506	chip->PGRAPH[0x00000820/4] = state->offset0;
1440	chip->PGRAPH[0x00000824/4] = state->offset1;	1507	chip->PGRAPH[0x00000824/4] = state->offset1;
1441	chip->PGRAPH[0x00000828/4] = state->offset2;	1508	chip->PGRAPH[0x00000828/4] = state->offset2;
1442	chip->PGRAPH[0x0000082C/4] = state->offset3;	1509	chip->PGRAPH[0x0000082C/4] = state->offset3;
1443	chip->PGRAPH[0x00000850/4] = state->pitch0;	1510	chip->PGRAPH[0x00000850/4] = state->pitch0;
1444	chip->PGRAPH[0x00000854/4] = state->pitch1;	1511	chip->PGRAPH[0x00000854/4] = state->pitch1;
1445	chip->PGRAPH[0x00000858/4] = state->pitch2;	1512	chip->PGRAPH[0x00000858/4] = state->pitch2;
1446	chip->PGRAPH[0x0000085C/4] = state->pitch3;	1513	chip->PGRAPH[0x0000085C/4] = state->pitch3;
1447	chip->PGRAPH[0x00000860/4] = state->pitch3;	1514	chip->PGRAPH[0x00000860/4] = state->pitch3;
1448	chip->PGRAPH[0x00000864/4] = state->pitch3;	1515	chip->PGRAPH[0x00000864/4] = state->pitch3;
1449	chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];	1516	chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
1450	chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];	1517	chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
1451	}	1518	}
1452		1519	if(chip->twoHeads) {
1453	chip->PFB[0x00000240/4] = 0;	1520	chip->PCRTC0[0x00000860/4] = state->head;
1454	chip->PFB[0x00000244/4] = 0;	1521	chip->PCRTC0[0x00002860/4] = state->head2;
1455	chip->PFB[0x00000248/4] = 0;	1522	}
1456	chip->PFB[0x0000024C/4] = 0;	1523	chip->PRAMDAC[0x00000404/4] \|= (1 << 25);
1457	chip->PFB[0x00000250/4] = 0;	1524
1458	chip->PFB[0x00000244/4] = 0;	1525	chip->PMC[0x00008704/4] = 1;
1459	chip->PFB[0x00000248/4] = 0;	1526	chip->PMC[0x00008140/4] = 0;
1460	chip->PFB[0x0000024C/4] = 0;	1527	chip->PMC[0x00008920/4] = 0;
		1528	chip->PMC[0x00008924/4] = 0;
		1529	chip->PMC[0x00008908/4] = 0x01ffffff;
		1530	chip->PMC[0x0000890C/4] = 0x01ffffff;
		1531	chip->PMC[0x00001588/4] = 0;
		1532
		1533	chip->PFB[0x00000240/4] = 0;
		1534	chip->PFB[0x00000244/4] = 0;
		1535	chip->PFB[0x00000248/4] = 0;
		1536	chip->PFB[0x0000024C/4] = 0;
		1537	chip->PFB[0x00000250/4] = 0;
		1538	chip->PFB[0x00000254/4] = 0;
		1539	chip->PFB[0x00000258/4] = 0;
		1540	chip->PFB[0x0000025C/4] = 0;
1461		1541
1462	chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];	1542	chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4];
1463	chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];	1543	chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4];
Lines 1533-1547 Link Here
1533	for (i = 0; i < 4; i++)	1613	for (i = 0; i < 4; i++)
1534	chip->PGRAPH[0x00000F54/4] = 0x00000000;	1614	chip->PGRAPH[0x00000F54/4] = 0x00000000;
1535		1615
1536	if (chip->flatPanel) {	1616	chip->PCRTC[0x00000810/4] = state->cursorConfig;
1537	VGA_WR08(chip->PCIO, 0x3d4, 0x53);	1617
1538	VGA_WR08(chip->PCIO, 0x3d5, 0);	1618	if(chip->flatPanel) {
1539	VGA_WR08(chip->PCIO, 0x3d4, 0x54);	1619	if((chip->Chipset & 0x0ff0) == 0x0110) {
1540	VGA_WR08(chip->PCIO, 0x3d5, 0);	1620	chip->PRAMDAC[0x0528/4] = state->dither;
1541	VGA_WR08(chip->PCIO, 0x3d4, 0x21);	1621	} else
1542	VGA_WR08(chip->PCIO, 0x3d5, 0xfa);	1622	if((chip->Chipset & 0x0ff0) >= 0x0170) {
1543	}	1623	chip->PRAMDAC[0x083C/4] = state->dither;
1544	break;	1624	}
		1625
		1626	VGA_WR08(chip->PCIO, 0x03D4, 0x53);
		1627	VGA_WR08(chip->PCIO, 0x03D5, 0);
		1628	VGA_WR08(chip->PCIO, 0x03D4, 0x54);
		1629	VGA_WR08(chip->PCIO, 0x03D5, 0);
		1630	VGA_WR08(chip->PCIO, 0x03D4, 0x21);
		1631	VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
		1632	}
		1633
		1634	VGA_WR08(chip->PCIO, 0x03D4, 0x41);
		1635	VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1545	}	1636	}
1546	LOAD_FIXED_STATE(Riva,FIFO);	1637	LOAD_FIXED_STATE(Riva,FIFO);
1547	UpdateFifoState(chip);	1638	UpdateFifoState(chip);
Lines 1566-1590 Link Here
1566	VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);	1657	VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1567	VGA_WR08(chip->PCIO, 0x03D4, 0x31);	1658	VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1568	VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);	1659	VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1569	VGA_WR08(chip->PCIO, 0x03D4, 0x41);	1660	VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1570	VGA_WR08(chip->PCIO, 0x03D5, state->extra);	1661	VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1571		1662	VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1572	if (!chip->flatPanel) {	1663	VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1573	chip->PRAMDAC[0x00000508/4] = state->vpll;	1664
1574	chip->PRAMDAC[0x00000520/4] = state->vpll2;	1665	if(!chip->flatPanel) {
1575	chip->PRAMDAC[0x0000050C/4] = state->pllsel;	1666	chip->PRAMDAC0[0x00000508/4] = state->vpll;
1576	} else {	1667	chip->PRAMDAC0[0x0000050C/4] = state->pllsel;
1577	chip->PRAMDAC[0x00000848/4] = state->scale;	1668	if(chip->twoHeads)
1578	}	1669	chip->PRAMDAC0[0x00000520/4] = state->vpll2;
1579	chip->PRAMDAC[0x00000300/4] = state->cursor2;	1670	} else {
1580	chip->PRAMDAC[0x00000508/4] = state->vpll;	1671	chip->PRAMDAC[0x00000848/4] = state->scale;
1581	chip->PRAMDAC[0x0000050C/4] = state->pllsel;	1672	}
1582	chip->PRAMDAC[0x00000600/4] = state->general;	1673	chip->PRAMDAC[0x00000600/4] = state->general;
		1674
1583	/*	1675	/*
1584	* Turn off VBlank enable and reset.	1676	* Turn off VBlank enable and reset.
1585	*/	1677	*/
1586	*(chip->VBLANKENABLE) = 0;	1678	chip->PCRTC[0x00000140/4] = 0;
1587	*(chip->VBLANK) = chip->VBlankBit;	1679	chip->PCRTC[0x00000100/4] = chip->VBlankBit;
1588	/*	1680	/*
1589	* Set interrupt enable.	1681	* Set interrupt enable.
1590	*/	1682	*/
Lines 1627-1640 Link Here
1627	state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);	1719	state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1628	VGA_WR08(chip->PCIO, 0x03D4, 0x31);	1720	VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1629	state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);	1721	state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1630	VGA_WR08(chip->PCIO, 0x03D4, 0x41);	1722	VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1631	state->extra = VGA_RD08(chip->PCIO, 0x03D5);	1723	state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1632	state->cursor2 = chip->PRAMDAC[0x00000300/4];	1724	VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1633	state->vpll = chip->PRAMDAC[0x00000508/4];	1725	state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1634	state->vpll2 = chip->PRAMDAC[0x00000520/4];	1726	state->vpll = chip->PRAMDAC0[0x00000508/4];
1635	state->pllsel = chip->PRAMDAC[0x0000050C/4];	1727	state->vpll2 = chip->PRAMDAC0[0x00000520/4];
		1728	state->pllsel = chip->PRAMDAC0[0x0000050C/4];
1636	state->general = chip->PRAMDAC[0x00000600/4];	1729	state->general = chip->PRAMDAC[0x00000600/4];
1637	state->scale = chip->PRAMDAC[0x00000848/4];	1730	state->scale = chip->PRAMDAC[0x00000848/4];
1638	state->config = chip->PFB[0x00000200/4];	1731	state->config = chip->PFB[0x00000200/4];
1639	switch (chip->Architecture)	1732	switch (chip->Architecture)
1640	{	1733	{
Lines 1659-1665 Link Here
1659	state->pitch3 = chip->PGRAPH[0x0000067C/4];	1752	state->pitch3 = chip->PGRAPH[0x0000067C/4];
1660	break;	1753	break;
1661	case NV_ARCH_10:	1754	case NV_ARCH_10:
1662	case NV_ARCH_20:	1755	case NV_ARCH_20:
1663	state->offset0 = chip->PGRAPH[0x00000640/4];	1756	state->offset0 = chip->PGRAPH[0x00000640/4];
1664	state->offset1 = chip->PGRAPH[0x00000644/4];	1757	state->offset1 = chip->PGRAPH[0x00000644/4];
1665	state->offset2 = chip->PGRAPH[0x00000648/4];	1758	state->offset2 = chip->PGRAPH[0x00000648/4];
Lines 1668-1673 Link Here
1668	state->pitch1 = chip->PGRAPH[0x00000674/4];	1761	state->pitch1 = chip->PGRAPH[0x00000674/4];
1669	state->pitch2 = chip->PGRAPH[0x00000678/4];	1762	state->pitch2 = chip->PGRAPH[0x00000678/4];
1670	state->pitch3 = chip->PGRAPH[0x0000067C/4];	1763	state->pitch3 = chip->PGRAPH[0x0000067C/4];
		1764	if(chip->twoHeads) {
		1765	state->head = chip->PCRTC0[0x00000860/4];
		1766	state->head2 = chip->PCRTC0[0x00002860/4];
		1767	VGA_WR08(chip->PCIO, 0x03D4, 0x44);
		1768	state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
		1769	}
		1770	VGA_WR08(chip->PCIO, 0x03D4, 0x41);
		1771	state->extra = VGA_RD08(chip->PCIO, 0x03D5);
		1772	state->cursorConfig = chip->PCRTC[0x00000810/4];
		1773
		1774	if((chip->Chipset & 0x0ff0) == 0x0110) {
		1775	state->dither = chip->PRAMDAC[0x0528/4];
		1776	} else
		1777	if((chip->Chipset & 0x0ff0) >= 0x0170) {
		1778	state->dither = chip->PRAMDAC[0x083C/4];
		1779	}
1671	break;	1780	break;
1672	}	1781	}
1673	}	1782	}
Lines 1677-1682 Link Here
1677	unsigned start	1786	unsigned start
1678	)	1787	)
1679	{	1788	{
		1789	chip->PCRTC[0x800/4] = start;
		1790	}
		1791
		1792	static void SetStartAddress3
		1793	(
		1794	RIVA_HW_INST *chip,
		1795	unsigned start
		1796	)
		1797	{
1680	int offset = start >> 2;	1798	int offset = start >> 2;
1681	int pan = (start & 3) << 1;	1799	int pan = (start & 3) << 1;
1682	unsigned char tmp;	1800	unsigned char tmp;
Lines 1857-1867 Link Here
1857	break;	1975	break;
1858	}	1976	}
1859	}	1977	}
1860	chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500;	1978	chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
1861	chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);	1979	chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
1862	chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
1863	chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]);
1864	chip->VBLANK = &(chip->PGRAPH[0x0100/4]);
1865	chip->VBlankBit = 0x00000100;	1980	chip->VBlankBit = 0x00000100;
1866	chip->MaxVClockFreqKHz = 256000;	1981	chip->MaxVClockFreqKHz = 256000;
1867	/*	1982	/*
Lines 1872-1878 Link Here
1872	chip->CalcStateExt = CalcStateExt;	1987	chip->CalcStateExt = CalcStateExt;
1873	chip->LoadStateExt = LoadStateExt;	1988	chip->LoadStateExt = LoadStateExt;
1874	chip->UnloadStateExt = UnloadStateExt;	1989	chip->UnloadStateExt = UnloadStateExt;
1875	chip->SetStartAddress = SetStartAddress;	1990	chip->SetStartAddress = SetStartAddress3;
1876	chip->SetSurfaces2D = nv3SetSurfaces2D;	1991	chip->SetSurfaces2D = nv3SetSurfaces2D;
1877	chip->SetSurfaces3D = nv3SetSurfaces3D;	1992	chip->SetSurfaces3D = nv3SetSurfaces3D;
1878	chip->LockUnlock = nv3LockUnlock;	1993	chip->LockUnlock = nv3LockUnlock;
Lines 1920-1928 Link Here
1920	}	2035	}
1921	chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;	2036	chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
1922	chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);	2037	chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
1923	chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
1924	chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);
1925	chip->VBLANK = &(chip->PCRTC[0x0100/4]);
1926	chip->VBlankBit = 0x00000001;	2038	chip->VBlankBit = 0x00000001;
1927	chip->MaxVClockFreqKHz = 350000;	2039	chip->MaxVClockFreqKHz = 350000;
1928	/*	2040	/*
Lines 1940-1980 Link Here
1940	}	2052	}
1941	static void nv10GetConfig	2053	static void nv10GetConfig
1942	(	2054	(
1943	RIVA_HW_INST *chip	2055	RIVA_HW_INST *chip,
		2056	unsigned int chipset
1944	)	2057	)
1945	{	2058	{
1946	#if defined(__BIG_ENDIAN)	2059	struct pci_dev* dev;
1947	chip->PMC[0x00000004/4] = 0x01000001;	2060	int amt;
		2061
		2062	#ifdef __BIG_ENDIAN
		2063	/* turn on big endian register access */
		2064	if(!(chip->PMC[0x00000004/4] & 0x01000001))
		2065	chip->PMC[0x00000004/4] = 0x01000001;
1948	#endif	2066	#endif
		2067
1949	/*	2068	/*
1950	* Fill in chip configuration.	2069	* Fill in chip configuration.
1951	*/	2070	*/
1952	switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF)	2071	if(chipset == NV_CHIP_IGEFORCE2) {
1953	{	2072	dev = pci_find_slot(0, 1);
1954	case 0x02:	2073	pci_read_config_dword(dev, 0x7C, &amt);
1955	chip->RamAmountKBytes = 1024 * 2;	2074	chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
1956	break;	2075	} else if(chipset == NV_CHIP_0x01F0) {
1957	case 0x04:	2076	dev = pci_find_slot(0, 1);
1958	chip->RamAmountKBytes = 1024 * 4;	2077	pci_read_config_dword(dev, 0x84, &amt);
1959	break;	2078	chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
1960	case 0x08:	2079	} else {
1961	chip->RamAmountKBytes = 1024 * 8;	2080	switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF)
1962	break;	2081	{
1963	case 0x10:	2082	case 0x02:
1964	chip->RamAmountKBytes = 1024 * 16;	2083	chip->RamAmountKBytes = 1024 * 2;
1965	break;	2084	break;
1966	case 0x20:	2085	case 0x04:
1967	chip->RamAmountKBytes = 1024 * 32;	2086	chip->RamAmountKBytes = 1024 * 4;
1968	break;	2087	break;
1969	case 0x40:	2088	case 0x08:
1970	chip->RamAmountKBytes = 1024 * 64;	2089	chip->RamAmountKBytes = 1024 * 8;
1971	break;	2090	break;
1972	case 0x80:	2091	case 0x10:
1973	chip->RamAmountKBytes = 1024 * 128;	2092	chip->RamAmountKBytes = 1024 * 16;
1974	break;	2093	break;
1975	default:	2094	case 0x20:
1976	chip->RamAmountKBytes = 1024 * 16;	2095	chip->RamAmountKBytes = 1024 * 32;
1977	break;	2096	break;
		2097	case 0x40:
		2098	chip->RamAmountKBytes = 1024 * 64;
		2099	break;
		2100	case 0x80:
		2101	chip->RamAmountKBytes = 1024 * 128;
		2102	break;
		2103	default:
		2104	chip->RamAmountKBytes = 1024 * 16;
		2105	break;
		2106	}
1978	}	2107	}
1979	switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)	2108	switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
1980	{	2109	{
Lines 1985-1995 Link Here
1985	chip->RamBandwidthKBytesPerSec = 1000000;	2114	chip->RamBandwidthKBytesPerSec = 1000000;
1986	break;	2115	break;
1987	}	2116	}
1988	chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;	2117	chip->CrystalFreqKHz = (chip->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 :
1989	chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);	2118	13500;
1990	chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);	2119
1991	chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);	2120	switch (chipset & 0x0ff0) {
1992	chip->VBLANK = &(chip->PCRTC[0x0100/4]);	2121	case 0x0170:
		2122	case 0x0180:
		2123	case 0x01F0:
		2124	case 0x0250:
		2125	case 0x0280:
		2126	case 0x0300:
		2127	case 0x0310:
		2128	case 0x0320:
		2129	case 0x0330:
		2130	case 0x0340:
		2131	if(chip->PEXTDEV[0x0000/4] & (1 << 22))
		2132	chip->CrystalFreqKHz = 27000;
		2133	break;
		2134	default:
		2135	break;
		2136	}
		2137
		2138	chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
		2139	chip->CURSOR = NULL; /* can't set this here */
1993	chip->VBlankBit = 0x00000001;	2140	chip->VBlankBit = 0x00000001;
1994	chip->MaxVClockFreqKHz = 350000;	2141	chip->MaxVClockFreqKHz = 350000;
1995	/*	2142	/*
Lines 2003-2013 Link Here
2003	chip->SetStartAddress = SetStartAddress;	2150	chip->SetStartAddress = SetStartAddress;
2004	chip->SetSurfaces2D = nv10SetSurfaces2D;	2151	chip->SetSurfaces2D = nv10SetSurfaces2D;
2005	chip->SetSurfaces3D = nv10SetSurfaces3D;	2152	chip->SetSurfaces3D = nv10SetSurfaces3D;
2006	chip->LockUnlock = nv10LockUnlock;	2153	chip->LockUnlock = nv4LockUnlock;
		2154
		2155	switch(chipset & 0x0ff0) {
		2156	case 0x0110:
		2157	case 0x0170:
		2158	case 0x0180:
		2159	case 0x01F0:
		2160	case 0x0250:
		2161	case 0x0280:
		2162	case 0x0300:
		2163	case 0x0310:
		2164	case 0x0320:
		2165	case 0x0330:
		2166	case 0x0340:
		2167	chip->twoHeads = TRUE;
		2168	break;
		2169	default:
		2170	chip->twoHeads = FALSE;
		2171	break;
		2172	}
2007	}	2173	}
2008	int RivaGetConfig	2174	int RivaGetConfig
2009	(	2175	(
2010	RIVA_HW_INST *chip	2176	RIVA_HW_INST *chip,
		2177	unsigned int chipset
2011	)	2178	)
2012	{	2179	{
2013	/*	2180	/*
Lines 2026-2037 Link Here
2026	nv4GetConfig(chip);	2193	nv4GetConfig(chip);
2027	break;	2194	break;
2028	case NV_ARCH_10:	2195	case NV_ARCH_10:
2029	case NV_ARCH_20:	2196	case NV_ARCH_20:
2030	nv10GetConfig(chip);	2197	nv10GetConfig(chip, chipset);
2031	break;	2198	break;
2032	default:	2199	default:
2033	return (-1);	2200	return (-1);
2034	}	2201	}
		2202	chip->Chipset = chipset;
2035	/*	2203	/*
2036	* Fill in FIFO pointers.	2204	* Fill in FIFO pointers.
2037	*/	2205	*/




 * GPL licensing note -- nVidia is allowing a liberal interpretation of
 * the documentation restriction above, to merely say that this nVidia's
 * copyright and disclaimer should be included with all code derived
 * from this source.  -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 
 */

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
#ifndef __RIVA_HW_H__
#define __RIVA_HW_H__
#define RIVA_SW_VERSION 0x00010003

#ifndef Bool
typedef int Bool;
#endif

#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif

/*
 * Typedefs to force certain sized values.
 */

#else
    U016 FifoFree;
    U016 Nop;
#endif
    U032 reserved01[0x0BB];
    U032 Rop3;
} RivaRop;

#else
    U016 FifoFree;
    U016 Nop;
#endif
    U032 reserved01[0x0BC];
    U032 TextureOffset;
    U032 TextureFormat;

#else
    U016 FifoFree;
    U016 Nop;
#endif
    U032 reserved01[0x0BB];
    U032 ColorKey;
    U032 TextureOffset;

#else
    U016 FifoFree;
    U016 Nop[1];
#endif
    U032 reserved01[0x0BC];
    U032 Color;             /* source color               0304-0307*/
    U032 Reserved02[0x03e];

*                                                                           *
\***************************************************************************/

#define FP_ENABLE  1
#define FP_DITHER  2

struct _riva_hw_inst;
struct _riva_hw_state;
/*

     */
    U032 Architecture;
    U032 Version;
    U032 Chipset;
    U032 CrystalFreqKHz;
    U032 RamAmountKBytes;
    U032 MaxVClockFreqKHz;

    U032 VBlankBit;
    U032 FifoFreeCount;
    U032 FifoEmptyCount;
    U032 CursorStart;
    U032 flatPanel;
    Bool twoHeads;
    /*
     * Non-FIFO registers.
     */
    volatile U032 *PCRTC0;
    volatile U032 *PCRTC;
    volatile U032 *PRAMDAC0;
    volatile U032 *PFB;
    volatile U032 *PFIFO;
    volatile U032 *PGRAPH;

    volatile U032 *PRAMIN;
    volatile U032 *FIFO;
    volatile U032 *CURSOR;
    volatile U008 *PCIO0;
    volatile U032 *VBLANKENABLE;
    volatile U032 *VBLANK;
    volatile U008 *PCIO;
    volatile U008 *PVIO;
    volatile U008 *PDIO0;
    volatile U008 *PDIO;
    volatile U032 *PRAMDAC;
    /*
     * Common chip functions.
     */
    int  (*Busy)(struct _riva_hw_inst *);
    void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
    void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
    void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
    void (*SetStartAddress)(struct _riva_hw_inst *,U032);

    U032 bpp;
    U032 width;
    U032 height;
    U032 interlace;
    U032 repaint0;
    U032 repaint1;
    U032 screen;
    U032 scale;
    U032 dither;
    U032 extra;
    U032 pixel;
    U032 horiz;

    U032 vpll2;
    U032 pllsel;
    U032 general;
    U032 crtcOwner;
    U032 head; 
    U032 head2; 
    U032 config;
    U032 cursorConfig;	
    U032 cursor0;
    U032 cursor1;
    U032 cursor2;

/*
 * External routines.
 */
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
/*
 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
 */

/*
 * The mb()'s work around some lockup problems I experienced with some
 * GeForceII MX cards, neither I nor Mark Vojkovich knows for sure what's
 * going on there. --BenH
 */ 
#define RIVA_FIFO_FREE(hwinst,hwptr,cnt)                            \
{                                                                   \
    while ((hwinst).FifoFreeCount < (cnt)) {                        \
    	mb();                                              \
    	mb();	                                            \
        (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2;     \
    } \
    (hwinst).FifoFreeCount -= (cnt);                                \
}
#endif /* __RIVA_HW_H__ */


Lines 41-50 Link Here

(-)linux-2.4.22/drivers/video/riva/riva_tbl.h (-13 / +35 lines)
41	* GPL licensing note -- nVidia is allowing a liberal interpretation of	41	* GPL licensing note -- nVidia is allowing a liberal interpretation of
42	* the documentation restriction above, to merely say that this nVidia's	42	* the documentation restriction above, to merely say that this nVidia's
43	* copyright and disclaimer should be included with all code derived	43	* copyright and disclaimer should be included with all code derived
44	* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99	44	* from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99
45	*/	45	*/
46		46
47	/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.5 2000/02/08 17:19:12 dawes Exp $ */	47	/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */
		48
		49
48	/*	50	/*
49	* RIVA Fixed Functionality Init Tables.	51	* RIVA Fixed Functionality Init Tables.
50	*/	52	*/
Lines 69-74 Link Here
69	{0x00001800, 0x80000010},	71	{0x00001800, 0x80000010},
70	{0x00002000, 0x80000011},	72	{0x00002000, 0x80000011},
71	{0x00002800, 0x80000012},	73	{0x00002800, 0x80000012},
		74	{0x00003000, 0x80000016},
72	{0x00003800, 0x80000013}	75	{0x00003800, 0x80000013}
73	};	76	};
74	static unsigned nv3TablePFIFO[][2] =	77	static unsigned nv3TablePFIFO[][2] =
Lines 174-179 Link Here
174	{0x00000249, 0x00CC0346},	177	{0x00000249, 0x00CC0346},
175	{0x0000024C, 0x80000013},	178	{0x0000024C, 0x80000013},
176	{0x0000024D, 0x00D70347},	179	{0x0000024D, 0x00D70347},
		180	{0x00000258, 0x80000016},
		181	{0x00000259, 0x00CA034C},
177	{0x00000D05, 0x00000000},	182	{0x00000D05, 0x00000000},
178	{0x00000D06, 0x00000000},	183	{0x00000D06, 0x00000000},
179	{0x00000D07, 0x00000000},	184	{0x00000D07, 0x00000000},
Lines 210-216 Link Here
210	{0x00000D2C, 0x10830200},	215	{0x00000D2C, 0x10830200},
211	{0x00000D2D, 0x00000000},	216	{0x00000D2D, 0x00000000},
212	{0x00000D2E, 0x00000000},	217	{0x00000D2E, 0x00000000},
213	{0x00000D2F, 0x00000000}	218	{0x00000D2F, 0x00000000},
		219	{0x00000D31, 0x00000000},
		220	{0x00000D32, 0x00000000},
		221	{0x00000D33, 0x00000000}
214	};	222	};
215	static unsigned nv3TablePRAMIN_8BPP[][2] =	223	static unsigned nv3TablePRAMIN_8BPP[][2] =
216	{	224	{
Lines 222-228 Link Here
222	{0x00000D10, 0x10118203},	230	{0x00000D10, 0x10118203},
223	{0x00000D14, 0x10110203},	231	{0x00000D14, 0x10110203},
224	{0x00000D18, 0x10110203},	232	{0x00000D18, 0x10110203},
225	{0x00000D1C, 0x10419208}	233	{0x00000D1C, 0x10419208},
		234	{0x00000D30, 0x10118203}
226	};	235	};
227	static unsigned nv3TablePRAMIN_15BPP[][2] =	236	static unsigned nv3TablePRAMIN_15BPP[][2] =
228	{	237	{
Lines 234-240 Link Here
234	{0x00000D10, 0x10118200},	243	{0x00000D10, 0x10118200},
235	{0x00000D14, 0x10110200},	244	{0x00000D14, 0x10110200},
236	{0x00000D18, 0x10110200},	245	{0x00000D18, 0x10110200},
237	{0x00000D1C, 0x10419208}	246	{0x00000D1C, 0x10419208},
		247	{0x00000D30, 0x10118200}
238	};	248	};
239	static unsigned nv3TablePRAMIN_32BPP[][2] =	249	static unsigned nv3TablePRAMIN_32BPP[][2] =
240	{	250	{
Lines 246-252 Link Here
246	{0x00000D10, 0x10118201},	256	{0x00000D10, 0x10118201},
247	{0x00000D14, 0x10110201},	257	{0x00000D14, 0x10110201},
248	{0x00000D18, 0x10110201},	258	{0x00000D18, 0x10110201},
249	{0x00000D1C, 0x10419208}	259	{0x00000D1C, 0x10419208},
		260	{0x00000D30, 0x10118201}
250	};	261	};
251	static unsigned nv4TableFIFO[][2] =	262	static unsigned nv4TableFIFO[][2] =
252	{	263	{
Lines 370-375 Link Here
370	{0x00000009, 0x80011149},	381	{0x00000009, 0x80011149},
371	{0x0000000A, 0x80000015},	382	{0x0000000A, 0x80000015},
372	{0x0000000B, 0x8001114A},	383	{0x0000000B, 0x8001114A},
		384	{0x0000000C, 0x80000016},
		385	{0x0000000D, 0x8001114F},
373	{0x00000020, 0x80000000},	386	{0x00000020, 0x80000000},
374	{0x00000021, 0x80011142},	387	{0x00000021, 0x80011142},
375	{0x00000022, 0x80000001},	388	{0x00000022, 0x80000001},
Lines 437-443 Link Here
437	{0x00000537, 0x00000000},	450	{0x00000537, 0x00000000},
438	{0x00000538, 0x0000005B},	451	{0x00000538, 0x0000005B},
439	{0x0000053A, 0x11401140},	452	{0x0000053A, 0x11401140},
440	{0x0000053B, 0x00000000}	453	{0x0000053B, 0x00000000},
		454	{0x0000053C, 0x0300A01C},
		455	{0x0000053E, 0x11401140},
		456	{0x0000053F, 0x00000000}
441	};	457	};
442	static unsigned nv4TablePRAMIN_8BPP[][2] =	458	static unsigned nv4TablePRAMIN_8BPP[][2] =
443	{	459	{
Lines 452-458 Link Here
452	{0x0000052D, 0x00000302},	468	{0x0000052D, 0x00000302},
453	{0x0000052E, 0x00000302},	469	{0x0000052E, 0x00000302},
454	{0x00000535, 0x00000000},	470	{0x00000535, 0x00000000},
455	{0x00000539, 0x00000000}	471	{0x00000539, 0x00000000},
		472	{0x0000053D, 0x00000302}
456	};	473	};
457	static unsigned nv4TablePRAMIN_15BPP[][2] =	474	static unsigned nv4TablePRAMIN_15BPP[][2] =
458	{	475	{
Lines 467-473 Link Here
467	{0x0000052D, 0x00000902},	484	{0x0000052D, 0x00000902},
468	{0x0000052E, 0x00000902},	485	{0x0000052E, 0x00000902},
469	{0x00000535, 0x00000702},	486	{0x00000535, 0x00000702},
470	{0x00000539, 0x00000702}	487	{0x00000539, 0x00000702},
		488	{0x0000053D, 0x00000902}
471	};	489	};
472	static unsigned nv4TablePRAMIN_16BPP[][2] =	490	static unsigned nv4TablePRAMIN_16BPP[][2] =
473	{	491	{
Lines 482-488 Link Here
482	{0x0000052D, 0x00000C02},	500	{0x0000052D, 0x00000C02},
483	{0x0000052E, 0x00000C02},	501	{0x0000052E, 0x00000C02},
484	{0x00000535, 0x00000702},	502	{0x00000535, 0x00000702},
485	{0x00000539, 0x00000702}	503	{0x00000539, 0x00000702},
		504	{0x0000053D, 0x00000C02}
486	};	505	};
487	static unsigned nv4TablePRAMIN_32BPP[][2] =	506	static unsigned nv4TablePRAMIN_32BPP[][2] =
488	{	507	{
Lines 497-503 Link Here
497	{0x0000052D, 0x00000E02},	516	{0x0000052D, 0x00000E02},
498	{0x0000052E, 0x00000E02},	517	{0x0000052E, 0x00000E02},
499	{0x00000535, 0x00000E02},	518	{0x00000535, 0x00000E02},
500	{0x00000539, 0x00000E02}	519	{0x00000539, 0x00000E02},
		520	{0x0000053D, 0x00000E02}
501	};	521	};
502	static unsigned nv10TableFIFO[][2] =	522	static unsigned nv10TableFIFO[][2] =
503	{	523	{
Lines 810-815 Link Here
810	{0x00000009, 0x80011149},	830	{0x00000009, 0x80011149},
811	{0x0000000A, 0x80000015},	831	{0x0000000A, 0x80000015},
812	{0x0000000B, 0x8001114A},	832	{0x0000000B, 0x8001114A},
		833	{0x0000000C, 0x80000016},
		834	{0x0000000D, 0x80011150},
813	{0x00000020, 0x80000000},	835	{0x00000020, 0x80000000},
814	{0x00000021, 0x80011142},	836	{0x00000021, 0x80011142},
815	{0x00000022, 0x80000001},	837	{0x00000022, 0x80000001},
Lines 831-837 Link Here
831	{0x00000502, 0x00000002},	853	{0x00000502, 0x00000002},
832	{0x00000503, 0x00000002},	854	{0x00000503, 0x00000002},
833	#ifdef __BIG_ENDIAN	855	#ifdef __BIG_ENDIAN
834	{0x00000508, 0x01088043},	856	{0x00000508, 0x01088043},
835	#else	857	#else
836	{0x00000508, 0x01008043},	858	{0x00000508, 0x01008043},
837	#endif	859	#endif
Lines 946-952 Link Here
946	{0x0000052E, 0x00000902},	968	{0x0000052E, 0x00000902},
947	{0x00000535, 0x00000902},	969	{0x00000535, 0x00000902},
948	{0x00000539, 0x00000902},	970	{0x00000539, 0x00000902},
949	{0x0000053D, 0x00000902},	971	{0x0000053D, 0x00000902},
950	{0x00000541, 0x00000902}	972	{0x00000541, 0x00000902}
951	};	973	};
952	static unsigned nv10TablePRAMIN_16BPP[][2] =	974	static unsigned nv10TablePRAMIN_16BPP[][2] =

Lines 92-97 Link Here

(-)linux-2.4.22/drivers/video/riva/rivafb.h (+6 lines)
92	#ifdef CONFIG_MTRR	92	#ifdef CONFIG_MTRR
93	struct { int vram; int vram_valid; } mtrr;	93	struct { int vram; int vram_valid; } mtrr;
94	#endif	94	#endif
		95	unsigned int Chipset;
		96	int forceCRTC;
		97	Bool SecondCRTC;
		98	int FlatPanel;
95	};	99	};
96		100
		101	void riva_common_setup(struct rivafb_info*);
		102
97	#endif /* __RIVAFB_H */	103	#endif /* __RIVAFB_H */

Lines 88-93 Link Here

(-)linux-2.4.22/fs/buffer.c (-5 / +37 lines)
88	static int osync_buffers_list(struct list_head *);	88	static int osync_buffers_list(struct list_head *);
89	static void __refile_buffer(struct buffer_head *);	89	static void __refile_buffer(struct buffer_head *);
90		90
		91	/*
		92	* A global sysctl-controlled flag which puts the machine into "laptop mode"
		93	*/
		94	int laptop_mode;
		95
		96	static DECLARE_WAIT_QUEUE_HEAD(kupdate_wait);
		97
91	/* This is used by some architectures to estimate available memory. */	98	/* This is used by some architectures to estimate available memory. */
92	atomic_t buffermem_pages = ATOMIC_INIT(0);	99	atomic_t buffermem_pages = ATOMIC_INIT(0);
93		100
Lines 1016-1022 Link Here
1016	dirty *= 100;	1023	dirty *= 100;
1017	dirty_limit = tot * bdf_prm.b_un.nfract_stop_bdflush;	1024	dirty_limit = tot * bdf_prm.b_un.nfract_stop_bdflush;
1018		1025
1019	if (dirty > dirty_limit)	1026	if (!laptop_mode && dirty > dirty_limit)
1020	return 0;	1027	return 0;
1021	return 1;	1028	return 1;
1022	}	1029	}
Lines 1066-1071 Link Here
1066	void mark_buffer_dirty(struct buffer_head *bh)	1073	void mark_buffer_dirty(struct buffer_head *bh)
1067	{	1074	{
1068	if (!atomic_set_buffer_dirty(bh)) {	1075	if (!atomic_set_buffer_dirty(bh)) {
		1076	if (block_dump)
		1077	printk("%s: dirtied buffer\n", current->comm);
1069	__mark_dirty(bh);	1078	__mark_dirty(bh);
1070	balance_dirty();	1079	balance_dirty();
1071	}	1080	}
Lines 1077-1082 Link Here
1077	}	1086	}
1078	EXPORT_SYMBOL(set_buffer_flushtime);	1087	EXPORT_SYMBOL(set_buffer_flushtime);
1079		1088
		1089	unsigned long get_buffer_flushtime(void)
		1090	{
		1091	return bdf_prm.b_un.age_buffer;
		1092	}
		1093	EXPORT_SYMBOL(get_buffer_flushtime);
		1094
		1095
1080	/*	1096	/*
1081	* A buffer may need to be moved from one buffer list to another	1097	* A buffer may need to be moved from one buffer list to another
1082	* (e.g. in case it is not shared any more). Handle this.	1098	* (e.g. in case it is not shared any more). Handle this.
Lines 2859-2864 Link Here
2859	wake_up_interruptible(&bdflush_wait);	2875	wake_up_interruptible(&bdflush_wait);
2860	}	2876	}
2861		2877
		2878	void wakeup_kupdate(void)
		2879	{
		2880	if (waitqueue_active(&kupdate_wait))
		2881	wake_up(&kupdate_wait);
		2882	}
		2883
2862	/*	2884	/*
2863	* Here we attempt to write back old buffers. We also try to flush inodes	2885	* Here we attempt to write back old buffers. We also try to flush inodes
2864	* and supers as well, since this function is essentially "update", and	2886	* and supers as well, since this function is essentially "update", and
Lines 2879-2885 Link Here
2879		2901
2880	spin_lock(&lru_list_lock);	2902	spin_lock(&lru_list_lock);
2881	bh = lru_list[BUF_DIRTY];	2903	bh = lru_list[BUF_DIRTY];
2882	if (!bh \|\| time_before(jiffies, bh->b_flushtime))	2904	if (!bh)
		2905	break;
		2906	if (time_before(jiffies, bh->b_flushtime) && !laptop_mode)
2883	break;	2907	break;
2884	if (write_some_buffers(NODEV))	2908	if (write_some_buffers(NODEV))
2885	continue;	2909	continue;
Lines 3027-3042 Link Here
3027	complete((struct completion *)startup);	3051	complete((struct completion *)startup);
3028		3052
3029	for (;;) {	3053	for (;;) {
		3054	DECLARE_WAITQUEUE(wait, tsk);
		3055
		3056	add_wait_queue(&kupdate_wait, &wait);
		3057
3030	/* update interval */	3058	/* update interval */
3031	interval = bdf_prm.b_un.interval;	3059	interval = bdf_prm.b_un.interval;
3032	if (interval) {	3060	if (interval) {
3033	tsk->state = TASK_INTERRUPTIBLE;	3061	tsk->state = TASK_INTERRUPTIBLE;
3034	schedule_timeout(interval);	3062	schedule_timeout(interval);
3035	} else {	3063	} else {
3036	stop_kupdate:
3037	tsk->state = TASK_STOPPED;	3064	tsk->state = TASK_STOPPED;
3038	schedule(); /* wait for SIGCONT */	3065	schedule(); /* wait for SIGCONT */
3039	}	3066	}
		3067	remove_wait_queue(&kupdate_wait, &wait);
3040	/* check for sigstop */	3068	/* check for sigstop */
3041	if (signal_pending(tsk)) {	3069	if (signal_pending(tsk)) {
3042	int stopped = 0;	3070	int stopped = 0;
Lines 3047-3059 Link Here
3047	}	3075	}
3048	recalc_sigpending(tsk);	3076	recalc_sigpending(tsk);
3049	spin_unlock_irq(&tsk->sigmask_lock);	3077	spin_unlock_irq(&tsk->sigmask_lock);
3050	if (stopped)	3078	if (stopped) {
3051	goto stop_kupdate;	3079	tsk->state = TASK_STOPPED;
		3080	schedule(); /* wait for SIGCONT */
		3081	}
3052	}	3082	}
3053	#ifdef DEBUG	3083	#ifdef DEBUG
3054	printk(KERN_DEBUG "kupdate() activated...\n");	3084	printk(KERN_DEBUG "kupdate() activated...\n");
3055	#endif	3085	#endif
3056	sync_old_buffers();	3086	sync_old_buffers();
		3087	if (laptop_mode)
		3088	fsync_dev(NODEV);
3057	run_task_queue(&tq_disk);	3089	run_task_queue(&tq_disk);
3058	}	3090	}
3059	}	3091	}

Lines 211-216 Link Here

(-)linux-2.4.22/fs/hfsplus/hfsplus_fs.h (+1 lines)
211	hfsplus_cat_key key;	211	hfsplus_cat_key key;
212	};	212	};
213		213
		214
214	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)	215	#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
215	typedef long sector_t;	216	typedef long sector_t;
216	#endif	217	#endif

Lines 56-62 Link Here

(-)linux-2.4.22/fs/jbd/transaction.c (-1 / +5 lines)
56	transaction->t_journal = journal;	56	transaction->t_journal = journal;
57	transaction->t_state = T_RUNNING;	57	transaction->t_state = T_RUNNING;
58	transaction->t_tid = journal->j_transaction_sequence++;	58	transaction->t_tid = journal->j_transaction_sequence++;
59	transaction->t_expires = jiffies + journal->j_commit_interval;	59	/*
		60	* have to do it here, otherwise changed age_buffers since boot
		61	* wont have any effect
		62	*/
		63	transaction->t_expires = jiffies + get_buffer_flushtime();
60	INIT_LIST_HEAD(&transaction->t_jcb);	64	INIT_LIST_HEAD(&transaction->t_jcb);
61		65
62	/* Set up the commit timer for the new transaction. */	66	/* Set up the commit timer for the new transaction. */

Lines 763-769 Link Here

(-)linux-2.4.22/fs/namespace.c (-1 / +1 lines)
763	return -EPERM;	763	return -EPERM;
764	}	764	}
765		765
766	new_ns = kmalloc(sizeof(struct namespace *), GFP_KERNEL);	766	new_ns = kmalloc(sizeof(struct namespace), GFP_KERNEL);
767	if (!new_ns)	767	if (!new_ns)
768	goto out;	768	goto out;
769		769




extern void atomic_set_mask(unsigned long mask, unsigned long *addr);

#ifdef CONFIG_SMP
#define SMP_ISYNC	"\n\tisync\n"
#define SMP_EIEIO	"\n\teieio\n"
#else
#define SMP_ISYNC
#define SMP_EIEIO
#endif

/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.

	int t;

	__asm__ __volatile__(
	SMP_EIEIO
"1:	lwarx	%0,0,%2		# atomic_add_return\n\
	add	%0,%1,%0\n"
	PPC405_ERR77(0,%2)

	int t;

	__asm__ __volatile__(
	SMP_EIEIO
"1:	lwarx	%0,0,%2		# atomic_sub_return\n\
	subf	%0,%1,%0\n"
	PPC405_ERR77(0,%2)

	int t;

	__asm__ __volatile__(
	SMP_EIEIO
"1:	lwarx	%0,0,%1		# atomic_inc_return\n\
	addic	%0,%0,1\n"
	PPC405_ERR77(0,%1)

	int t;

	__asm__ __volatile__(
	SMP_EIEIO
"1:	lwarx	%0,0,%1		# atomic_dec_return\n\
	addic	%0,%0,-1\n"
	PPC405_ERR77(0,%1)

	int t;

	__asm__ __volatile__(
	SMP_EIEIO
"1:	lwarx	%0,0,%1		# atomic_dec_if_positive\n\
	addic.	%0,%0,-1\n\
	blt-	2f\n"

Lines 10-16 Link Here

(-)linux-2.4.22/include/asm-ppc/elf.h (-1 / +1 lines)
10		10
11	#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */	11	#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
12	#define ELF_NFPREG 33 /* includes fpscr */	12	#define ELF_NFPREG 33 /* includes fpscr */
13	#define ELF_NVRREG 33 /* includes vscr */	13	#define ELF_NVRREG 33 /* includes vscr & vrsave */
14		14
15	/*	15	/*
16	* These are used to set parameters in the core dumps.	16	* These are used to set parameters in the core dumps.

Lines 54-65 Link Here

(-)linux-2.4.22/include/asm-ppc/hardirq.h (+17 lines)
54	extern unsigned volatile long global_irq_lock;	54	extern unsigned volatile long global_irq_lock;
55	extern atomic_t global_irq_count;	55	extern atomic_t global_irq_count;
56		56
		57	#ifdef CONFIG_DEBUG_SPINLOCK
		58	extern int debug_long_irqlock;
		59	extern void print_backtrace(unsigned long *sp);
		60	#endif /* CONFIG_DEBUG_SPINLOCK */
		61
57	static inline void release_irqlock(int cpu)	62	static inline void release_irqlock(int cpu)
58	{	63	{
59	/* if we didn't own the irq lock, just ignore.. */	64	/* if we didn't own the irq lock, just ignore.. */
60	if (global_irq_holder == (unsigned char) cpu) {	65	if (global_irq_holder == (unsigned char) cpu) {
61	global_irq_holder = NO_PROC_ID;	66	global_irq_holder = NO_PROC_ID;
62	clear_bit(0,&global_irq_lock);	67	clear_bit(0,&global_irq_lock);
		68	#ifdef CONFIG_DEBUG_SPINLOCK
		69	if (debug_long_irqlock) {
		70	debug_long_irqlock = 0;
		71	printk("Release long irq lock\n");
		72	print_backtrace(NULL);
		73	}
		74	#endif /* CONFIG_DEBUG_SPINLOCK */
63	}	75	}
64	}	76	}
65		77
Lines 69-74 Link Here
69		81
70	++local_irq_count(cpu);	82	++local_irq_count(cpu);
71	atomic_inc(&global_irq_count);	83	atomic_inc(&global_irq_count);
		84	smp_mb__after_atomic_inc();
72	while (test_bit(0,&global_irq_lock)) {	85	while (test_bit(0,&global_irq_lock)) {
73	if (cpu == global_irq_holder) {	86	if (cpu == global_irq_holder) {
74	printk("uh oh, interrupt while we hold global irq lock! (CPU %d)\n", cpu);	87	printk("uh oh, interrupt while we hold global irq lock! (CPU %d)\n", cpu);
Lines 79-84 Link Here
79	}	92	}
80	if (loops-- == 0) {	93	if (loops-- == 0) {
81	printk("do_IRQ waiting for irq lock (holder=%d)\n", global_irq_holder);	94	printk("do_IRQ waiting for irq lock (holder=%d)\n", global_irq_holder);
		95	#ifdef CONFIG_DEBUG_SPINLOCK
		96	debug_long_irqlock = 1;
		97	#endif
82	#ifdef CONFIG_XMON	98	#ifdef CONFIG_XMON
83	xmon(0);	99	xmon(0);
84	#endif	100	#endif
Lines 88-93 Link Here
88		104
89	static inline void hardirq_exit(int cpu)	105	static inline void hardirq_exit(int cpu)
90	{	106	{
		107	smp_mb__after_atomic_dec();
91	atomic_dec(&global_irq_count);	108	atomic_dec(&global_irq_count);
92	--local_irq_count(cpu);	109	--local_irq_count(cpu);
93	}	110	}

Lines 28-34 Link Here

(-)linux-2.4.22/include/asm-ppc/highmem.h (-1 / +1 lines)
28	#include <asm/pgtable.h>	28	#include <asm/pgtable.h>
29		29
30	/* undef for production */	30	/* undef for production */
31	#define HIGHMEM_DEBUG 1	31	#define HIGHMEM_DEBUG 0
32		32
33	extern pte_t *kmap_pte;	33	extern pte_t *kmap_pte;
34	extern pgprot_t kmap_prot;	34	extern pgprot_t kmap_prot;




                                     ide_ioreg_t data_port,
                                     ide_ioreg_t ctrl_port,
                                     int *irq);
        int         (*reserved_hwifs)(void);
};

extern struct ide_machdep_calls ppc_ide_md;

#define IDE_ARCH_ACK_INTR 1
#endif

/*
 * How many IDE slots are "reserved" for bootable devices
 */
#define IDE_ARCH_RESERVED_HWIFS 1
static inline int ide_reserved_hwifs(void)
{
	if (ppc_ide_md.reserved_hwifs)
		return ppc_ide_md.reserved_hwifs();
	return 2;
}

#endif /* __KERNEL__ */

#endif /* __ASMPPC_IDE_H */

Lines 287-295 Link Here

(-)linux-2.4.22/include/asm-ppc/io.h (-8 / +14 lines)
287	/* Enforce in-order execution of data I/O.	287	/* Enforce in-order execution of data I/O.
288	* No distinction between read/write on PPC; use eieio for all three.	288	* No distinction between read/write on PPC; use eieio for all three.
289	*/	289	*/
290	#define iobarrier_rw() eieio()	290	#if 0
291	#define iobarrier_r() eieio()	291	#define iobarrier_rw() eieio()
292	#define iobarrier_w() eieio()	292	#define iobarrier_r() eieio()
		293	#define iobarrier_w() eieio()
		294	#endif
		295	extern inline void io_barrier(void)
		296	{
		297	__asm__ __volatile__ ("sync" : : : "memory");
		298	}
293		299
294	/*	300	/*
295	* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.	301	* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
Lines 311-317 Link Here
311		317
312	extern inline void out_8(volatile unsigned char *addr, int val)	318	extern inline void out_8(volatile unsigned char *addr, int val)
313	{	319	{
314	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));	320	__asm__ __volatile__("sync; stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
315	}	321	}
316		322
317	extern inline int in_le16(volatile unsigned short *addr)	323	extern inline int in_le16(volatile unsigned short *addr)
Lines 337-349 Link Here
337		343
338	extern inline void out_le16(volatile unsigned short *addr, int val)	344	extern inline void out_le16(volatile unsigned short *addr, int val)
339	{	345	{
340	__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :	346	__asm__ __volatile__("sync; sthbrx %1,0,%2; eieio" : "=m" (*addr) :
341	"r" (val), "r" (addr));	347	"r" (val), "r" (addr));
342	}	348	}
343		349
344	extern inline void out_be16(volatile unsigned short *addr, int val)	350	extern inline void out_be16(volatile unsigned short *addr, int val)
345	{	351	{
346	__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));	352	__asm__ __volatile__("sync; sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
347	}	353	}
348		354
349	extern inline unsigned in_le32(volatile unsigned *addr)	355	extern inline unsigned in_le32(volatile unsigned *addr)
Lines 369-381 Link Here
369		375
370	extern inline void out_le32(volatile unsigned *addr, int val)	376	extern inline void out_le32(volatile unsigned *addr, int val)
371	{	377	{
372	__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :	378	__asm__ __volatile__("sync; stwbrx %1,0,%2; eieio" : "=m" (*addr) :
373	"r" (val), "r" (addr));	379	"r" (val), "r" (addr));
374	}	380	}
375		381
376	extern inline void out_be32(volatile unsigned *addr, int val)	382	extern inline void out_be32(volatile unsigned *addr, int val)
377	{	383	{
378	__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));	384	__asm__ __volatile__("sync; stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
379	}	385	}
380		386
381	static inline int check_signature(unsigned long io_addr,	387	static inline int check_signature(unsigned long io_addr,

Lines 17-23 Link Here

(-)linux-2.4.22/include/asm-ppc/page.h (+2 lines)
17	#include <asm/system.h> /* for xmon definition */	17	#include <asm/system.h> /* for xmon definition */
18		18
19	#ifdef CONFIG_XMON	19	#ifdef CONFIG_XMON
		20	extern void xmon_printf(const char *fmt, ...);
20	#define BUG() do { \	21	#define BUG() do { \
		22	xmon_printf("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
21	printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \	23	printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
22	xmon(0); \	24	xmon(0); \
23	} while (0)	25	} while (0)

Lines 96-103 Link Here

(-)linux-2.4.22/include/asm-ppc/pmac_feature.h (-2 / +2 lines)
96	#define PMAC_TYPE_UNKNOWN_CORE99 0x5f	96	#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
97		97
98	/* MacRisc2 with UniNorth 2.0 */	98	/* MacRisc2 with UniNorth 2.0 */
99	#define PMAC_TYPE_RACKMAC 0x80 /* XServe */	99	#define PMAC_TYPE_RACKMAC 0x80 /* XServes (all) */
100	#define PMAC_TYPE_WINDTUNNEL 0x81	100	#define PMAC_TYPE_WINDTUNNEL 0x81 /* Windtunnel */
101		101
102	/* MacRISC2 machines based on the Pangea chipset	102	/* MacRISC2 machines based on the Pangea chipset
103	*/	103	*/




/*
 *    Copyright 2000 MontaVista Software Inc.
 *	PPC405GP modifications
 * 	Author: MontaVista Software, Inc.
 *         	frank_rowand@mvista.com or source@mvista.com
 * 	   	debbie_chu@mvista.com
 *
 *    Module name: ppc405_serial.h
 *
 *    Description:
 *      Macros, definitions, and data structures specific to the IBM PowerPC
 *      405 on-chip serial port devices.
 */

#ifdef __KERNEL__
#ifndef __ASMPPC_PPC4xx_SERIAL_H
#define __ASMPPC_PPC4xx_SERIAL_H

#include <linux/config.h>

#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE	64
#else
#define RS_TABLE_SIZE	4
#endif

#define PPC405GP_UART0_INT	0
#define PPC405GP_UART1_INT	1

/*
** 405GP UARTs are *not* PCI devices, so need to specify a non-pci memory
** address and an io_type of SERIAL_IO_MEM.
*/

#define PPC405GP_UART0_IO_BASE	(u8 *) 0xef600300
#define PPC405GP_UART1_IO_BASE	(u8 *) 0xef600400

/*
**  - there is no config option for this
**  - this name could be more informative
**  - also see arch/ppc/kernel/ppc405_serial.c
**
** #define CONFIG_PPC405GP_INTERNAL_CLOCK
*/
#ifdef	CONFIG_PPC405GP_INTERNAL_CLOCK
#define BASE_BAUD		201600
#else
#define BASE_BAUD		691200
#endif


#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS	(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
#define STD_COM4_FLAGS	(ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
#else
#define STD_COM_FLAGS	(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define STD_COM4_FLAGS	(ASYNC_BOOT_AUTOCONF)
#endif


#ifdef CONFIG_STB03XXX

#define UART0_IO_BASE 0x40040000
#define UART0_INT     20

#define STD_SERIAL_PORT_DFNS \
    /* ttyS0 */ \
    { 0, BASE_BAUD, 0, UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \
    UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL },

#elif defined(CONFIG_UART1_DFLT_CONSOLE)

#define STD_SERIAL_PORT_DFNS \
    /* ttyS1 */ \
    { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \
    PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL },        \
    /* ttyS0 */ \
    { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \
    PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL },

#else

#define STD_SERIAL_PORT_DFNS \
    /* ttyS0 */ \
    { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \
    PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL },        \
    /* ttyS1 */ \
    { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \
    PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL },

#endif


#define SERIAL_PORT_DFNS     \
	STD_SERIAL_PORT_DFNS \
	{}



#endif	/* __ASMPPC_PPC4xx_SERIAL_H */
#endif /* __KERNEL__ */

Lines 716-721 Link Here

(-)linux-2.4.22/include/asm-ppc/processor.h (+1 lines)
716	vector128 vr[32]; /* Complete AltiVec set */	716	vector128 vr[32]; /* Complete AltiVec set */
717	vector128 vscr; /* AltiVec status */	717	vector128 vscr; /* AltiVec status */
718	unsigned long vrsave;	718	unsigned long vrsave;
		719	int used_vr; /* set if process has used altivec */
719	#endif /* CONFIG_ALTIVEC */	720	#endif /* CONFIG_ALTIVEC */
720	#if defined(CONFIG_4xx)	721	#if defined(CONFIG_4xx)
721	/* Saved 4xx debug registers */	722	/* Saved 4xx debug registers */




	/*
	 * Try to get the semaphore, take the slow path if we fail.
	 */
	if (unlikely(atomic_dec_return(&sem->count) < 0))
		__down(sem);
	smp_wmb();
}

extern inline int down_interruptible(struct semaphore * sem)

	CHECK_MAGIC(sem->__magic);
#endif

	if (unlikely(atomic_dec_return(&sem->count) < 0))
		ret = __down_interruptible(sem);
	smp_wmb();
	return ret;
}

extern inline int down_trylock(struct semaphore * sem)
{
	int ret;

#if WAITQUEUE_DEBUG
	CHECK_MAGIC(sem->__magic);
#endif

	return atomic_dec_if_positive(&sem->count) < 0;
	smp_wmb();
	return ret;
}

extern inline void up(struct semaphore * sem)

	CHECK_MAGIC(sem->__magic);
#endif

	if (unlikely(atomic_inc_return(&sem->count) <= 0))
	if (atomic_inc_return(&sem->count) <= 0)
		__up(sem);
}


Lines 3-10 Link Here

(-)linux-2.4.22/include/asm-ppc/sigcontext.h (-2 / +1 lines)
3		3
4	#include <asm/ptrace.h>	4	#include <asm/ptrace.h>
5		5
6		6	struct sigcontext {
7	struct sigcontext_struct {
8	unsigned long _unused[4];	7	unsigned long _unused[4];
9	int signal;	8	int signal;
10	unsigned long handler;	9	unsigned long handler;

Lines 17-22 Link Here

(-)linux-2.4.22/include/asm-ppc/smp.h (+4 lines)
17		17
18	#ifndef __ASSEMBLY__	18	#ifndef __ASSEMBLY__
19		19
		20	#define cpu_online(cpu) (cpu_online_map & (1<<(cpu)))
		21
20	struct cpuinfo_PPC {	22	struct cpuinfo_PPC {
21	unsigned long loops_per_jiffy;	23	unsigned long loops_per_jiffy;
22	unsigned long pvr;	24	unsigned long pvr;
Lines 69-74 Link Here
69		71
70	#else /* !(CONFIG_SMP) */	72	#else /* !(CONFIG_SMP) */
71		73
		74	#define cpu_online(cpu) ((cpu) == 0)
		75
72	#endif /* !(CONFIG_SMP) */	76	#endif /* !(CONFIG_SMP) */
73		77
74	#endif /* !(_PPC_SMP_H) */	78	#endif /* !(_PPC_SMP_H) */




#ifndef _ASMPPC_UCONTEXT_H
#define _ASMPPC_UCONTEXT_H

#include <asm/elf.h>
#include <asm/signal.h>

struct mcontext {
	elf_gregset_t	mc_gregs;
	elf_fpregset_t	mc_fregs;
	unsigned long	mc_pad[2];
	elf_vrregset_t	mc_vregs __attribute__((__aligned__(16)));
};

struct ucontext {
	unsigned long	 uc_flags;
	struct ucontext *uc_link;
	stack_t		 uc_stack;
	int		 uc_pad[7];
	struct mcontext	*uc_regs;	/* backward compat */
	sigset_t	 uc_oldsigmask;	/* backward compat */
	int		 uc_pad2;
	sigset_t	 uc_sigmask;
	/* glibc has 1024-bit signal masks, ours are 64-bit */
	int		 uc_maskext[30];
	struct mcontext	 uc_mcontext;
};

#endif /* !_ASMPPC_UCONTEXT_H */

Lines 90-95 Link Here

(-)linux-2.4.22/include/linux/agp_backend.h (+1 lines)
90	NVIDIA_NFORCE2,	90	NVIDIA_NFORCE2,
91	NVIDIA_GENERIC,	91	NVIDIA_GENERIC,
92	HP_ZX1,	92	HP_ZX1,
		93	APPLE_UNINORTH
93	};	94	};
94		95
95	typedef struct _agp_version {	96	typedef struct _agp_version {

Lines 63-68 Link Here

(-)linux-2.4.22/include/linux/blkdev.h (+7 lines)
63	typedef int (make_request_fn) (request_queue_t q, int rw, struct buffer_head bh);	63	typedef int (make_request_fn) (request_queue_t q, int rw, struct buffer_head bh);
64	typedef void (plug_device_fn) (request_queue_t *q, kdev_t device);	64	typedef void (plug_device_fn) (request_queue_t *q, kdev_t device);
65	typedef void (unplug_device_fn) (void *q);	65	typedef void (unplug_device_fn) (void *q);
		66	typedef void (activity_fn) (void *data, int rw);
		67
66		68
67	struct request_list {	69	struct request_list {
68	unsigned int count;	70	unsigned int count;
Lines 114-125 Link Here
114	merge_requests_fn * merge_requests_fn;	116	merge_requests_fn * merge_requests_fn;
115	make_request_fn * make_request_fn;	117	make_request_fn * make_request_fn;
116	plug_device_fn * plug_device_fn;	118	plug_device_fn * plug_device_fn;
		119	activity_fn * activity_fn;
		120
117	/*	121	/*
118	* The queue owner gets to use this for whatever they like.	122	* The queue owner gets to use this for whatever they like.
119	* ll_rw_blk doesn't touch it.	123	* ll_rw_blk doesn't touch it.
120	*/	124	*/
121	void * queuedata;	125	void * queuedata;
122		126
		127	void * activity_data;
		128
123	/*	129	/*
124	* This is used to remove the plug when tq_disk runs.	130	* This is used to remove the plug when tq_disk runs.
125	*/	131	*/
Lines 246-251 Link Here
246	extern void blk_queue_throttle_sectors(request_queue_t *, int);	252	extern void blk_queue_throttle_sectors(request_queue_t *, int);
247	extern void blk_queue_make_request(request_queue_t , make_request_fn );	253	extern void blk_queue_make_request(request_queue_t , make_request_fn );
248	extern void generic_unplug_device(void *);	254	extern void generic_unplug_device(void *);
		255	extern void blk_queue_activity_fn(request_queue_t , activity_fn , void *);
249	extern inline int blk_seg_merge_ok(struct buffer_head , struct buffer_head );	256	extern inline int blk_seg_merge_ok(struct buffer_head , struct buffer_head );
250		257
251	extern int * blk_size[MAX_BLKDEV];	258	extern int * blk_size[MAX_BLKDEV];




/*
 *  linux/include/linux/cpufreq.h
 *
 *  Copyright (C) 2001 Russell King
 *            (C) 2002 Dominik Brodowski <linux@brodo.de>
 *            
 *
 * $Id: cpufreq.h,v 1.29 2002/11/11 15:35:47 db Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _LINUX_CPUFREQ_H
#define _LINUX_CPUFREQ_H

#include <linux/config.h>
#include <linux/notifier.h>
#include <linux/threads.h>


/*********************************************************************
 *                     CPUFREQ NOTIFIER INTERFACE                    *
 *********************************************************************/

int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list);
int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list);

#define CPUFREQ_TRANSITION_NOTIFIER     (0)
#define CPUFREQ_POLICY_NOTIFIER         (1)

#define CPUFREQ_ALL_CPUS        ((NR_CPUS))


/********************** cpufreq policy notifiers *********************/

#define CPUFREQ_POLICY_POWERSAVE        (1)
#define CPUFREQ_POLICY_PERFORMANCE      (2)

/* values here are CPU kHz so that hardware which doesn't run with some
 * frequencies can complain without having to guess what per cent / per
 * mille means. */
struct cpufreq_policy {
	unsigned int            cpu;    /* cpu nr or CPUFREQ_ALL_CPUS */
	unsigned int            min;    /* in kHz */
	unsigned int            max;    /* in kHz */
        unsigned int            policy; /* see above */
	unsigned int            max_cpu_freq; /* for information */
};

#define CPUFREQ_ADJUST          (0)
#define CPUFREQ_INCOMPATIBLE    (1)
#define CPUFREQ_NOTIFY          (2)


/******************** cpufreq transition notifiers *******************/

#define CPUFREQ_PRECHANGE	(0)
#define CPUFREQ_POSTCHANGE	(1)

struct cpufreq_freqs {
	unsigned int cpu;      /* cpu nr or CPUFREQ_ALL_CPUS */
	unsigned int old;
	unsigned int new;
};


/**
 * cpufreq_scale - "old * mult / div" calculation for large values (32-bit-arch safe)
 * @old:   old value
 * @div:   divisor
 * @mult:  multiplier
 *
 * Needed for loops_per_jiffy and similar calculations.  We do it 
 * this way to avoid math overflow on 32-bit machines.  This will
 * become architecture dependent once high-resolution-timer is
 * merged (or any other thing that introduces sc_math.h).
 *
 *    new = old * mult / div
 */
static inline unsigned long cpufreq_scale(unsigned long old, u_int div, u_int mult)
{
	unsigned long val, carry;

	mult /= 100;
	div  /= 100;
        val   = (old / div) * mult;
        carry = old % div;
	carry = carry * mult / div;

	return carry + val;
};


/*********************************************************************
 *                      DYNAMIC CPUFREQ INTERFACE                    *
 *********************************************************************/
#ifdef CONFIG_CPU_FREQ_DYNAMIC
/* TBD */
#endif /* CONFIG_CPU_FREQ_DYNAMIC */


/*********************************************************************
 *                      CPUFREQ DRIVER INTERFACE                     *
 *********************************************************************/

typedef int (*cpufreq_policy_t)          (struct cpufreq_policy *policy);

struct cpufreq_driver {
	/* needed by all drivers */
	cpufreq_policy_t        verify;
	cpufreq_policy_t        setpolicy;
	struct cpufreq_policy   *policy;
#ifdef CONFIG_CPU_FREQ_DYNAMIC
	/* TBD */
#endif
	/* 2.4. compatible API */
#ifdef CONFIG_CPU_FREQ_24_API
	unsigned int            cpu_min_freq[NR_CPUS];
	unsigned int            cpu_cur_freq[NR_CPUS];
#endif
};

int cpufreq_register(struct cpufreq_driver *driver_data);
int cpufreq_unregister(void);

void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state);


static inline void cpufreq_verify_within_limits(struct cpufreq_policy *policy, unsigned int min, unsigned int max) 
{
	if (policy->min < min)
		policy->min = min;
	if (policy->max < min)
		policy->max = min;
	if (policy->min > max)
		policy->min = max;
	if (policy->max > max)
		policy->max = max;
	if (policy->min > policy->max)
		policy->min = policy->max;
	return;
}

/*********************************************************************
 *                        CPUFREQ 2.6. INTERFACE                     *
 *********************************************************************/
int cpufreq_set_policy(struct cpufreq_policy *policy);
int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu);

#ifdef CONFIG_PM
int cpufreq_restore(void);
#endif


#ifdef CONFIG_CPU_FREQ_24_API
/*********************************************************************
 *                        CPUFREQ 2.4. INTERFACE                     *
 *********************************************************************/
int cpufreq_setmax(unsigned int cpu);
int cpufreq_set(unsigned int kHz, unsigned int cpu);
unsigned int cpufreq_get(unsigned int cpu);

/* /proc/sys/cpu */
enum {
	CPU_NR   = 1,           /* compatibilty reasons */
	CPU_NR_0 = 1,
	CPU_NR_1 = 2,
	CPU_NR_2 = 3,
	CPU_NR_3 = 4,
	CPU_NR_4 = 5,
	CPU_NR_5 = 6,
	CPU_NR_6 = 7,
	CPU_NR_7 = 8,
	CPU_NR_8 = 9,
	CPU_NR_9 = 10,
	CPU_NR_10 = 11,
	CPU_NR_11 = 12,
	CPU_NR_12 = 13,
	CPU_NR_13 = 14,
	CPU_NR_14 = 15,
	CPU_NR_15 = 16,
	CPU_NR_16 = 17,
	CPU_NR_17 = 18,
	CPU_NR_18 = 19,
	CPU_NR_19 = 20,
	CPU_NR_20 = 21,
	CPU_NR_21 = 22,
	CPU_NR_22 = 23,
	CPU_NR_23 = 24,
	CPU_NR_24 = 25,
	CPU_NR_25 = 26,
	CPU_NR_26 = 27,
	CPU_NR_27 = 28,
	CPU_NR_28 = 29,
	CPU_NR_29 = 30,
	CPU_NR_30 = 31,
	CPU_NR_31 = 32,
};

/* /proc/sys/cpu/{0,1,...,(NR_CPUS-1)} */
enum {
	CPU_NR_FREQ_MAX = 1,
	CPU_NR_FREQ_MIN = 2,
	CPU_NR_FREQ = 3,
};

#define CTL_CPU_VARS_SPEED_MAX(cpunr) { \
                .ctl_name	= CPU_NR_FREQ_MAX, \
                .data		= &cpu_max_freq[cpunr], \
                .procname	= "speed-max", \
                .maxlen		= sizeof(cpu_max_freq[cpunr]),\
                .mode		= 0444, \
                .proc_handler	= proc_dointvec, }

#define CTL_CPU_VARS_SPEED_MIN(cpunr) { \
                .ctl_name	= CPU_NR_FREQ_MIN, \
                .data		= &cpu_min_freq[cpunr], \
                .procname	= "speed-min", \
                .maxlen		= sizeof(cpu_min_freq[cpunr]),\
                .mode		= 0444, \
                .proc_handler	= proc_dointvec, }

#define CTL_CPU_VARS_SPEED(cpunr) { \
                .ctl_name	= CPU_NR_FREQ, \
                .procname	= "speed", \
                .mode		= 0644, \
                .proc_handler	= cpufreq_procctl, \
                .strategy	= cpufreq_sysctl, \
                .extra1		= (void*) (cpunr), }

#define CTL_TABLE_CPU_VARS(cpunr) static ctl_table ctl_cpu_vars_##cpunr[] = {\
                CTL_CPU_VARS_SPEED_MAX(cpunr), \
                CTL_CPU_VARS_SPEED_MIN(cpunr), \
                CTL_CPU_VARS_SPEED(cpunr),  \
                { .ctl_name = 0, }, }

/* the ctl_table entry for each CPU */
#define CPU_ENUM(s) { \
                .ctl_name	= (CPU_NR + s), \
                .procname	= #s, \
                .mode		= 0555, \
                .child		= ctl_cpu_vars_##s }

#endif /* CONFIG_CPU_FREQ_24_API */

#endif /* _LINUX_CPUFREQ_H */




}

extern void set_buffer_flushtime(struct buffer_head *);
extern unsigned long get_buffer_flushtime(void);
extern void balance_dirty(void);
extern int check_disk_change(kdev_t);
extern int invalidate_inodes(struct super_block *);

	return get_hash_table(sb->s_dev, block, sb->s_blocksize);
}
extern void wakeup_bdflush(void);
extern void wakeup_kupdate(void);
extern void put_unused_buffer_head(struct buffer_head * bh);
extern struct buffer_head * get_unused_buffer_head(int async);
extern int block_dump;

extern int brw_page(int, struct page *, kdev_t, int [], int);


Lines 345-350 Link Here

(-)linux-2.4.22/include/linux/ide.h (+9 lines)
345	# define ide_ack_intr(hwif) (1)	345	# define ide_ack_intr(hwif) (1)
346	#endif	346	#endif
347		347
		348	/* Do we have arch-specififed "reserved" IDE slots for bootable
		349	* devices ? By default, we have 2
		350	*/
		351	#ifndef IDE_ARCH_RESERVED_HWIFS
		352	# define ide_reserved_hwifs() 2
		353	#endif
		354
348	/* Currently only Atari needs it */	355	/* Currently only Atari needs it */
349	#ifndef IDE_ARCH_LOCK	356	#ifndef IDE_ARCH_LOCK
350	# define ide_release_lock() do {} while (0)	357	# define ide_release_lock() do {} while (0)
Lines 1005-1010 Link Here
1005	unsigned no_dsc : 1; /* 0 default, 1 dsc_overlap disabled */	1012	unsigned no_dsc : 1; /* 0 default, 1 dsc_overlap disabled */
1006		1013
1007	void hwif_data; / extra hwif data */	1014	void hwif_data; / extra hwif data */
		1015
		1016	void (led_act)(void data, int rw);
1008	} ide_hwif_t;	1017	} ide_hwif_t;
1009		1018
1010	/*	1019	/*





	return gfp_mask;
}

extern int heap_stack_gap;

/*
 * vma is the first one with  address < vma->vm_end,
 * and even  address < vma->vm_start. Have to extend vma.
 *
 * Locking: vm_start can decrease under you if you only hold
 * the read semaphore, you either need the write semaphore
 * or both the read semaphore and the page_table_lock acquired
 * if you want vm_start consistent. vm_end and the vma layout
 * are just consistent with only the read semaphore acquired
 * instead.
 */
#define EXPAND_STACK_HAS_3_ARGS
static inline int expand_stack(struct vm_area_struct * vma, unsigned long address,
			       struct vm_area_struct * prev_vma)
{
	unsigned long grow;
	int err = -ENOMEM;

	/*
	 * vma->vm_start/vm_end cannot change under us because the caller is required

	 * before relocating the vma range ourself.
	 */
	address &= PAGE_MASK;
	if (prev_vma && prev_vma->vm_end + (heap_stack_gap << PAGE_SHIFT) > address)
		goto out;
	spin_lock(&vma->vm_mm->page_table_lock);
	grow = (vma->vm_start - address) >> PAGE_SHIFT;
	if (vma->vm_end - address > current->rlim[RLIMIT_STACK].rlim_cur ||
	    ((vma->vm_mm->total_vm + grow) << PAGE_SHIFT) > current->rlim[RLIMIT_AS].rlim_cur)
		goto out_unlock;
		return -ENOMEM;
	}
	vma->vm_start = address;
	vma->vm_pgoff -= grow;
	vma->vm_mm->total_vm += grow;
	if (vma->vm_flags & VM_LOCKED)
		vma->vm_mm->locked_vm += grow;
	err = 0;
 out_unlock:
	spin_unlock(&vma->vm_mm->page_table_lock);
 out:
	return err;
}

/* Look up the first VMA which satisfies  addr < vm_end,  NULL if none. */

Lines 403-411 Link Here

(-)linux-2.4.22/include/linux/pci_ids.h (-28 / +47 lines)
403	#define PCI_DEVICE_ID_IBM_MPIC 0x0046	403	#define PCI_DEVICE_ID_IBM_MPIC 0x0046
404	#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d	404	#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d
405	#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096	405	#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096
		406	#define PCI_DEVICE_ID_IBM_CPC700 0x00f9
406	#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc	407	#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc
407	#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105	408	#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105
408	#define PCI_DEVICE_ID_IBM_405GP 0x0156	409	#define PCI_DEVICE_ID_IBM_405GP 0x0156
409	#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd	410	#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
410	#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff	411	#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff
411		412
Lines 654-659 Link Here
654	#define PCI_DEVICE_ID_TI_4410 0xac41	655	#define PCI_DEVICE_ID_TI_4410 0xac41
655	#define PCI_DEVICE_ID_TI_4451 0xac42	656	#define PCI_DEVICE_ID_TI_4451 0xac42
656	#define PCI_DEVICE_ID_TI_1420 0xac51	657	#define PCI_DEVICE_ID_TI_1420 0xac51
		658	#define PCI_DEVICE_ID_TI_1510 0xac56
657		659
658	#define PCI_VENDOR_ID_SONY 0x104d	660	#define PCI_VENDOR_ID_SONY 0x104d
659	#define PCI_DEVICE_ID_SONY_CXD3222 0x8039	661	#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
Lines 747-752 Link Here
747	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027	749	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
748	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d	750	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
749	#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030	751	#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030
		752	#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
		753	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
		754	#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e
		755	#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
750		756
751	#define PCI_VENDOR_ID_YAMAHA 0x1073	757	#define PCI_VENDOR_ID_YAMAHA 0x1073
752	#define PCI_DEVICE_ID_YAMAHA_724 0x0004	758	#define PCI_DEVICE_ID_YAMAHA_724 0x0004
Lines 957-989 Link Here
957	#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021	963	#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021
958	#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022	964	#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022
959		965
960	#define PCI_VENDOR_ID_NVIDIA 0x10de	966	#define PCI_VENDOR_ID_NVIDIA 0x10de
961	#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020	967	#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
962	#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028	968	#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
963	#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029	969	#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029
964	#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C	970	#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C
965	#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D	971	#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D
966	#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065	972	#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0
967	#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0	973	#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100
968	#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100	974	#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101
969	#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101	975	#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103
970	#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103	976	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110
971	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110	977	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111
972	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111	978	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112
973	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112	979	#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113
974	#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113	980	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150
975	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150	981	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151
976	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151	982	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152
977	#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152	983	#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153
978	#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153	984	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170
979	#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0	985	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171
980	#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4	986	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172
981	#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc	987	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174
982	#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0	988	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175
983	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200	989	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
984	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201	990	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178
985	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202	991	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
986	#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203	992	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A
		993	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B
		994	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C
		995	#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
		996	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
		997	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201
		998	#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202
		999	#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203
		1000	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250
		1001	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251
		1002	#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253
		1003	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258
		1004	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259
		1005	#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B
987		1006
988	#define PCI_VENDOR_ID_IMS 0x10e0	1007	#define PCI_VENDOR_ID_IMS 0x10e0
989	#define PCI_DEVICE_ID_IMS_8849 0x8849	1008	#define PCI_DEVICE_ID_IMS_8849 0x8849

Lines 143-148 Link Here

(-)linux-2.4.22/include/linux/pmu.h (+3 lines)
143	void (done)(struct adb_request ), int nbytes, ...);	143	void (done)(struct adb_request ), int nbytes, ...);
144		144
145	extern void pmu_poll(void);	145	extern void pmu_poll(void);
		146	extern void pmu_poll_adb(void); /* For use by xmon */
		147	extern void pmu_wait_complete(struct adb_request *req);
146		148
147	/* For use before switching interrupts off for a long time;	149	/* For use before switching interrupts off for a long time;
148	* warning: not stackable	150	* warning: not stackable
Lines 154-159 Link Here
154		156
155	extern void pmu_restart(void);	157	extern void pmu_restart(void);
156	extern void pmu_shutdown(void);	158	extern void pmu_shutdown(void);
		159	extern void pmu_unlock(void);
157		160
158	extern int pmu_present(void);	161	extern int pmu_present(void);
159	extern int pmu_get_model(void);	162	extern int pmu_get_model(void);

Lines 146-151 Link Here

(-)linux-2.4.22/include/linux/sysctl.h (+3 lines)
146	VM_MAX_MAP_COUNT=11, /* int: Maximum number of active map areas */	146	VM_MAX_MAP_COUNT=11, /* int: Maximum number of active map areas */
147	VM_MIN_READAHEAD=12, /* Min file readahead */	147	VM_MIN_READAHEAD=12, /* Min file readahead */
148	VM_MAX_READAHEAD=13, /* Max file readahead */	148	VM_MAX_READAHEAD=13, /* Max file readahead */
		149	VM_HEAP_STACK_GAP=14, /* int: page gap between heap and stack */
		150	VM_LAPTOP_MODE=15,
		151	VM_BLOCK_DUMP=16,
149	};	152	};
150		153
151		154




 * spurious .aligns.
 */
#if WAITQUEUE_DEBUG
#ifdef CONFIG_XMON
extern void xmon_printf(const char* fmt, ...);
#define wqbug_printf	xmon_printf
#else
#define wqbug_printf	printk
#endif
#define WQ_BUG()	BUG()
#define CHECK_MAGIC(x)							\
	do {									\
		if ((x) != (long)&(x)) {					\
			wqbug_printf("bad magic %lx (should be %lx), ",		\
				(long)x, (long)&(x));				\
			WQ_BUG();						\
		}								\

#define CHECK_MAGIC_WQHEAD(x)							\
	do {									\
		if ((x)->__magic != (long)&((x)->__magic)) {			\
			wqbug_printf("bad magic %lx (should be %lx, creator %lx), ",	\
			(x)->__magic, (long)&((x)->__magic), (x)->__creator);	\
			WQ_BUG();						\
		}								\

Lines 161-167 Link Here

(-)linux-2.4.22/init/main.c (-1 / +1 lines)
161	better than 1% */	161	better than 1% */
162	#define LPS_PREC 8	162	#define LPS_PREC 8
163		163
164	void __init calibrate_delay(void)	164	void /__init/ calibrate_delay(void)
165	{	165	{
166	unsigned long ticks, loopbit;	166	unsigned long ticks, loopbit;
167	int lps_precision = LPS_PREC;	167	int lps_precision = LPS_PREC;

Lines 9-15 Link Here

(-)linux-2.4.22/kernel/Makefile (-1 / +2 lines)
9		9
10	O_TARGET := kernel.o	10	O_TARGET := kernel.o
11		11
12	export-objs = signal.o sys.o kmod.o context.o ksyms.o pm.o exec_domain.o printk.o	12	export-objs = signal.o sys.o kmod.o context.o ksyms.o pm.o exec_domain.o printk.o cpufreq.o
13		13
14	obj-y = sched.o dma.o fork.o exec_domain.o panic.o printk.o \	14	obj-y = sched.o dma.o fork.o exec_domain.o panic.o printk.o \
15	module.o exit.o itimer.o info.o time.o softirq.o resource.o \	15	module.o exit.o itimer.o info.o time.o softirq.o resource.o \
Lines 19-24 Link Here
19	obj-$(CONFIG_UID16) += uid16.o	19	obj-$(CONFIG_UID16) += uid16.o
20	obj-$(CONFIG_MODULES) += ksyms.o	20	obj-$(CONFIG_MODULES) += ksyms.o
21	obj-$(CONFIG_PM) += pm.o	21	obj-$(CONFIG_PM) += pm.o
		22	obj-$(CONFIG_CPU_FREQ) += cpufreq.o
22		23
23	ifneq ($(CONFIG_IA64),y)	24	ifneq ($(CONFIG_IA64),y)
24	# According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is	25	# According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is




/*
 *  linux/kernel/cpufreq.c
 *
 *  Copyright (C) 2001 Russell King
 *            (C) 2002 Dominik Brodowski <linux@brodo.de>
 *
 *  $Id: cpufreq.c,v 1.50 2002/11/11 15:35:48 db Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <asm/system.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/ctype.h>
#include <linux/proc_fs.h>

#include <asm/uaccess.h>

#ifdef CONFIG_CPU_FREQ_24_API
#include <linux/sysctl.h>
#endif


/**
 * The "cpufreq driver" - the arch- or hardware-dependend low
 * level driver of CPUFreq support, and its locking mutex. 
 * cpu_max_freq is in kHz.
 */
static struct cpufreq_driver   	*cpufreq_driver;
static DECLARE_MUTEX            (cpufreq_driver_sem);


/**
 * Two notifier lists: the "policy" list is involved in the 
 * validation process for a new CPU frequency policy; the 
 * "transition" list for kernel code that needs to handle
 * changes to devices when the CPU clock speed changes.
 * The mutex locks both lists. If both cpufreq_driver_sem
 * and cpufreq_notifier_sem need to be hold, get cpufreq_driver_sem
 * first.
 */
static struct notifier_block    *cpufreq_policy_notifier_list;
static struct notifier_block    *cpufreq_transition_notifier_list;
static DECLARE_MUTEX            (cpufreq_notifier_sem);


/**
 * The cpufreq default policy. Can be set by a "cpufreq=..." command
 * line option.
 */
static struct cpufreq_policy default_policy = {
	.cpu    = CPUFREQ_ALL_CPUS,
	.min    = 0,
	.max    = 0,
	.policy = 0,
};


#ifdef CONFIG_CPU_FREQ_24_API
/**
 * A few values needed by the 2.4.-compatible API
 */
static unsigned int     cpu_max_freq[NR_CPUS];
static unsigned int     cpu_min_freq[NR_CPUS];
static unsigned int     cpu_cur_freq[NR_CPUS];
#endif



/*********************************************************************
 *                              2.6. API                             *
 *********************************************************************/

/**
 * cpufreq_parse_policy - parse a policy string
 * @input_string: the string to parse.
 * @policy: the policy written inside input_string
 *
 * This function parses a "policy string" - something the user echo'es into
 * /proc/cpufreq or gives as boot parameter - into a struct cpufreq_policy.
 * If there are invalid/missing entries, they are replaced with current
 * cpufreq policy.
 */
static int cpufreq_parse_policy(char input_string[42], struct cpufreq_policy *policy)
{
	unsigned int            min = 0;
	unsigned int            max = 0;
	unsigned int            cpu = 0;
	char			policy_string[42] = {'\0'};
	struct cpufreq_policy   current_policy;
	unsigned int            result = -EFAULT;
	unsigned int            i = 0;

	if (!policy)
		return -EINVAL;

	policy->min = 0;
	policy->max = 0;
	policy->policy = 0;
	policy->cpu = CPUFREQ_ALL_CPUS;

	if (sscanf(input_string, "%d:%d:%d:%s", &cpu, &min, &max, policy_string) == 4) 
	{
		policy->min = min;
		policy->max = max;
		policy->cpu = cpu;
		result = 0;
		goto scan_policy;
	}
	if (sscanf(input_string, "%d%%%d%%%d%%%s", &cpu, &min, &max, policy_string) == 4)
	{
		if (!cpufreq_get_policy(&current_policy, cpu)) {
			policy->min = (min * current_policy.max_cpu_freq) / 100;
			policy->max = (max * current_policy.max_cpu_freq) / 100;
			policy->cpu = cpu;
			result = 0;
			goto scan_policy;
		}
	}

	if (sscanf(input_string, "%d:%d:%s", &min, &max, policy_string) == 3) 
	{
		policy->min = min;
		policy->max = max;
		result = 0;
		goto scan_policy;
	}

	if (sscanf(input_string, "%d%%%d%%%s", &min, &max, policy_string) == 3)
	{
		if (!cpufreq_get_policy(&current_policy, cpu)) {
			policy->min = (min * current_policy.max_cpu_freq) / 100;
			policy->max = (max * current_policy.max_cpu_freq) / 100;
			result = 0;
			goto scan_policy;
		}
	}

	return -EINVAL;

scan_policy:

	for (i=0;i<sizeof(policy_string);i++){
		if (policy_string[i]=='\0')
			break;
		policy_string[i] = tolower(policy_string[i]);
	}

	if (!strncmp(policy_string, "powersave", 6) ||  
            !strncmp(policy_string, "eco", 3) ||       
	    !strncmp(policy_string, "batter", 6) ||
	    !strncmp(policy_string, "low", 3)) 
	{
		result = 0;
		policy->policy = CPUFREQ_POLICY_POWERSAVE;
	}
	else if (!strncmp(policy_string, "performance",6) ||
	    !strncmp(policy_string, "high",4) ||
	    !strncmp(policy_string, "full",4))
	{
		result = 0;
		policy->policy = CPUFREQ_POLICY_PERFORMANCE;
	}
	else if (!cpufreq_get_policy(&current_policy, policy->cpu))
	{
		policy->policy = current_policy.policy;
	}
	else
	{
		policy->policy = 0;
	}

	return result;
}


/*
 * cpufreq command line parameter.  Must be hard values (kHz)
 *  cpufreq=1000000:2000000:PERFORMANCE   
 * to set the default CPUFreq policy.
 */
static int __init cpufreq_setup(char *str)
{
	cpufreq_parse_policy(str, &default_policy);
	default_policy.cpu = CPUFREQ_ALL_CPUS;
	return 1;
}
__setup("cpufreq=", cpufreq_setup);


#ifdef CONFIG_PROC_FS

/**
 * cpufreq_proc_read - read /proc/cpufreq
 *
 * This function prints out the current cpufreq policy.
 */
static int cpufreq_proc_read (
	char			*page,
	char			**start,
	off_t			off,
	int 			count,
	int 			*eof,
	void			*data)
{
	char			*p = page;
	int			len = 0;
	struct cpufreq_policy   policy;
	unsigned int            min_pctg = 0;
	unsigned int            max_pctg = 0;
	unsigned int            i = 0;

	if (off != 0)
		goto end;

	p += sprintf(p, "          minimum CPU frequency  -  maximum CPU frequency  -  policy\n");
	for (i=0;i<NR_CPUS;i++) {
		if (!cpu_online(i))
			continue;

		cpufreq_get_policy(&policy, i);

		if (!policy.max_cpu_freq)
			continue;

		min_pctg = (policy.min * 100) / policy.max_cpu_freq;
		max_pctg = (policy.max * 100) / policy.max_cpu_freq;

		p += sprintf(p, "CPU%3d    %9d kHz (%3d %%)  -  %9d kHz (%3d %%)  -  ",
			     i , policy.min, min_pctg, policy.max, max_pctg);
		switch (policy.policy) {
		case CPUFREQ_POLICY_POWERSAVE:
			p += sprintf(p, "powersave\n");
			break;
		case CPUFREQ_POLICY_PERFORMANCE:
			p += sprintf(p, "performance\n");
			break;
		default:
			p += sprintf(p, "INVALID\n");
			break;
		}
	}
end:
	len = (p - page);
	if (len <= off+count) 
		*eof = 1;
	*start = page + off;
	len -= off;
	if (len>count) 
		len = count;
	if (len<0) 
		len = 0;

	return len;
}


/**
 * cpufreq_proc_write - handles writing into /proc/cpufreq
 *
 * This function calls the parsing script and then sets the policy
 * accordingly.
 */
static int cpufreq_proc_write (
        struct file		*file,
        const char		*buffer,
        unsigned long		count,
        void			*data)
{
	int                     result = 0;
	char			proc_string[42] = {'\0'};
	struct cpufreq_policy   policy;


	if ((count > sizeof(proc_string) - 1))
		return -EINVAL;
	
	if (copy_from_user(proc_string, buffer, count))
		return -EFAULT;
	
	proc_string[count] = '\0';

	result = cpufreq_parse_policy(proc_string, &policy);
	if (result)
		return -EFAULT;

	cpufreq_set_policy(&policy);

	return count;
}


/**
 * cpufreq_proc_init - add "cpufreq" to the /proc root directory
 *
 * This function adds "cpufreq" to the /proc root directory.
 */
static unsigned int cpufreq_proc_init (void)
{
	struct proc_dir_entry *entry = NULL;

        /* are these acceptable values? */
	entry = create_proc_entry("cpufreq", S_IFREG|S_IRUGO|S_IWUSR, 
				  &proc_root);

	if (!entry) {
		printk(KERN_ERR "unable to create /proc/cpufreq entry\n");
		return -EIO;
	} else {
		entry->read_proc = cpufreq_proc_read;
		entry->write_proc = cpufreq_proc_write;
	}

	return 0;
}


/**
 * cpufreq_proc_exit - removes "cpufreq" from the /proc root directory.
 *
 * This function removes "cpufreq" from the /proc root directory.
 */
static void cpufreq_proc_exit (void)
{
	remove_proc_entry("cpufreq", &proc_root);
	return;
}
#endif /* CONFIG_PROC_FS */



/*********************************************************************
 *                        2.4. COMPATIBLE API                        *
 *********************************************************************/

#ifdef CONFIG_CPU_FREQ_24_API
/** 
 * cpufreq_set - set the CPU frequency
 * @freq: target frequency in kHz
 * @cpu: CPU for which the frequency is to be set
 *
 * Sets the CPU frequency to freq.
 */
int cpufreq_set(unsigned int freq, unsigned int cpu)
{
	struct cpufreq_policy policy;
	down(&cpufreq_driver_sem);
	if (!cpufreq_driver || !cpu_max_freq) {
		up(&cpufreq_driver_sem);
		return -EINVAL;
	}

	policy.min = freq;
	policy.max = freq;
	policy.policy = CPUFREQ_POLICY_POWERSAVE;
	policy.cpu = cpu;
	
	up(&cpufreq_driver_sem);

	return cpufreq_set_policy(&policy);
}
EXPORT_SYMBOL_GPL(cpufreq_set);


/** 
 * cpufreq_setmax - set the CPU to the maximum frequency
 * @cpu - affected cpu;
 *
 * Sets the CPU frequency to the maximum frequency supported by
 * this CPU.
 */
int cpufreq_setmax(unsigned int cpu)
{
	if (!cpu_online(cpu) && (cpu != CPUFREQ_ALL_CPUS))
		return -EINVAL;
	return cpufreq_set(cpu_max_freq[cpu], cpu);
}
EXPORT_SYMBOL_GPL(cpufreq_setmax);


/** 
 * cpufreq_get - get the current CPU frequency (in kHz)
 * @cpu: CPU number - currently without effect.
 *
 * Get the CPU current (static) CPU frequency
 */
unsigned int cpufreq_get(unsigned int cpu)
{
	if (!cpu_online(cpu))
		return -EINVAL;
	return cpu_cur_freq[cpu];
}
EXPORT_SYMBOL(cpufreq_get);


#ifdef CONFIG_SYSCTL


/*********************** cpufreq_sysctl interface ********************/
static int
cpufreq_procctl(ctl_table *ctl, int write, struct file *filp,
		void *buffer, size_t *lenp)
{
	char buf[16], *p;
	int cpu = (int) ctl->extra1;
	int len, left = *lenp;

	if (!left || (filp->f_pos && !write) || !cpu_online(cpu)) {
		*lenp = 0;
		return 0;
	}

	if (write) {
		unsigned int freq;

		len = left;
		if (left > sizeof(buf))
			left = sizeof(buf);
		if (copy_from_user(buf, buffer, left))
			return -EFAULT;
		buf[sizeof(buf) - 1] = '\0';

		freq = simple_strtoul(buf, &p, 0);
		cpufreq_set(freq, cpu);
	} else {
		len = sprintf(buf, "%d\n", cpufreq_get(cpu));
		if (len > left)
			len = left;
		if (copy_to_user(buffer, buf, len))
			return -EFAULT;
	}

	*lenp = len;
	filp->f_pos += len;
	return 0;
}

static int
cpufreq_sysctl(ctl_table *table, int *name, int nlen,
	       void *oldval, size_t *oldlenp,
	       void *newval, size_t newlen, void **context)
{
	int cpu = (int) table->extra1;

	if (!cpu_online(cpu))
		return -EINVAL;

	if (oldval && oldlenp) {
		size_t oldlen;

		if (get_user(oldlen, oldlenp))
			return -EFAULT;

		if (oldlen != sizeof(unsigned int))
			return -EINVAL;

		if (put_user(cpufreq_get(cpu), (unsigned int *)oldval) ||
		    put_user(sizeof(unsigned int), oldlenp))
			return -EFAULT;
	}
	if (newval && newlen) {
		unsigned int freq;

		if (newlen != sizeof(unsigned int))
			return -EINVAL;

		if (get_user(freq, (unsigned int *)newval))
			return -EFAULT;

		cpufreq_set(freq, cpu);
	}
	return 1;
}

/* ctl_table ctl_cpu_vars_{0,1,...,(NR_CPUS-1)} */
/* due to NR_CPUS tweaking, a lot of if/endifs are required, sorry */
        CTL_TABLE_CPU_VARS(0);
#if NR_CPUS > 1
	CTL_TABLE_CPU_VARS(1);
#endif
#if NR_CPUS > 2
	CTL_TABLE_CPU_VARS(2);
#endif
#if NR_CPUS > 3
	CTL_TABLE_CPU_VARS(3);
#endif
#if NR_CPUS > 4
	CTL_TABLE_CPU_VARS(4);
#endif
#if NR_CPUS > 5
	CTL_TABLE_CPU_VARS(5);
#endif
#if NR_CPUS > 6
	CTL_TABLE_CPU_VARS(6);
#endif
#if NR_CPUS > 7
	CTL_TABLE_CPU_VARS(7);
#endif
#if NR_CPUS > 8
	CTL_TABLE_CPU_VARS(8);
#endif
#if NR_CPUS > 9
	CTL_TABLE_CPU_VARS(9);
#endif
#if NR_CPUS > 10
	CTL_TABLE_CPU_VARS(10);
#endif
#if NR_CPUS > 11
	CTL_TABLE_CPU_VARS(11);
#endif
#if NR_CPUS > 12
	CTL_TABLE_CPU_VARS(12);
#endif
#if NR_CPUS > 13
	CTL_TABLE_CPU_VARS(13);
#endif
#if NR_CPUS > 14
	CTL_TABLE_CPU_VARS(14);
#endif
#if NR_CPUS > 15
	CTL_TABLE_CPU_VARS(15);
#endif
#if NR_CPUS > 16
	CTL_TABLE_CPU_VARS(16);
#endif
#if NR_CPUS > 17
	CTL_TABLE_CPU_VARS(17);
#endif
#if NR_CPUS > 18
	CTL_TABLE_CPU_VARS(18);
#endif
#if NR_CPUS > 19
	CTL_TABLE_CPU_VARS(19);
#endif
#if NR_CPUS > 20
	CTL_TABLE_CPU_VARS(20);
#endif
#if NR_CPUS > 21
	CTL_TABLE_CPU_VARS(21);
#endif
#if NR_CPUS > 22
	CTL_TABLE_CPU_VARS(22);
#endif
#if NR_CPUS > 23
	CTL_TABLE_CPU_VARS(23);
#endif
#if NR_CPUS > 24
	CTL_TABLE_CPU_VARS(24);
#endif
#if NR_CPUS > 25
	CTL_TABLE_CPU_VARS(25);
#endif
#if NR_CPUS > 26
	CTL_TABLE_CPU_VARS(26);
#endif
#if NR_CPUS > 27
	CTL_TABLE_CPU_VARS(27);
#endif
#if NR_CPUS > 28
	CTL_TABLE_CPU_VARS(28);
#endif
#if NR_CPUS > 29
	CTL_TABLE_CPU_VARS(29);
#endif
#if NR_CPUS > 30
	CTL_TABLE_CPU_VARS(30);
#endif
#if NR_CPUS > 31
	CTL_TABLE_CPU_VARS(31);
#endif
#if NR_CPUS > 32
#error please extend CPU enumeration
#endif

/* due to NR_CPUS tweaking, a lot of if/endifs are required, sorry */
static ctl_table ctl_cpu_table[NR_CPUS + 1] = {
	CPU_ENUM(0),
#if NR_CPUS > 1
	CPU_ENUM(1),
#endif
#if NR_CPUS > 2
	CPU_ENUM(2),
#endif
#if NR_CPUS > 3
	CPU_ENUM(3),
#endif
#if NR_CPUS > 4
	CPU_ENUM(4),
#endif
#if NR_CPUS > 5
	CPU_ENUM(5),
#endif
#if NR_CPUS > 6
	CPU_ENUM(6),
#endif
#if NR_CPUS > 7
	CPU_ENUM(7),
#endif
#if NR_CPUS > 8
	CPU_ENUM(8),
#endif
#if NR_CPUS > 9
	CPU_ENUM(9),
#endif
#if NR_CPUS > 10
	CPU_ENUM(10),
#endif
#if NR_CPUS > 11
	CPU_ENUM(11),
#endif
#if NR_CPUS > 12
	CPU_ENUM(12),
#endif
#if NR_CPUS > 13
	CPU_ENUM(13),
#endif
#if NR_CPUS > 14
	CPU_ENUM(14),
#endif
#if NR_CPUS > 15
	CPU_ENUM(15),
#endif
#if NR_CPUS > 16
	CPU_ENUM(16),
#endif
#if NR_CPUS > 17
	CPU_ENUM(17),
#endif
#if NR_CPUS > 18
	CPU_ENUM(18),
#endif
#if NR_CPUS > 19
	CPU_ENUM(19),
#endif
#if NR_CPUS > 20
	CPU_ENUM(20),
#endif
#if NR_CPUS > 21
	CPU_ENUM(21),
#endif
#if NR_CPUS > 22
	CPU_ENUM(22),
#endif
#if NR_CPUS > 23
	CPU_ENUM(23),
#endif
#if NR_CPUS > 24
	CPU_ENUM(24),
#endif
#if NR_CPUS > 25
	CPU_ENUM(25),
#endif
#if NR_CPUS > 26
	CPU_ENUM(26),
#endif
#if NR_CPUS > 27
	CPU_ENUM(27),
#endif
#if NR_CPUS > 28
	CPU_ENUM(28),
#endif
#if NR_CPUS > 29
	CPU_ENUM(29),
#endif
#if NR_CPUS > 30
	CPU_ENUM(30),
#endif
#if NR_CPUS > 31
	CPU_ENUM(31),
#endif
#if NR_CPUS > 32
#error please extend CPU enumeration
#endif
	{
		.ctl_name	= 0,
	}
};

static ctl_table ctl_cpu[2] = {
	{
		.ctl_name	= CTL_CPU,
		.procname	= "cpu",
		.mode		= 0555,
		.child		= ctl_cpu_table,
	},
	{
		.ctl_name	= 0,
	}
};

struct ctl_table_header *cpufreq_sysctl_table;

static inline void cpufreq_sysctl_init(void)
{
	cpufreq_sysctl_table = register_sysctl_table(ctl_cpu, 0);
}

static inline void cpufreq_sysctl_exit(void)
{
	unregister_sysctl_table(cpufreq_sysctl_table);
}

#else
#define cpufreq_sysctl_init()
#define cpufreq_sysctl_exit()
#endif /* CONFIG_SYSCTL */
#endif /* CONFIG_CPU_FREQ_24_API */



/*********************************************************************
 *                     NOTIFIER LISTS INTERFACE                      *
 *********************************************************************/

/**
 *	cpufreq_register_notifier - register a driver with cpufreq
 *	@nb: notifier function to register
 *      @list: CPUFREQ_TRANSITION_NOTIFIER or CPUFREQ_POLICY_NOTIFIER
 *
 *	Add a driver to one of two lists: either a list of drivers that 
 *      are notified about clock rate changes (once before and once after
 *      the transition), or a list of drivers that are notified about
 *      changes in cpufreq policy.
 *
 *	This function may sleep, and has the same return conditions as
 *	notifier_chain_register.
 */
int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list)
{
	int ret;

	down(&cpufreq_notifier_sem);
	switch (list) {
	case CPUFREQ_TRANSITION_NOTIFIER:
		ret = notifier_chain_register(&cpufreq_transition_notifier_list, nb);
		break;
	case CPUFREQ_POLICY_NOTIFIER:
		ret = notifier_chain_register(&cpufreq_policy_notifier_list, nb);
		break;
	default:
		ret = -EINVAL;
	}
	up(&cpufreq_notifier_sem);

	return ret;
}
EXPORT_SYMBOL(cpufreq_register_notifier);


/**
 *	cpufreq_unregister_notifier - unregister a driver with cpufreq
 *	@nb: notifier block to be unregistered
 *      @list: CPUFREQ_TRANSITION_NOTIFIER or CPUFREQ_POLICY_NOTIFIER
 *
 *	Remove a driver from the CPU frequency notifier list.
 *
 *	This function may sleep, and has the same return conditions as
 *	notifier_chain_unregister.
 */
int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list)
{
	int ret;

	down(&cpufreq_notifier_sem);
	switch (list) {
	case CPUFREQ_TRANSITION_NOTIFIER:
		ret = notifier_chain_unregister(&cpufreq_transition_notifier_list, nb);
		break;
	case CPUFREQ_POLICY_NOTIFIER:
		ret = notifier_chain_unregister(&cpufreq_policy_notifier_list, nb);
		break;
	default:
		ret = -EINVAL;
	}
	up(&cpufreq_notifier_sem);

	return ret;
}
EXPORT_SYMBOL(cpufreq_unregister_notifier);



/*********************************************************************
 *                          POLICY INTERFACE                         *
 *********************************************************************/

/**
 * cpufreq_get_policy - get the current cpufreq_policy
 * @policy: struct cpufreq_policy into which the current cpufreq_policy is written
 *
 * Reads the current cpufreq policy.
 */
int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu)
{
	down(&cpufreq_driver_sem);
	if (!cpufreq_driver  || !policy || 
	    (cpu >= NR_CPUS) || (!cpu_online(cpu))) {
		up(&cpufreq_driver_sem);
		return -EINVAL;
	}
	
	policy->min    = cpufreq_driver->policy[cpu].min;
	policy->max    = cpufreq_driver->policy[cpu].max;
	policy->policy = cpufreq_driver->policy[cpu].policy;
	policy->max_cpu_freq = cpufreq_driver->policy[cpu].max_cpu_freq;
	policy->cpu    = cpu;

	up(&cpufreq_driver_sem);

	return 0;
}
EXPORT_SYMBOL(cpufreq_get_policy);


/**
 *	cpufreq_set_policy - set a new CPUFreq policy
 *	@policy: policy to be set.
 *
 *	Sets a new CPU frequency and voltage scaling policy.
 */
int cpufreq_set_policy(struct cpufreq_policy *policy)
{
	unsigned int i;
	int ret;

	down(&cpufreq_driver_sem);
	if (!cpufreq_driver || !cpufreq_driver->verify || 
	    !cpufreq_driver->setpolicy || !policy ||
	    (policy->cpu > NR_CPUS)) {
		up(&cpufreq_driver_sem);
		return -EINVAL;
	}

	if (policy->cpu == CPUFREQ_ALL_CPUS)
		policy->max_cpu_freq = cpufreq_driver->policy[0].max_cpu_freq;
	else
		policy->max_cpu_freq = cpufreq_driver->policy[policy->cpu].max_cpu_freq;


	/* verify the cpu speed can be set within this limit */
	ret = cpufreq_driver->verify(policy);
	if (ret) {
		up(&cpufreq_driver_sem);
		return ret;
	}

	down(&cpufreq_notifier_sem);

	/* adjust if neccessary - all reasons */
	notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_ADJUST,
			    policy);

	/* adjust if neccessary - hardware incompatibility*/
	notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_INCOMPATIBLE,
			    policy);

	/* verify the cpu speed can be set within this limit,
	   which might be different to the first one */
	ret = cpufreq_driver->verify(policy);
	if (ret) {
		up(&cpufreq_notifier_sem);
		up(&cpufreq_driver_sem);
		return ret;
	}

	/* notification of the new policy */
	notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_NOTIFY,
			    policy);

	up(&cpufreq_notifier_sem);

	if (policy->cpu == CPUFREQ_ALL_CPUS) {
		for (i=0;i<NR_CPUS;i++) {
			cpufreq_driver->policy[i].min    = policy->min;
			cpufreq_driver->policy[i].max    = policy->max;
			cpufreq_driver->policy[i].policy = policy->policy;
		} 
	} else {
		cpufreq_driver->policy[policy->cpu].min    = policy->min;
		cpufreq_driver->policy[policy->cpu].max    = policy->max;
		cpufreq_driver->policy[policy->cpu].policy = policy->policy;
	}

#ifdef CONFIG_CPU_FREQ_24_API
	if (policy->cpu == CPUFREQ_ALL_CPUS) {
		for (i=0;i<NR_CPUS;i++)
			cpu_cur_freq[i] = policy->max;
	} else
		cpu_cur_freq[policy->cpu] = policy->max;
#endif

	ret = cpufreq_driver->setpolicy(policy);
	
	up(&cpufreq_driver_sem);

	return ret;
}
EXPORT_SYMBOL(cpufreq_set_policy);



/*********************************************************************
 *                    DYNAMIC CPUFREQ SWITCHING                      *
 *********************************************************************/
#ifdef CONFIG_CPU_FREQ_DYNAMIC
/* TBD */
#endif /* CONFIG_CPU_FREQ_DYNAMIC */



/*********************************************************************
 *            EXTERNALLY AFFECTING FREQUENCY CHANGES                 *
 *********************************************************************/

/**
 * adjust_jiffies - adjust the system "loops_per_jiffy"
 *
 * This function alters the system "loops_per_jiffy" for the clock
 * speed change. Note that loops_per_jiffy is only updated if all
 * CPUs are affected - else there is a need for per-CPU loops_per_jiffy
 * values which are provided by various architectures. 
 */
static inline void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
{
	if ((val == CPUFREQ_PRECHANGE  && ci->old < ci->new) ||
	    (val == CPUFREQ_POSTCHANGE && ci->old > ci->new))
		if (ci->cpu == CPUFREQ_ALL_CPUS)
			loops_per_jiffy = cpufreq_scale(loops_per_jiffy, ci->old, ci->new);
}


/**
 * cpufreq_notify_transition - call notifier chain and adjust_jiffies on frequency transition
 *
 * This function calls the transition notifiers and the "adjust_jiffies" function. It is called
 * twice on all CPU frequency changes that have external effects. 
 */
void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state)
{
	down(&cpufreq_notifier_sem);
	switch (state) {
	case CPUFREQ_PRECHANGE:
		notifier_call_chain(&cpufreq_transition_notifier_list, CPUFREQ_PRECHANGE, freqs);
		adjust_jiffies(CPUFREQ_PRECHANGE, freqs);		
		break;
	case CPUFREQ_POSTCHANGE:
		adjust_jiffies(CPUFREQ_POSTCHANGE, freqs);
		notifier_call_chain(&cpufreq_transition_notifier_list, CPUFREQ_POSTCHANGE, freqs);
#ifdef CONFIG_CPU_FREQ_24_API
		if (freqs->cpu == CPUFREQ_ALL_CPUS) {
			int i;
			for (i=0;i<NR_CPUS;i++)
				cpu_cur_freq[i] = freqs->new;
		} else
			cpu_cur_freq[freqs->cpu] = freqs->new;
#endif
		break;
	}
	up(&cpufreq_notifier_sem);
}
EXPORT_SYMBOL_GPL(cpufreq_notify_transition);



/*********************************************************************
 *               REGISTER / UNREGISTER CPUFREQ DRIVER                *
 *********************************************************************/

/**
 * cpufreq_register - register a CPU Frequency driver
 * @driver_data: A struct cpufreq_driver containing the values submitted by the CPU Frequency driver.
 *
 *   Registers a CPU Frequency driver to this core code. This code 
 * returns zero on success, -EBUSY when another driver got here first
 * (and isn't unregistered in the meantime). 
 *
 */
int cpufreq_register(struct cpufreq_driver *driver_data)
{
	unsigned int            ret;
	unsigned int            i;
	struct cpufreq_policy   policy;

	if (cpufreq_driver)
		return -EBUSY;
	
	if (!driver_data || !driver_data->verify || 
	    !driver_data->setpolicy)
		return -EINVAL;

	down(&cpufreq_driver_sem);
	cpufreq_driver        = driver_data;
	
	/* check for a default policy - if it exists, use it on _all_ CPUs*/
	for (i=0; i<NR_CPUS; i++)
	{
		if (default_policy.policy)
			cpufreq_driver->policy[i].policy = default_policy.policy;
		if (default_policy.min)
			cpufreq_driver->policy[i].min = default_policy.min;
		if (default_policy.max)
			cpufreq_driver->policy[i].max = default_policy.max;
	}

	/* set default policy on all CPUs. Must be called per-CPU and not
	 * with CPUFREQ_ALL_CPUs as there might be no common policy for all
	 * CPUs (UltraSPARC etc.)
	 */
	for (i=0; i<NR_CPUS; i++)
	{
		policy.policy = cpufreq_driver->policy[i].policy;
		policy.min    = cpufreq_driver->policy[i].min;
		policy.max    = cpufreq_driver->policy[i].max;
		policy.cpu    = i;
		up(&cpufreq_driver_sem);
		ret = cpufreq_set_policy(&policy);
		down(&cpufreq_driver_sem);
		if (ret) {
			cpufreq_driver = NULL;
			up(&cpufreq_driver_sem);
			return ret;
		}
	}

	up(&cpufreq_driver_sem);

	cpufreq_proc_init();

#ifdef CONFIG_CPU_FREQ_24_API
 	down(&cpufreq_driver_sem);
	for (i=0; i<NR_CPUS; i++) 
	{
		cpu_min_freq[i] = driver_data->cpu_min_freq[i];
		cpu_max_freq[i] = driver_data->policy[i].max_cpu_freq;
		cpu_cur_freq[i] = driver_data->cpu_cur_freq[i];
	}
	up(&cpufreq_driver_sem);

	cpufreq_sysctl_init();
#endif

	return 0;
}
EXPORT_SYMBOL_GPL(cpufreq_register);


/**
 * cpufreq_unregister - unregister the current CPUFreq driver
 *
 *    Unregister the current CPUFreq driver. Only call this if you have 
 * the right to do so, i.e. if you have succeeded in initialising before!
 * Returns zero if successful, and -EINVAL if the cpufreq_driver is
 * currently not initialised.
 */
int cpufreq_unregister(void)
{
	down(&cpufreq_driver_sem);

	if (!cpufreq_driver) {
		up(&cpufreq_driver_sem);
		return -EINVAL;
	}

	cpufreq_driver = NULL;

	up(&cpufreq_driver_sem);

	cpufreq_proc_exit();

#ifdef CONFIG_CPU_FREQ_24_API
	cpufreq_sysctl_exit();
#endif

	return 0;
}
EXPORT_SYMBOL_GPL(cpufreq_unregister);


#ifdef CONFIG_PM
/**
 *	cpufreq_restore - restore the CPU clock frequency after resume
 *
 *	Restore the CPU clock frequency so that our idea of the current
 *	frequency reflects the actual hardware.
 */
int cpufreq_restore(void)
{
	struct cpufreq_policy policy;
	unsigned int i;
	unsigned int ret = 0;

	if (in_interrupt())
		panic("cpufreq_restore() called from interrupt context!");

	for (i=0;i<NR_CPUS;i++) {
		if (!cpu_online(i))
			continue;

		down(&cpufreq_driver_sem);
		if (!cpufreq_driver) {
			up(&cpufreq_driver_sem);
			return 0;
		}
	
		policy.min    = cpufreq_driver->policy[i].min;
		policy.max    = cpufreq_driver->policy[i].max;
		policy.policy = cpufreq_driver->policy[i].policy;
		policy.cpu    = i;
		up(&cpufreq_driver_sem);

		ret += cpufreq_set_policy(&policy);
	}

	return ret;
}
EXPORT_SYMBOL_GPL(cpufreq_restore);
#else
#define cpufreq_restore()
#endif /* CONFIG_PM */


Lines 48-53 Link Here

(-)linux-2.4.22/kernel/panic.c (+4 lines)
48	#if defined(CONFIG_ARCH_S390)	48	#if defined(CONFIG_ARCH_S390)
49	unsigned long caller = (unsigned long) __builtin_return_address(0);	49	unsigned long caller = (unsigned long) __builtin_return_address(0);
50	#endif	50	#endif
		51	#ifdef CONFIG_BOOTX_TEXT
		52	extern int force_printk_to_btext;
		53	force_printk_to_btext = 1;
		54	#endif
51		55
52	bust_spinlocks(1);	56	bust_spinlocks(1);
53	va_start(args, fmt);	57	va_start(args, fmt);

Lines 26-32 Link Here

(-)linux-2.4.22/kernel/printk.c (-2 / +10 lines)
26	#include <linux/module.h>	26	#include <linux/module.h>
27	#include <linux/interrupt.h> /* For in_interrupt() */	27	#include <linux/interrupt.h> /* For in_interrupt() */
28	#include <linux/config.h>	28	#include <linux/config.h>
29		29	#ifdef CONFIG_BOOTX_TEXT
		30	#include <asm/btext.h>
		31	#endif
30	#include <asm/uaccess.h>	32	#include <asm/uaccess.h>
31		33
32	#if defined(CONFIG_MULTIQUAD) \|\| defined(CONFIG_IA64)	34	#if defined(CONFIG_MULTIQUAD) \|\| defined(CONFIG_IA64)
Lines 412-417 Link Here
412	char *p;	414	char *p;
413	static char printk_buf[1024];	415	static char printk_buf[1024];
414	static int log_level_unknown = 1;	416	static int log_level_unknown = 1;
		417	#ifdef CONFIG_BOOTX_TEXT
		418	extern int force_printk_to_btext;
		419	#endif
415		420
416	if (oops_in_progress) {	421	if (oops_in_progress) {
417	/* If a crash is occurring, make sure we can't deadlock */	422	/* If a crash is occurring, make sure we can't deadlock */
Lines 427-433 Link Here
427	va_start(args, fmt);	432	va_start(args, fmt);
428	printed_len = vsnprintf(printk_buf, sizeof(printk_buf), fmt, args);	433	printed_len = vsnprintf(printk_buf, sizeof(printk_buf), fmt, args);
429	va_end(args);	434	va_end(args);
430		435	#ifdef CONFIG_BOOTX_TEXT
		436	if (force_printk_to_btext)
		437	btext_drawstring(printk_buf);
		438	#endif /* CONFIG_BOOTX_TEXT */
431	/*	439	/*
432	* Copy the output into log_buf. If the caller didn't provide	440	* Copy the output into log_buf. If the caller didn't provide
433	* appropriate log level tags, we insert them here	441	* appropriate log level tags, we insert them here

Lines 118-123 Link Here

(-)linux-2.4.22/kernel/resource.c (+5 lines)
118	write_lock(&resource_lock);	118	write_lock(&resource_lock);
119	conflict = __request_resource(root, new);	119	conflict = __request_resource(root, new);
120	write_unlock(&resource_lock);	120	write_unlock(&resource_lock);
		121	if (conflict) {
		122	printk("resource conflict with: %lx..%lx (%lx), name: %s\n",
		123	conflict->start, conflict->end, conflict->flags,
		124	conflict->name ? conflict->name : "<NULL>");
		125	}
121	return conflict ? -EBUSY : 0;	126	return conflict ? -EBUSY : 0;
122	}	127	}
123		128

Lines 51-56 Link Here

(-)linux-2.4.22/kernel/sysctl.c (+8 lines)
51	extern int core_uses_pid;	51	extern int core_uses_pid;
52	extern char core_pattern[];	52	extern char core_pattern[];
53	extern int cad_pid;	53	extern int cad_pid;
		54	extern int laptop_mode;
		55	extern int block_dump;
54		56
55	/* this is needed for the proc_dointvec_minmax for [fs_]overflow UID and GID */	57	/* this is needed for the proc_dointvec_minmax for [fs_]overflow UID and GID */
56	static int maxolduid = 65535;	58	static int maxolduid = 65535;
Lines 284-295 Link Here
284	&pgt_cache_water, 2*sizeof(int), 0644, NULL, &proc_dointvec},	286	&pgt_cache_water, 2*sizeof(int), 0644, NULL, &proc_dointvec},
285	{VM_PAGE_CLUSTER, "page-cluster",	287	{VM_PAGE_CLUSTER, "page-cluster",
286	&page_cluster, sizeof(int), 0644, NULL, &proc_dointvec},	288	&page_cluster, sizeof(int), 0644, NULL, &proc_dointvec},
		289	{VM_HEAP_STACK_GAP, "heap-stack-gap",
		290	&heap_stack_gap, sizeof(int), 0644, NULL, &proc_dointvec},
287	{VM_MIN_READAHEAD, "min-readahead",	291	{VM_MIN_READAHEAD, "min-readahead",
288	&vm_min_readahead,sizeof(int), 0644, NULL, &proc_dointvec},	292	&vm_min_readahead,sizeof(int), 0644, NULL, &proc_dointvec},
289	{VM_MAX_READAHEAD, "max-readahead",	293	{VM_MAX_READAHEAD, "max-readahead",
290	&vm_max_readahead,sizeof(int), 0644, NULL, &proc_dointvec},	294	&vm_max_readahead,sizeof(int), 0644, NULL, &proc_dointvec},
291	{VM_MAX_MAP_COUNT, "max_map_count",	295	{VM_MAX_MAP_COUNT, "max_map_count",
292	&max_map_count, sizeof(int), 0644, NULL, &proc_dointvec},	296	&max_map_count, sizeof(int), 0644, NULL, &proc_dointvec},
		297	{VM_LAPTOP_MODE, "laptop_mode",
		298	&laptop_mode, sizeof(int), 0644, NULL, &proc_dointvec},
		299	{VM_BLOCK_DUMP, "block_dump",
		300	&block_dump, sizeof(int), 0644, NULL, &proc_dointvec},
293	{0}	301	{0}
294	};	302	};
295		303

Lines 165-170 Link Here

(-)linux-2.4.22/mm/filemap.c (+2 lines)
165		165
166	if (mapping && mapping->host)	166	if (mapping && mapping->host)
167	mark_inode_dirty_pages(mapping->host);	167	mark_inode_dirty_pages(mapping->host);
		168	if (block_dump)
		169	printk("%s: dirtied page\n", current->comm);
168	}	170	}
169	}	171	}
170	}	172	}

Lines 45-50 Link Here

(-)linux-2.4.22/mm/mmap.c (-3 / +11 lines)
45	};	45	};
46		46
47	int sysctl_overcommit_memory;	47	int sysctl_overcommit_memory;
		48	int heap_stack_gap = 1;
48	int max_map_count = DEFAULT_MAX_MAP_COUNT;	49	int max_map_count = DEFAULT_MAX_MAP_COUNT;
49		50
50	/* Check that a process has enough memory to allocate a	51	/* Check that a process has enough memory to allocate a
Lines 630-638 Link Here
630		631
631	for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {	632	for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
632	/* At this point: (!vma \|\| addr < vma->vm_end). */	633	/* At this point: (!vma \|\| addr < vma->vm_end). */
		634	unsigned long __heap_stack_gap;
633	if (TASK_SIZE - len < addr)	635	if (TASK_SIZE - len < addr)
634	return -ENOMEM;	636	return -ENOMEM;
635	if (!vma \|\| addr + len <= vma->vm_start)	637	if (!vma)
		638	return addr;
		639	__heap_stack_gap = 0;
		640	if (vma->vm_flags & VM_GROWSDOWN)
		641	__heap_stack_gap = heap_stack_gap << PAGE_SHIFT;
		642	if (addr + len + __heap_stack_gap <= vma->vm_start)
636	return addr;	643	return addr;
637	addr = vma->vm_end;	644	addr = vma->vm_end;
638	}	645	}
Lines 741-747 Link Here
741		748
742	struct vm_area_struct * find_extend_vma(struct mm_struct * mm, unsigned long addr)	749	struct vm_area_struct * find_extend_vma(struct mm_struct * mm, unsigned long addr)
743	{	750	{
744	struct vm_area_struct * vma;	751	struct vm_area_struct * vma, * prev_vma;
745	unsigned long start;	752	unsigned long start;
746		753
747	addr &= PAGE_MASK;	754	addr &= PAGE_MASK;
Lines 753-759 Link Here
753	if (!(vma->vm_flags & VM_GROWSDOWN))	760	if (!(vma->vm_flags & VM_GROWSDOWN))
754	return NULL;	761	return NULL;
755	start = vma->vm_start;	762	start = vma->vm_start;
756	if (expand_stack(vma, addr))	763	find_vma_prev(mm, addr, &prev_vma);
		764	if (expand_stack(vma, addr, prev_vma))
757	return NULL;	765	return NULL;
758	if (vma->vm_flags & VM_LOCKED) {	766	if (vma->vm_flags & VM_LOCKED) {
759	make_pages_present(addr, start);	767	make_pages_present(addr, start);

Return to bug 35819

Lines 27170-27175 Link Here

(-)linux-2.4.22/Documentation/Configure.help (+23 lines)
27170		27170
27171	If unsure, say N.	27171	If unsure, say N.
27172		27172
		27173	CONFIG_CPU_FREQ
		27174	Clock scaling allows you to change the clock speed of CPUs on the
		27175	fly. This is a nice method to save battery power on notebooks,
		27176	because the lower the clock speed, the less power the CPU consumes.
		27177
		27178	For more information, take a look at linux/Documentation/cpufreq or
		27179	at <http://www.brodo.de/cpufreq/>
		27180
		27181	If in doubt, say N.
		27182
		27183	CONFIG_CPU_FREQ_24_API
		27184	This enables the /proc/sys/cpu/ sysctl interface for controlling
		27185	CPUFreq, as known from the 2.4.-kernel patches for CPUFreq. Note
		27186	that some drivers do not support this interface or offer less
		27187	functionality.
		27188
		27189	If you say N here, you'll be able to control CPUFreq using the
		27190	new /proc/cpufreq interface.
		27191
		27192	For details, take a look at linux/Documentation/cpufreq.
		27193
		27194	If in doubt, say N.
		27195
27173	NatSemi SCx200 support	27196	NatSemi SCx200 support
27174	CONFIG_SCx200	27197	CONFIG_SCx200
27175	This provides basic support for the National Semiconductor SCx200	27198	This provides basic support for the National Semiconductor SCx200

Line 0 Link Here

(-)linux-2.4.22/Documentation/cpufreq (+361 lines)
		1	CPU frequency and voltage scaling code in the Linux(TM) kernel
		2
		3
		4	L i n u x C P U F r e q
		5
		6
		7
		8
		9	Dominik Brodowski <linux@brodo.de>
		10	David Kimdon <dwhedon@debian.org>
		11
		12
		13
		14	Clock scaling allows you to change the clock speed of the CPUs on the
		15	fly. This is a nice method to save battery power, because the lower
		16	the clock speed, the less power the CPU consumes.
		17
		18
		19
		20	Contents:
		21	---------
		22	1. Supported architectures
		23	2. User interface
		24	2.1 /proc/cpufreq interface [2.6]
		25	2.2. /proc/sys/cpu/ interface [2.4]
		26	3. CPUFreq core and interfaces
		27	3.1 General information
		28	3.2 CPUFreq notifiers
		29	3.3 CPUFreq architecture drivers
		30	4. Mailing list and Links
		31
		32
		33
		34	1. Supported architectures
		35	==========================
		36
		37	ARM:
		38	ARM Integrator, SA 1100, SA1110
		39	--------------------------------
		40	This driver will be ported to new CPUFreq core soon, so
		41	far it will not work.
		42
		43
		44	AMD Elan:
		45	SC400, SC410
		46	--------------------------------
		47	You need to specify the highest allowed CPU frequency as
		48	a module parameter ("max_freq") or as boot parameter
		49	("elanfreq="). Else the available speed range will be
		50	limited to the speed at which the CPU runs while this
		51	module is loaded.
		52
		53
		54	VIA Cyrix Longhaul:
		55	VIA Samuel/CyrixIII, VIA Cyrix Samuel/C3,
		56	VIA Cyrix Ezra, VIA Cyrix Ezra-T
		57	--------------------------------
		58	If you do not want to scale the Front Side Bus or voltage,
		59	pass the module parameter "dont_scale_fsb 1" or
		60	"dont_scale_voltage 1". Additionally, it is advised that
		61	you pass the current Front Side Bus speed (in MHz) to
		62	this module as module parameter "current_fsb", e.g.
		63	"current_fsb 133" for a Front Side Bus speed of 133 MHz.
		64
65
66	Intel SpeedStep:
67	certain mobile Intel Pentium III (Coppermine), and all mobile
68	Intel Pentium III-M (Tualatin) and mobile Intel Pentium 4 P4-Ms.
69	--------------------------------
70	Unfortunately only modern Intel ICH2-M and ICH3-M chipsets are
71	supported.
72
73
74	P4 CPU Clock Modulation:
75	Intel Pentium 4 Xeon processors
76	---------------------------------
77	Note that you can only switch the speed of two logical CPUs at
78	once - but each phyiscal CPU may have different throttling levels.
79
80
81	PowerNow! K6:
82	mobile AMD K6-2+ / mobile K6-3+:
83	--------------------------------
84	No known issues.
85
86
87	Transmeta Crusoe Longrun:
88	Transmeta Crusoe processors:
89	--------------------------------
90	Does not work with the 2.4. /proc/sys/cpu/ interface.
91
92
93
94	2. User Interface
95	=================
96
97	2.1 /proc/cpufreq interface [2.6]
98	***********************************
99
100	Starting in the patches for kernel 2.5.33, CPUFreq uses a "policy"
101	interface /proc/cpufreq.
102
103	When you "cat" this file, you'll find something like:
104
105	--
106	minimum CPU frequency - maximum CPU frequency - policy
107	CPU 0 1200000 ( 75%) - 1600000 (100%) - performance
108	--
109
110	This means the current policy allows this CPU to be run anywhere
111	between 1.2 GHz (the value is in kHz) and 1.6 GHz with an eye towards
112	performance.
113
114	To change the policy, "echo" the desired new policy into
115	/proc/cpufreq. Use one of the following formats:
116
117	cpu_nr:min_freq:max_freq:policy
118	cpu_nr%min_freq%max_freq%policy
119	min_freq:max_freq:policy
120	min_freq%max_freq%policy
121
122	with cpu_nr being the CPU which shall be affected, min_freq and
123	max_freq the lower and upper limit of the CPU core frequency in kHz,
124	and policy either "performance" or "powersave".
125	A few examples:
126
127	root@notebook:#echo -n "0:0:0:powersave" > /proc/cpufreq
128	sets the CPU #0 to the lowest supported frequency.
129
130	root@notebook:#echo -n "1%100%100%performance" > /proc/cpufreq
131	sets the CPU #1 to the highest supported frequency.
132
133	root@notebook:#echo -n "1000000:2000000:performance" > /proc/cpufreq
134	to set the frequency of all CPUs between 1 GHz and 2 GHz and to
135	the policy "performance".
136
137	Please note that the values you "echo" into /proc/cpufreq are
138	validated first, and may be limited by hardware or thermal
139	considerations. Because of this, a read from /proc/cpufreq might
140	differ from what was written into it.
141
142
143	When you read /proc/cpufreq for the first time after a CPUFreq driver
144	has been initialized, you'll see the "default policy" for this
145	driver. If this does not suit your needs, you can pass a boot
146	parameter to the cpufreq core. Use the following syntax for this:
147	"cpufreq=min_freq:max_freq:policy", i.e. you may not chose a
148	specific CPU and you need to specify the limits in kHz and not in
149	per cent.
150
151
152	2.2 /proc/cpufreq interface [2.4]
153	***********************************
154
155	Previsiously (and still available as a config option), CPUFreq used
156	a "sysctl" interface which is located in
157	/proc/sys/cpu/0/
158	/proc/sys/cpu/1/ ... (SMP only)
159
160	In these directories, you will find three files of importance for
161	CPUFreq: speed-max, speed-min and speed:
162
163	speed shows the current CPU frequency in kHz,
164	speed-min the minimum supported CPU frequency, and
165	speed-max the maximum supported CPU frequency.
166
167
168	To change the CPU frequency, "echo" the desired CPU frequency (in kHz)
169	to speed. For example, to set the CPU speed to the lowest/highest
170	allowed frequency do:
171
172	root@notebook:# cat /proc/sys/cpu/0/speed-min > /proc/sys/cpu/0/speed
173	root@notebook:# cat /proc/sys/cpu/0/speed-max > /proc/sys/cpu/0/speed
174
175
176
177	3. CPUFreq core and interfaces
178	===============================
179
180	3.1 General information
181	*************************
182
183	The CPUFreq core code is located in linux/kernel/cpufreq.c. This
184	cpufreq code offers a standardized interface for the CPUFreq
185	architecture drivers (those pieces of code that do actual
186	frequency transitions), as well as to "notifiers". These are device
187	drivers or other part of the kernel that need to be informed of
188	policy changes (like thermal modules like ACPI) or of all
189	frequency changes (like timing code) or even need to force certain
190	speed limits (like LCD drivers on ARM architecture). Additionally, the
191	kernel "constant" loops_per_jiffy is updated on frequency changes
192	here.
193
194
195	3.2 CPUFreq notifiers
196	***********************
197
198	CPUFreq notifiers conform to the standard kernel notifier interface.
199	See linux/include/linux/notifier.h for details on notifiers.
200
201	There are two different CPUFreq notifiers - policy notifiers and
202	transition notifiers.
203
204
205	3.2.1 CPUFreq policy notifiers
206	******************************
207
208	These are notified when a new policy is intended to be set. Each
209	CPUFreq policy notifier is called three times for a policy transition:
210
211	1.) During CPUFREQ_ADJUST all CPUFreq notifiers may change the limit if
212	they see a need for this - may it be thermal considerations or
213	hardware limitations.
214
215	2.) During CPUFREQ_INCOMPATIBLE only changes may be done in order to avoid
216	hardware failure.
217
218	3.) And during CPUFREQ_NOTIFY all notifiers are informed of the new policy
219	- if two hardware drivers failed to agree on a new policy before this
220	stage, the incompatible hardware shall be shut down, and the user
221	informed of this.
222
223	The phase is specified in the second argument to the notifier.
224
225	The third argument, a void *pointer, points to a struct cpufreq_policy
226	consisting of five values: cpu, min, max, policy and max_cpu_freq. Min
227	and max are the lower and upper frequencies (in kHz) of the new
228	policy, policy the new policy, cpu the number of the affected CPU or
229	CPUFREQ_ALL_CPUS for all CPUs; and max_cpu_freq the maximum supported
230	CPU frequency. This value is given for informational purposes only.
231
232
233	3.2.2 CPUFreq transition notifiers
234	**********************************
235
236	These are notified twice when the CPUfreq driver switches the CPU core
237	frequency and this change has any external implications.
238
239	The second argument specifies the phase - CPUFREQ_PRECHANGE or
240	CPUFREQ_POSTCHANGE.
241
242	The third argument is a struct cpufreq_freqs with the following
243	values:
244	cpu - number of the affected CPU or CPUFREQ_ALL_CPUS
245	old - old frequency
246	new - new frequency
247
248
249	3.3 CPUFreq architecture drivers
250	**********************************
251
252	CPUFreq architecture drivers are the pieces of kernel code that
253	actually perform CPU frequency transitions. These need to be
254	initialized separately (separate initcalls), and may be
255	modularized. They interact with the CPUFreq core in the following way:
256
257	cpufreq_register()
258	------------------
259	cpufreq_register registers an arch driver to the CPUFreq core. Please
260	note that only one arch driver may be registered at any time. -EBUSY
261	is returned when an arch driver is already registered. The argument to
262	cpufreq_register, struct cpufreq_driver *driver, is described later.
263
264	cpufreq_unregister()
265	--------------------
266	cpufreq_unregister unregisters an arch driver, e.g. on module
267	unloading. Please note that there is no check done that this is called
268	from the driver which actually registered itself to the core, so
269	please only call this function when you are sure the arch driver got
270	registered correctly before.
271
272	cpufreq_notify_transition()
273	---------------------------
274	On "dumb" hardware where only fixed frequency can be set, the driver
275	must call cpufreq_notify_transition() once before, and once after the
276	actual transition.
277
278	struct cpufreq_driver
279	---------------------
280	On initialization, the arch driver is supposed to pass a pointer
281	to a struct cpufreq_driver *cpufreq_driver consisting of the following
282	entries:
283
284	cpufreq_verify_t verify: This is a pointer to a function with the
285	following definition:
286	void verify_function (struct cpufreq_policy *policy).
287	This function must verify the new policy is within the limits
288	supported by the CPU, and at least one supported CPU is within
289	this range. It may be useful to use cpufreq.h /
290	cpufreq_verify_within_limits for this.
291
292	cpufreq_setpolicy_t setpolicy: This is a pointer to a function with
293	the following definition:
294	void setpolicy_function (struct cpufreq_policy *policy).
295	This function must set the CPU to the new policy. If it is a
296	"dumb" CPU which only allows fixed frequencies to be set, it
297	shall set it to the lowest within the limit for
298	CPUFREQ_POLICY_POWERSAVE, and to the highest for
299	CPUFREQ_POLICY_PERFORMANCE. Once CONFIG_CPU_FREQ_DYNAMIC is
300	implemented, it can use a dynamic method to adjust the speed
301	between the lower and upper limit.
302
303	struct cpufreq_policy *policy: This is an array of NR_CPUS struct
304	cpufreq_policies, containing the current policies set for these
305	CPUs. Note that policy[0].max_cpu_freq must contain the
306	absolute maximum CPU frequency supported by _all_ CPUs.
307
308	In case the driver is expected to run with the 2.4.-style API
309	(/proc/sys/cpu/.../), two more values must be passed
310	#ifdef CONFIG_CPU_FREQ_24_API
311	unsigned int cpu_min_freq;
312	unsigned int cpu_cur_freq[NR_CPUS];
313	#endif
314	with cpu_min_freq being the minimum CPU frequency supported by
315	the CPUs; and the entries in cpu_cur_freq reflecting the
316	current speed of the appropriate CPU.
317
318	Some Requirements to CPUFreq architecture drivers
319	-------------------------------------------------
320	* Only call cpufreq_register() when the ability to switch CPU
321	frequencies is _verified_ or can't be missing
322	* cpufreq_unregister() may only be called if cpufreq_register() has
323	been successfully(!) called before.
324	* kfree() the struct cpufreq_driver only after the call to
325	cpufreq_unregister(), unless cpufreq_register() failed.
326	* Be aware that there is currently no error management in the
327	setpolicy() code in the CPUFreq core. So only call yourself a
328	cpufreq_driver if you are really a working cpufreq_driver!
329
330
331
332	4. Mailing list and Links
333	*************************
334
335
336	Mailing List
337	------------
338	There is a CPU frequency changing CVS commit and general list where
339	you can report bugs, problems or submit patches. To post a message,
340	send an email to cpufreq@www.linux.org.uk, to subscribe go to
341	http://www.linux.org.uk/mailman/listinfo/cpufreq. Previous post to the
342	mailing list are available to subscribers at
343	http://www.linux.org.uk/mailman/private/cpufreq/.
344
345
346	Links
347	-----
348	the FTP archives:
349	* ftp://ftp.linux.org.uk/pub/linux/cpufreq/
350
351	how to access the CVS repository:
352	* http://cvs.arm.linux.org.uk/
353
354	the CPUFreq Mailing list:
355	* http://www.linux.org.uk/mailman/listinfo/cpufreq
356
357	Clock and voltage scaling for the SA-1100:
358	* http://www.lart.tudelft.nl/projects/scaling
359
360	CPUFreq project homepage
361	* http://www.brodo.de/cpufreq/

Line 0 Link Here

(-)linux-2.4.22/Documentation/laptop-mode.sh (+42 lines)
	1	#!/bin/sh
	2	#
	3	# start of stop laptop mode, best run by a power management daemon when
	4	# ac gets connected/disconnected from a laptop
	5	#
	6	# FIXME: assumes HZ == 100
	7
	8	# age time, in seconds. should be put into a sysconfig file
	9	MAX_AGE=600
	10
	11	# kernel default dirty buffer age
	12	DEF_AGE=30
	13	DEF_UPDATE=5
	14
	15	if [ ! -w /proc/sys/vm/laptop_mode ]; then
	16	echo "Kernel is not patched with laptop_mode patch"
	17	exit 1
	18	fi
	19
	20	case "$1" in
	21	start)
	22	AGE=$((100*$MAX_AGE))
	23	echo -n "Starting laptop mode"
	24	echo "1" > /proc/sys/vm/laptop_mode
	25	echo "30 500 0 0 $AGE $AGE 60 20 0" > /proc/sys/vm/bdflush
	26	echo "."
	27	;;
	28	stop)
	29	U_AGE=$((100*$DEF_UPDATE))
	30	B_AGE=$((100*$DEF_AGE))
	31	echo -n "Stopping laptop mode"
	32	echo "0" > /proc/sys/vm/laptop_mode
	33	echo "30 500 0 0 $U_AGE $B_AGE 60 20 0" > /proc/sys/vm/bdflush
	34	echo "."
	35	;;
	36	*)
	37	echo "$0 {start\|stop}"
	38	;;
	39
	40	esac
	41
	42	exit 0

Line 0 Link Here

(-)linux-2.4.22/Documentation/laptop-mode.txt (+72 lines)
		1	Laptop mode
		2	===========
		3
		4	This small doc describes the 2.4 laptop mode patch.
		5
		6	Last updated 2003-05-25, Jens Axboe <axboe@suse.de>
		7
		8	Introduction
		9	------------
		10
		11	A few properties of the Linux vm makes it virtually impossible to attempt
		12	to spin down the hard drive in a laptop for a longer period of time (more
		13	than a handful of seconds). This means you are lucky if you can even reach
		14	the break even point with regards to power consumption, let alone expect any
		15	decrease.
		16
		17	One problem is the age time of dirty buffers. Linux uses 30 seconds per
		18	default, so if you dirty any data then flusing of that data will commence
		19	at most 30 seconds from then. Another is the journal commit interval of
		20	journalled file systems such as ext3, which is 5 seconds on a stock kernel.
		21	Both of these are tweakable either from proc/sysctl or as mount options
		22	though, and thus partly solvable from user space.
		23
		24	The kernel update daemon (kupdated) also runs at specific intervals, flushing
		25	old dirty data out. Default is every 5 seconds, this too can be tweaked
		26	from sysctl.
		27
		28	So what does the laptop mode patch do? It attempts to fully utilize the
		29	hard drive once it has been spun up, flushing the old dirty data out to
		30	disk. Instead of flushing just the expired data, it will clean everything.
		31	When a read causes the disk to spin up, we kick off this flushing after
		32	a few seconds. This means that once the disk spins down again, everything
		33	is up to date. That allows longer dirty data and journal expire times.
		34
		35	It follows that you have to set long expire times to get long spin downs.
		36	This means you could potentially loose 10 minutes worth of data, if you
		37	set a 10 minute expire count instead of just 30 seconds worth. The biggest
		38	risk here is undoubtedly running out of battery.
		39
		40	Settings
		41	--------
		42
		43	The main knob is /proc/sys/vm/laptop mode. Setting that to 1 switches the
		44	vm (and block layer) to laptop mode. Leaving it to 0 makes the kernel work
		45	like before. When in laptop mode, you also want to extend the intervals
		46	desribed above. See the laptop-mode.sh script for how to do that.
		47
		48	It can happen that the disk still keeps spinning up and you don't quite
		49	know why or what causes it. The laptop mode patch has a little helper for
		50	that as well, /proc/sys/vm/block-dump. When set to 1, it will dump info to
		51	the kernel message buffer about what process caused the io. Be very careful
		52	when playing with this setting, it is advisable to shut down syslog first!
		53
		54	Result
		55	------
		56
		57	Using the laptop-mode.sh script with its default settings, I get the full
		58	10 minutes worth of drive spin down. Provided your work load is cached,
		59	the disk will only spin up every 10 minutes (well actually, 9 minutes and 55
		60	seconds due to the 5 second delay in flushing dirty data after the last read
		61	completes). I can't tell you exactly how much extra battery life you will
		62	gain in laptop mode, it will vary greatly on the laptop and workload in
		63	question. The only way to know for sure is to try it out. Getting 10% extra
		64	battery life is not unrealistic.
65
66	Notes
67	-----
68
69	Patch only changes journal expire time for ext3. reiserfs uses a hardwire
70	value, should be trivial to adapt though (basically just make it call
71	get_buffer_flushtime() and uses that). I have not looked at other
72	journalling file systems, I'll happily accept patches to rectify that!

Line 0 Link Here

(-)linux-2.4.22/README.BENH (+23 lines)
	1	Welcome to my PowerMac tree.
	2
	3	In addition to the standard feature set of kernel.org's 2.4.22, this
	4	tree includes small fixes that didn't make it into 2.4.21, including all
	5	of what was present as of 2.4.21-ben3. Some of the major additions are:
	6
	7	- Laptop mode patch (Jens Axboe). See Documentation/laptop_mode.sh script
	8	- Andrea Arcangeli's silent-stack-overflow patch
	9	- CPU Frequency switching support on some laptops
	10	- Support for UniNorth AGP in the agpgart driver (though it's strongly
	11	recommended that you use Michel's Danzer DRM module for that to work
	12	properly)
	13	- Support for blinking the laptop LED on internal HD activity
	14	(Jens and me)
	15	- Improved support for lba48 capable disks (Jens Axboe)
	16	- Updated rivafb with support for more cards & eMac
	17	- Updated sungem driver, supports more chips & recent PHYs
	18	- Updated dmasound driver to support tumbler & snapper
	19	- Add reporting of OF device path of IDE interfaces in /proc/ide
	20	- Fixes for CompactFlash cards
	21	- Fixes to vmlinux.coff oldworld wrapper
	22	- Better TB sync code for 2 CPU machines from Samuel Rydth
	23

Lines 32-38 Link Here

(-)linux-2.4.22/arch/i386/mm/fault.c (-4 / +6 lines)
32	*/	32	*/
33	int __verify_write(const void * addr, unsigned long size)	33	int __verify_write(const void * addr, unsigned long size)
34	{	34	{
35	struct vm_area_struct * vma;	35	struct vm_area_struct * vma, * prev_vma;
36	unsigned long start = (unsigned long) addr;	36	unsigned long start = (unsigned long) addr;
37		37
38	if (!size)	38	if (!size)
Lines 78-84 Link Here
78	check_stack:	78	check_stack:
79	if (!(vma->vm_flags & VM_GROWSDOWN))	79	if (!(vma->vm_flags & VM_GROWSDOWN))
80	goto bad_area;	80	goto bad_area;
81	if (expand_stack(vma, start) == 0)	81	find_vma_prev(current->mm, start, &prev_vma);
		82	if (expand_stack(vma, start, prev_vma) == 0)
82	goto good_area;	83	goto good_area;
83		84
84	bad_area:	85	bad_area:
Lines 141-147 Link Here
141	{	142	{
142	struct task_struct *tsk;	143	struct task_struct *tsk;
143	struct mm_struct *mm;	144	struct mm_struct *mm;
144	struct vm_area_struct * vma;	145	struct vm_area_struct * vma, * prev_vma;
145	unsigned long address;	146	unsigned long address;
146	unsigned long page;	147	unsigned long page;
147	unsigned long fixup;	148	unsigned long fixup;
Lines 202-208 Link Here
202	if (address + 32 < regs->esp)	203	if (address + 32 < regs->esp)
203	goto bad_area;	204	goto bad_area;
204	}	205	}
205	if (expand_stack(vma, address))	206	find_vma_prev(mm, address, &prev_vma);
		207	if (expand_stack(vma, address, prev_vma))
206	goto bad_area;	208	goto bad_area;
207	/*	209	/*
208	* Ok, we have a good vm_area for this memory access, so	210	* Ok, we have a good vm_area for this memory access, so

Lines 18-23 Link Here

(-)linux-2.4.22/arch/ppc/boot/pmac/coffmain.c (-14 / +20 lines)
18	extern char _start, _end;	18	extern char _start, _end;
19		19
20	extern char *claim(unsigned, unsigned, unsigned);	20	extern char *claim(unsigned, unsigned, unsigned);
		21	extern int map(unsigned, unsigned, unsigned);
21	extern char image_data[], initrd_data[];	22	extern char image_data[], initrd_data[];
22	extern int initrd_len, image_len;	23	extern int initrd_len, image_len;
23	extern int getprop(void , const char , void *, int);	24	extern int getprop(void , const char , void *, int);
Lines 34-49 Link Here
34	char begin_avail, end_avail;	35	char begin_avail, end_avail;
35	char *avail_high;	36	char *avail_high;
36		37
37	#define RAM_START 0
38	#define RAM_END (RAM_START + 0x800000) /* only 8M mapped with BATs */
39
40	#define PROG_START RAM_START
41	#define PROG_SIZE 0x00400000
42
43	#define SCRATCH_SIZE (128 << 10)	38	#define SCRATCH_SIZE (128 << 10)
44		39
45	static char heap[SCRATCH_SIZE];	40	static char heap[SCRATCH_SIZE];
46		41
		42	//static unsigned long ram_start = 0;
		43	//static unsigned long ram_end = 0x800000;
		44	//static unsigned long prog_start = 0;
		45	//static unsigned long prog_size = 0x380000;
		46
		47	static unsigned long ram_start = 0;
		48	static unsigned long ram_end = 0x1000000;
		49	static unsigned long prog_start = 0x800000;
		50	static unsigned long prog_size = 0x800000;
47	typedef void (kernel_start_t)(int, int, void );	51	typedef void (kernel_start_t)(int, int, void );
48		52
49	void boot(int a1, int a2, void *prom)	53	void boot(int a1, int a2, void *prom)
Lines 54-85 Link Here
54	unsigned initrd_start, initrd_size;	58	unsigned initrd_start, initrd_size;
55		59
56	printf("coffboot starting: loaded at 0x%p\n", &_start);	60	printf("coffboot starting: loaded at 0x%p\n", &_start);
57	setup_bats(RAM_START);	61	setup_bats(ram_start);
58		62
59	initrd_size = (char )(&__ramdisk_end) - (char )(&__ramdisk_begin);	63	initrd_size = (char )(&__ramdisk_end) - (char )(&__ramdisk_begin);
60	if (initrd_size) {	64	if (initrd_size) {
61	initrd_start = (RAM_END - initrd_size) & ~0xFFF;	65	initrd_start = (ram_end - initrd_size) & ~0xFFF;
62	a1 = initrd_start;	66	a1 = initrd_start;
63	a2 = initrd_size;	67	a2 = initrd_size;
64	claim(initrd_start, RAM_END - initrd_start, 0);	68	claim(initrd_start, ram_end - initrd_start, 0);
65	printf("initial ramdisk moving 0x%x <- 0x%p (%x bytes)\n\r",	69	printf("initial ramdisk moving 0x%x <- 0x%p (%x bytes)\n\r",
66	initrd_start, (char *)(&__ramdisk_begin), initrd_size);	70	initrd_start, (char *)(&__ramdisk_begin), initrd_size);
67	memcpy((char )initrd_start, (char )(&__ramdisk_begin), initrd_size);	71	memcpy((char )initrd_start, (char )(&__ramdisk_begin), initrd_size);
		72	prog_size = initrd_start - prog_start;
68	} else	73	} else
69	a2 = 0xdeadbeef;	74	a2 = 0xdeadbeef;
70		75
71	im = (char *)(&__image_begin);	76	im = (char *)(&__image_begin);
72	len = (char )(&__image_end) - (char )(&__image_begin);	77	len = (char )(&__image_end) - (char )(&__image_begin);
73	/* claim 4MB starting at 0 */	78	/* claim 4MB starting at 0 */
74	claim(0, PROG_SIZE, 0);	79	claim(prog_start, prog_size, 0);
75	dst = (void *) RAM_START;	80	map(prog_start, prog_start, prog_size);
		81	dst = (void *) prog_start;
76	if (im[0] == 0x1f && im[1] == 0x8b) {	82	if (im[0] == 0x1f && im[1] == 0x8b) {
77	/* set up scratch space */	83	/* set up scratch space */
78	begin_avail = avail_high = avail_ram = heap;	84	begin_avail = avail_high = avail_ram = heap;
79	end_avail = heap + sizeof(heap);	85	end_avail = heap + sizeof(heap);
80	printf("heap at 0x%p\n", avail_ram);	86	printf("heap at 0x%p\n", avail_ram);
81	printf("gunzipping (0x%p <- 0x%p:0x%p)...", dst, im, im+len);	87	printf("gunzipping (0x%p <- 0x%p:0x%p)...", dst, im, im+len);
82	gunzip(dst, PROG_SIZE, im, &len);	88	gunzip(dst, prog_size, im, &len);
83	printf("done %u bytes\n", len);	89	printf("done %u bytes\n", len);
84	printf("%u bytes of heap consumed, max in use %u\n",	90	printf("%u bytes of heap consumed, max in use %u\n",
85	avail_high - begin_avail, heap_max);	91	avail_high - begin_avail, heap_max);
Lines 89-97 Link Here
89		95
90	flush_cache(dst, len);	96	flush_cache(dst, len);
91	make_bi_recs(((unsigned long) dst + len), "coffboot", _MACH_Pmac,	97	make_bi_recs(((unsigned long) dst + len), "coffboot", _MACH_Pmac,
92	(PROG_START + PROG_SIZE));	98	(prog_start + prog_size));
93		99
94	sa = (unsigned long)PROG_START;	100	sa = (unsigned long)prog_start;
95	printf("start address = 0x%x\n", sa);	101	printf("start address = 0x%x\n", sa);
96		102
97	(*(kernel_start_t)sa)(a1, a2, prom);	103	(*(kernel_start_t)sa)(a1, a2, prom);

Lines 53-58 Link Here

(-)linux-2.4.22/arch/ppc/config.in (+11 lines)
53	define_bool CONFIG_PPC_STD_MMU y	53	define_bool CONFIG_PPC_STD_MMU y
54	fi	54	fi
55		55
		56	bool 'CPU Frequency scaling' CONFIG_CPU_FREQ
		57	if [ "$CONFIG_CPU_FREQ" = "y" ]; then
		58	bool ' /proc/sys/cpu/ interface (2.4.)' CONFIG_CPU_FREQ_24_API
		59	if [ "$CONFIG_CPU_FREQ_24_API" = "n" ]; then
		60	define_bool CONFIG_CPU_FREQ_26_API y
		61	fi
		62	if [ "$CONFIG_ADB_PMU" = "y" ]; then
		63	bool " Support for Apple PowerBooks" CONFIG_CPU_FREQ_PMAC
		64	fi
		65	fi
		66
56	if [ "$CONFIG_8260" = "y" ]; then	67	if [ "$CONFIG_8260" = "y" ]; then
57	define_bool CONFIG_SERIAL_CONSOLE y	68	define_bool CONFIG_SERIAL_CONSOLE y
58	bool 'Support for EST8260' CONFIG_EST8260	69	bool 'Support for EST8260' CONFIG_EST8260

Lines 1-5 Link Here

(-)linux-2.4.22/arch/ppc/configs/briq_defconfig (-21 / +2 lines)
1	#	1	#
2	# Automatically generated make config: don't edit	2	# Automatically generated by make menuconfig: don't edit
3	#	3	#
4	# CONFIG_UID16 is not set	4	# CONFIG_UID16 is not set
5	# CONFIG_RWSEM_GENERIC_SPINLOCK is not set	5	# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
Lines 30-35 Link Here
30	# CONFIG_8xx is not set	30	# CONFIG_8xx is not set
31	# CONFIG_8260 is not set	31	# CONFIG_8260 is not set
32	CONFIG_PPC_STD_MMU=y	32	CONFIG_PPC_STD_MMU=y
		33	# CONFIG_CPU_FREQ is not set
33	CONFIG_ALL_PPC=y	34	CONFIG_ALL_PPC=y
34	# CONFIG_APUS is not set	35	# CONFIG_APUS is not set
35	# CONFIG_SPRUCE is not set	36	# CONFIG_SPRUCE is not set
Lines 191-200 Link Here
191	# CONFIG_KHTTPD is not set	192	# CONFIG_KHTTPD is not set
192	# CONFIG_ATM is not set	193	# CONFIG_ATM is not set
193	# CONFIG_VLAN_8021Q is not set	194	# CONFIG_VLAN_8021Q is not set
194
195	#
196	#
197	#
198	# CONFIG_IPX is not set	195	# CONFIG_IPX is not set
199	CONFIG_ATALK=m	196	CONFIG_ATALK=m
200		197
Lines 232-241 Link Here
232	# IDE, ATA and ATAPI Block devices	229	# IDE, ATA and ATAPI Block devices
233	#	230	#
234	CONFIG_BLK_DEV_IDE=y	231	CONFIG_BLK_DEV_IDE=y
235
236	#
237	# Please see Documentation/ide.txt for help/info on IDE drives
238	#
239	# CONFIG_BLK_DEV_HD_IDE is not set	232	# CONFIG_BLK_DEV_HD_IDE is not set
240	# CONFIG_BLK_DEV_HD is not set	233	# CONFIG_BLK_DEV_HD is not set
241	CONFIG_BLK_DEV_IDEDISK=y	234	CONFIG_BLK_DEV_IDEDISK=y
Lines 247-256 Link Here
247	CONFIG_BLK_DEV_IDEFLOPPY=y	240	CONFIG_BLK_DEV_IDEFLOPPY=y
248	CONFIG_BLK_DEV_IDESCSI=y	241	CONFIG_BLK_DEV_IDESCSI=y
249	# CONFIG_IDE_TASK_IOCTL is not set	242	# CONFIG_IDE_TASK_IOCTL is not set
250
251	#
252	# IDE chipset support/bugfixes
253	#
254	# CONFIG_BLK_DEV_CMD640 is not set	243	# CONFIG_BLK_DEV_CMD640 is not set
255	# CONFIG_BLK_DEV_CMD640_ENHANCED is not set	244	# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
256	# CONFIG_BLK_DEV_ISAPNP is not set	245	# CONFIG_BLK_DEV_ISAPNP is not set
Lines 588-601 Link Here
588	# Joysticks	577	# Joysticks
589	#	578	#
590	# CONFIG_INPUT_GAMEPORT is not set	579	# CONFIG_INPUT_GAMEPORT is not set
591
592	#
593	# Input core support is needed for gameports
594	#
595
596	#
597	# Input core support is needed for joysticks
598	#
599	# CONFIG_QIC02_TAPE is not set	580	# CONFIG_QIC02_TAPE is not set
600	# CONFIG_IPMI_HANDLER is not set	581	# CONFIG_IPMI_HANDLER is not set
601	# CONFIG_IPMI_PANIC_EVENT is not set	582	# CONFIG_IPMI_PANIC_EVENT is not set

Lines 42-63 Link Here

(-)linux-2.4.22/arch/ppc/kernel/btext.c (-11 / +3 lines)
42	static unsigned char vga_font[cmapsz];	42	static unsigned char vga_font[cmapsz];
43		43
44	int boot_text_mapped;	44	int boot_text_mapped;
		45	int force_printk_to_btext;
45		46
46	boot_infos_t disp_bi;	47	boot_infos_t disp_bi;
47		48
48	extern char *klimit;	49	extern char *klimit;
49		50
50	/*	51	#define BTEXT
51	* Powermac can use btext_* after boot for xmon,	52	#define BTDATA
52	* chrp only uses it during early boot.
53	*/
54	#ifdef CONFIG_XMON
55	#define BTEXT __pmac
56	#define BTDATA __pmacdata
57	#else
58	#define BTEXT __init
59	#define BTDATA __initdata
60	#endif /* CONFIG_XMON */
61		53
62	/*	54	/*
63	* This is called only when we are booted via BootX.	55	* This is called only when we are booted via BootX.

Lines 316-325 Link Here

(-)linux-2.4.22/arch/ppc/kernel/head.S (-4 / +2 lines)
316	#endif	316	#endif
317		317
318	/* Machine check */	318	/* Machine check */
319	BEGIN_FTR_SECTION
320	DSSALL
321	sync
322	END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
323	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)	319	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
324		320
325	/* Data access exception. */	321	/* Data access exception. */
Lines 983-989 Link Here
983	/* enable use of AltiVec after return */	979	/* enable use of AltiVec after return */
984	oris r23,r23,MSR_VEC@h	980	oris r23,r23,MSR_VEC@h
985	mfspr r5,SPRG3 /* current task's THREAD (phys) */	981	mfspr r5,SPRG3 /* current task's THREAD (phys) */
		982	li r4,1
986	li r20,THREAD_VSCR	983	li r20,THREAD_VSCR
		984	stw r4,THREAD_USED_VR(r5)
987	LVX(vr0,r20,r5)	985	LVX(vr0,r20,r5)
988	MTVSCR(vr0)	986	MTVSCR(vr0)
989	REST_32VR(0,r20,r5)	987	REST_32VR(0,r20,r5)

Lines 200-205 Link Here

(-)linux-2.4.22/arch/ppc/kernel/misc.S (+71 lines)
200	mr r4,r24	200	mr r4,r24
201	bctr	201	bctr
202		202
		203	#ifdef CONFIG_CPU_FREQ_PMAC
		204
		205	/* This gets called by via-pmu.c to switch the PLL selection
		206	* on 750fx CPU.
		207	*/
		208	_GLOBAL(low_choose_750fx_pll)
		209	/* Clear MSR:EE */
		210	mfmsr r7
		211	rlwinm r0,r7,0,17,15
		212	mtmsr r0
		213
		214	/* If switching to PLL1, disable HID0:BTIC */
		215	cmpli cr0,r3,0
		216	beq 1f
		217	mfspr r5,HID0
		218	rlwinm r5,r5,0,27,25
		219	sync
		220	mtspr HID0,r5
		221	isync
		222	sync
		223
		224	1:
		225	/* Calc new HID1 value */
		226	mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
		227	rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
		228	rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
		229	or r4,r4,r5
		230	mtspr SPRN_HID1,r4
		231
		232	/* Store new HID1 image */
		233	lwz r6,PROCESSOR(r2)
		234	slwi r6,r6,2
		235	addis r6,r6,nap_save_hid1@ha
		236	stw r4,nap_save_hid1@l(r6)
		237
		238	/* If switching to PLL0, enable HID0:BTIC */
		239	cmpli cr0,r3,0
		240	bne 1f
		241	mfspr r5,HID0
		242	ori r5,r5,HID0_BTIC
		243	sync
		244	mtspr HID0,r5
		245	isync
		246	sync
		247
		248	1:
		249	/* Return */
		250	mtmsr r7
		251	blr
		252
		253	#endif /* CONFIG_CPU_FREQ_PMAC */
		254
		255
203	/* void __save_flags_ptr(unsigned long flags) /	256	/* void __save_flags_ptr(unsigned long flags) /
204	_GLOBAL(__save_flags_ptr)	257	_GLOBAL(__save_flags_ptr)
205	mfmsr r4	258	mfmsr r4
Lines 1243-1248 Link Here
1243	.long sys_ni_syscall /* reserved for sys_io_getevents */	1296	.long sys_ni_syscall /* reserved for sys_io_getevents */
1244	.long sys_ni_syscall /* 230 reserved for sys_io_submit */	1297	.long sys_ni_syscall /* 230 reserved for sys_io_submit */
1245	.long sys_ni_syscall /* reserved for sys_io_cancel */	1298	.long sys_ni_syscall /* reserved for sys_io_cancel */
		1299	.long sys_ni_syscall /* reserved for sys_set_tid_address */
		1300	.long sys_ni_syscall /* reserved for sys_fadvise64 */
		1301	.long sys_ni_syscall /* reserved for sys_exit_group */
		1302	.long sys_ni_syscall /* 235 reserved for sys_lookup_dcookie */
		1303	.long sys_ni_syscall /* reserved for sys_epoll_create */
		1304	.long sys_ni_syscall /* reserved for sys_epoll_ctl */
		1305	.long sys_ni_syscall /* reserved for sys_epoll_wait */
		1306	.long sys_ni_syscall /* reserved for sys_remap_file_pages */
		1307	.long sys_ni_syscall /* 240 reserved for sys_timer_create */
		1308	.long sys_ni_syscall /* reserved for sys_timer_settime */
		1309	.long sys_ni_syscall /* reserved for sys_timer_gettime */
		1310	.long sys_ni_syscall /* reserved for sys_timer_getoverrun */
		1311	.long sys_ni_syscall /* reserved for sys_timer_delete */
		1312	.long sys_ni_syscall /* 245 reserved for sys_clock_settime */
		1313	.long sys_ni_syscall /* reserved for sys_clock_gettime */
		1314	.long sys_ni_syscall /* reserved for sys_clock_getres */
		1315	.long sys_ni_syscall /* reserved for sys_clock_nanosleep */
		1316	.long sys_swapcontext
1246		1317
1247	.rept NR_syscalls-(.-sys_call_table)/4	1318	.rept NR_syscalls-(.-sys_call_table)/4
1248	.long sys_ni_syscall	1319	.long sys_ni_syscall

Lines 14-19 Link Here

(-)linux-2.4.22/arch/ppc/kernel/ppc_ksyms.c (-5 / +14 lines)
14	#include <linux/irq.h>	14	#include <linux/irq.h>
15	#include <linux/pci.h>	15	#include <linux/pci.h>
16	#include <linux/delay.h>	16	#include <linux/delay.h>
		17	#include <linux/vmalloc.h>
17	#include <linux/ide.h>	18	#include <linux/ide.h>
18		19
19	#include <asm/page.h>	20	#include <asm/page.h>
Lines 67-75 Link Here
67	extern int pmac_newworld;	68	extern int pmac_newworld;
68	extern int sys_sigreturn(struct pt_regs *regs);	69	extern int sys_sigreturn(struct pt_regs *regs);
69		70
70	long long __ashrdi3(long long, int);	71	extern long long __ashrdi3(long long, int);
71	long long __ashldi3(long long, int);	72	extern long long __ashldi3(long long, int);
72	long long __lshrdi3(long long, int);	73	extern long long __lshrdi3(long long, int);
		74
73	int abs(int);	75	int abs(int);
74		76
75	extern unsigned char __res[];	77	extern unsigned char __res[];
Lines 128-134 Link Here
128	EXPORT_SYMBOL(strcmp);	130	EXPORT_SYMBOL(strcmp);
129	EXPORT_SYMBOL(strncmp);	131	EXPORT_SYMBOL(strncmp);
130	EXPORT_SYMBOL(strcasecmp);	132	EXPORT_SYMBOL(strcasecmp);
131	EXPORT_SYMBOL(__div64_32);
132		133
133	/* EXPORT_SYMBOL(csum_partial); already in net/netsyms.c */	134	/* EXPORT_SYMBOL(csum_partial); already in net/netsyms.c */
134	EXPORT_SYMBOL(csum_partial_copy_generic);	135	EXPORT_SYMBOL(csum_partial_copy_generic);
Lines 192-197 Link Here
192	EXPORT_SYMBOL(flush_icache_user_range);	193	EXPORT_SYMBOL(flush_icache_user_range);
193	EXPORT_SYMBOL(flush_icache_page);	194	EXPORT_SYMBOL(flush_icache_page);
194	EXPORT_SYMBOL(flush_dcache_page);	195	EXPORT_SYMBOL(flush_dcache_page);
		196	EXPORT_SYMBOL(local_flush_tlb_page);
195	EXPORT_SYMBOL(xchg_u32);	197	EXPORT_SYMBOL(xchg_u32);
196	#ifdef CONFIG_ALTIVEC	198	#ifdef CONFIG_ALTIVEC
197	EXPORT_SYMBOL(last_task_used_altivec);	199	EXPORT_SYMBOL(last_task_used_altivec);
Lines 288-293 Link Here
288	EXPORT_SYMBOL_NOVERS(memscan);	290	EXPORT_SYMBOL_NOVERS(memscan);
289	EXPORT_SYMBOL_NOVERS(memcmp);	291	EXPORT_SYMBOL_NOVERS(memcmp);
290	EXPORT_SYMBOL_NOVERS(memchr);	292	EXPORT_SYMBOL_NOVERS(memchr);
		293	EXPORT_SYMBOL_NOVERS(__div64_32);
291		294
292	EXPORT_SYMBOL(abs);	295	EXPORT_SYMBOL(abs);
293		296
Lines 314-320 Link Here
314	EXPORT_SYMBOL(get_wchan);	317	EXPORT_SYMBOL(get_wchan);
315	EXPORT_SYMBOL(console_drivers);	318	EXPORT_SYMBOL(console_drivers);
316	#ifdef CONFIG_XMON	319	#ifdef CONFIG_XMON
317	extern void xmon_printf(char *fmt, ...);	320	extern void xmon_printf(const char *fmt, ...);
318	EXPORT_SYMBOL(xmon);	321	EXPORT_SYMBOL(xmon);
319	EXPORT_SYMBOL(xmon_printf);	322	EXPORT_SYMBOL(xmon_printf);
320	#endif	323	#endif
Lines 367-373 Link Here
367	EXPORT_SYMBOL(ret_from_intercept);	370	EXPORT_SYMBOL(ret_from_intercept);
368	EXPORT_SYMBOL(cur_cpu_spec);	371	EXPORT_SYMBOL(cur_cpu_spec);
369	#if defined(CONFIG_ALL_PPC)	372	#if defined(CONFIG_ALL_PPC)
		373	extern int map_page(unsigned long va, unsigned long pa, int flags);
		374
		375	EXPORT_SYMBOL(map_page);
		376	EXPORT_SYMBOL(get_vm_area);
370	extern unsigned long agp_special_page;	377	extern unsigned long agp_special_page;
371	EXPORT_SYMBOL_NOVERS(agp_special_page);	378	EXPORT_SYMBOL_NOVERS(agp_special_page);
		379	EXPORT_SYMBOL(ioremap_bot);
		380	EXPORT_SYMBOL(local_flush_tlb_all);
372	#endif /* defined(CONFIG_ALL_PPC) */	381	#endif /* defined(CONFIG_ALL_PPC) */
373		382

Lines 73-81 Link Here

(-)linux-2.4.22/arch/ppc/kernel/semaphore.c (-8 / +7 lines)
73	struct task_struct *tsk = current;	73	struct task_struct *tsk = current;
74	DECLARE_WAITQUEUE(wait, tsk);	74	DECLARE_WAITQUEUE(wait, tsk);
75		75
76	tsk->state = TASK_UNINTERRUPTIBLE;	76	__set_task_state(tsk, TASK_UNINTERRUPTIBLE);
77	add_wait_queue_exclusive(&sem->wait, &wait);	77	add_wait_queue_exclusive(&sem->wait, &wait);
78	smp_wmb();
79		78
80	/*	79	/*
81	* Try to get the semaphore. If the count is > 0, then we've	80	* Try to get the semaphore. If the count is > 0, then we've
Lines 85-94 Link Here
85	*/	84	*/
86	while (__sem_update_count(sem, -1) <= 0) {	85	while (__sem_update_count(sem, -1) <= 0) {
87	schedule();	86	schedule();
88	tsk->state = TASK_UNINTERRUPTIBLE;	87	set_task_state(tsk, TASK_UNINTERRUPTIBLE);
89	}	88	}
90	remove_wait_queue(&sem->wait, &wait);	89	remove_wait_queue(&sem->wait, &wait);
91	tsk->state = TASK_RUNNING;	90	__set_task_state(tsk, TASK_RUNNING);
92		91
93	/*	92	/*
94	* If there are any more sleepers, wake one of them up so	93	* If there are any more sleepers, wake one of them up so
Lines 104-112 Link Here
104	struct task_struct *tsk = current;	103	struct task_struct *tsk = current;
105	DECLARE_WAITQUEUE(wait, tsk);	104	DECLARE_WAITQUEUE(wait, tsk);
106		105
107	tsk->state = TASK_INTERRUPTIBLE;	106	__set_task_state(tsk, TASK_INTERRUPTIBLE);
108	add_wait_queue_exclusive(&sem->wait, &wait);	107	add_wait_queue_exclusive(&sem->wait, &wait);
109	smp_wmb();
110		108
111	while (__sem_update_count(sem, -1) <= 0) {	109	while (__sem_update_count(sem, -1) <= 0) {
112	if (signal_pending(current)) {	110	if (signal_pending(current)) {
Lines 120-129 Link Here
120	break;	118	break;
121	}	119	}
122	schedule();	120	schedule();
123	tsk->state = TASK_INTERRUPTIBLE;	121	set_task_state(tsk, TASK_INTERRUPTIBLE);
124	}	122	}
125	tsk->state = TASK_RUNNING;
126	remove_wait_queue(&sem->wait, &wait);	123	remove_wait_queue(&sem->wait, &wait);
		124	__set_task_state(tsk, TASK_RUNNING);
		125
127	wake_up(&sem->wait);	126	wake_up(&sem->wait);
128	return retval;	127	return retval;
129	}	128	}

Lines 52-57 Link Here

(-)linux-2.4.22/arch/ppc/kernel/setup.c (-1 / +24 lines)
52	struct ide_machdep_calls ppc_ide_md;	52	struct ide_machdep_calls ppc_ide_md;
53	char *sysmap;	53	char *sysmap;
54	unsigned long sysmap_size;	54	unsigned long sysmap_size;
		55	int no_nap;
55		56
56	/* Used with the BI_MEMSIZE bootinfo parameter to store the memory	57	/* Used with the BI_MEMSIZE bootinfo parameter to store the memory
57	size value reported by the boot loader. */	58	size value reported by the boot loader. */
Lines 152-158 Link Here
152	return 0;	153	return 0;
153	pvr = cpu_data[i].pvr;	154	pvr = cpu_data[i].pvr;
154	lpj = cpu_data[i].loops_per_jiffy;	155	lpj = cpu_data[i].loops_per_jiffy;
155	seq_printf(m, "processor\t: %lu\n", i);	156	seq_printf(m, "processor\t: %u\n", i);
156	#else	157	#else
157	pvr = mfspr(PVR);	158	pvr = mfspr(PVR);
158	lpj = loops_per_jiffy;	159	lpj = loops_per_jiffy;
Lines 329-334 Link Here
329	unsigned long r6, unsigned long r7)	330	unsigned long r6, unsigned long r7)
330	{	331	{
331	#ifdef CONFIG_BOOTX_TEXT	332	#ifdef CONFIG_BOOTX_TEXT
		333	extern int force_printk_to_btext;
332	if (boot_text_mapped) {	334	if (boot_text_mapped) {
333	btext_clearscreen();	335	btext_clearscreen();
334	btext_welcome();	336	btext_welcome();
Lines 415-420 Link Here
415	}	417	}
416	cmd_line[sizeof(cmd_line) - 1] = 0;	418	cmd_line[sizeof(cmd_line) - 1] = 0;
417		419
		420	/* Debug stuff, do not merge ! */
		421	#ifdef CONFIG_ADB_PMU
		422	if (strstr(cmd_line, "fake_sleep")) {
		423	extern int __fake_sleep;
		424	__fake_sleep = 1;
		425	}
		426	#endif /* CONFIG_ADB_PMU */
		427	#ifdef CONFIG_ADB
		428	if (strstr(cmd_line, "adb_sync")) {
		429	extern int __adb_probe_sync;
		430	__adb_probe_sync = 1;
		431	}
		432	#endif /* CONFIG_ADB */
		433	if (strstr(cmd_line, "nol3") && cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR)
		434	_set_L3CR(0);
		435	if (strstr(cmd_line, "nonap"))
		436	cur_cpu_spec[0]->cpu_features &= ~CPU_FTR_CAN_NAP;
		437	#ifdef CONFIG_BOOTX_TEXT
		438	if (strstr(cmd_line, "printkbtext"))
		439	force_printk_to_btext = 1;
		440	#endif
418	switch (_machine) {	441	switch (_machine) {
419	case _MACH_Pmac:	442	case _MACH_Pmac:
420	pmac_init(r3, r4, r5, r6, r7);	443	pmac_init(r3, r4, r5, r6, r7);

Line 0 Link Here

(-)linux-2.4.22/arch/ppc/kernel/smp-tbsync.c (+182 lines)
		1	/*
		2	* Smp timebase synchronization for ppc.
		3	*
		4	* Copyright (C) 2003 Samuel Rydh (samuel@ibrium.se)
		5	*
		6	*/
		7
		8	#include <linux/config.h>
		9	#include <linux/kernel.h>
		10	#include <linux/sched.h>
		11	#include <linux/smp.h>
		12	#include <linux/unistd.h>
		13	#include <linux/init.h>
		14	#include <linux/slab.h>
		15	#include <asm/atomic.h>
		16	#include <asm/smp.h>
		17	#include <asm/time.h>
		18
		19	#define NUM_ITER 300
		20
		21	enum {
		22	kExit=0, kSetAndTest, kTest
		23	};
		24
		25	static struct {
		26	volatile int tbu;
		27	volatile int tbl;
		28	volatile int mark;
		29	volatile int cmd;
		30	volatile int handshake;
		31	int filler[3];
		32
		33	volatile int ack;
		34	int filler2[7];
		35
		36	volatile int race_result;
		37	} *tbsync;
		38
		39	static volatile int running;
		40
		41	static void __devinit
		42	enter_contest( int mark, int add )
		43	{
		44	while( (int)(get_tbl() - mark) < 0 )
		45	tbsync->race_result = add;
		46	}
		47
		48	void __devinit
		49	smp_generic_take_timebase( void )
		50	{
		51	int cmd, tbl, tbu;
		52
		53	local_irq_disable();
		54	while( !running )
		55	;
		56	rmb();
		57
		58	for( ;; ) {
		59	tbsync->ack = 1;
		60	while( !tbsync->handshake )
		61	;
		62	rmb();
		63
		64	cmd = tbsync->cmd;
65	tbl = tbsync->tbl;
66	tbu = tbsync->tbu;
67	tbsync->ack = 0;
68	if( cmd == kExit )
69	return;
70
71	if( cmd == kSetAndTest ) {
72	while( tbsync->handshake )
73	;
74	asm volatile ("mttbl %0" :: "r" (tbl) );
75	asm volatile ("mttbu %0" :: "r" (tbu) );
76	} else {
77	while( tbsync->handshake )
78	;
79	}
80	enter_contest( tbsync->mark, -1 );
81	}
82	local_irq_enable();
83	}
84
85	static int __devinit
86	start_contest( int cmd, int offset, int num )
87	{
88	int i, tbu, tbl, mark, score=0;
89
90	tbsync->cmd = cmd;
91
92	local_irq_disable();
93	for( i=-3; i<num; ) {
94	tbl = get_tbl() + 400;
95	tbsync->tbu = tbu = get_tbu();
96	tbsync->tbl = tbl + offset;
97	tbsync->mark = mark = tbl + 400;
98
99	wmb();
100
101	tbsync->handshake = 1;
102	while( tbsync->ack )
103	;
104
105	while( (int)(get_tbl() - tbl) <= 0 )
106	;
107	tbsync->handshake = 0;
108	enter_contest( mark, 1 );
109
110	while( !tbsync->ack )
111	;
112
113	if( tbsync->tbu != get_tbu() \|\| ((tbsync->tbl ^ get_tbl()) & 0x80000000) )
114	continue;
115	if( i++ > 0 )
116	score += tbsync->race_result;
117	}
118	local_irq_enable();
119	return score;
120	}
121
122	void __devinit
123	smp_generic_give_timebase( void )
124	{
125	int i, score, score2, old, min=0, max=5000, offset=1000;
126
127	printk("Synchronizing timebase\n");
128
129	/* if this fails then this kernel won't work anyway... */
130	tbsync = kmalloc( sizeof(*tbsync), GFP_KERNEL );
131	memset( tbsync, 0, sizeof(*tbsync) );
132	mb();
133	running = 1;
134
135	while( !tbsync->ack )
136	;
137
138	/* binary search */
139	for( old=-1 ; old != offset ; offset=(min+max)/2 ) {
140	score = start_contest( kSetAndTest, offset, NUM_ITER );
141
142	printk("score %d, offset %d\n", score, offset );
143
144	if( score > 0 )
145	max = offset;
146	else
147	min = offset;
148	old = offset;
149	}
150	score = start_contest( kSetAndTest, min, NUM_ITER );
151	score2 = start_contest( kSetAndTest, max, NUM_ITER );
152
153	printk( "Min %d (score %d), Max %d (score %d)\n", min, score, max, score2 );
154	score = abs( score );
155	score2 = abs( score2 );
156	offset = (score < score2) ? min : max;
157
158	/* guard against inaccurate mttb */
159	for( i=0; i<10; i++ ) {
160	start_contest( kSetAndTest, offset, NUM_ITER/10 );
161
162	if( (score2=start_contest(kTest, offset, NUM_ITER)) < 0 )
163	score2 = -score2;
164	if( score2 <= score \|\| score2 < 20 )
165	break;
166	}
167	printk("Final offset: %d (%d/%d)\n", offset, score2, NUM_ITER );
168
169	/* exiting */
170	tbsync->cmd = kExit;
171	wmb();
172	tbsync->handshake = 1;
173	while( tbsync->ack )
174	;
175	tbsync->handshake = 0;
176	kfree( tbsync );
177	tbsync = NULL;
178	running = 0;
179
180	/* all done */
181	smp_tb_synchronized = 1;
182	}

Lines 457-462 Link Here

(-)linux-2.4.22/arch/ppc/mm/init.c (+11 lines)
457	high_memory = (void *) __va(PPC_MEMSTART + total_lowmem);	457	high_memory = (void *) __va(PPC_MEMSTART + total_lowmem);
458	num_physpages = max_mapnr; /* RAM is assumed contiguous */	458	num_physpages = max_mapnr; /* RAM is assumed contiguous */
459		459
		460	/* Sanity check: did ioremap_bot stomp over vmalloc space ? We keep
		461	* a minimal 16Mb guard though if you only have 16Mb left, you'll
		462	* probably run into trouble, so we also printk something if you
		463	* have less than 64Mb. This is meant to help diagnosing such problems
		464	* as debugging it can be really painful. --BenH.
		465	*/
		466	if (VMALLOC_END < (VMALLOC_START + 0x01000000UL))
		467	panic("Argh ! Virtual space exhausted !");
		468	if (VMALLOC_END < (VMALLOC_START + 0x04000000UL))
		469	printk(KERN_WARNING "Warning ! Virtual space small !");
		470
460	totalram_pages += free_all_bootmem();	471	totalram_pages += free_all_bootmem();
461		472
462	#ifdef CONFIG_BLK_DEV_INITRD	473	#ifdef CONFIG_BLK_DEV_INITRD

Line 0 Link Here

(-)linux-2.4.22/arch/ppc/platforms/pmac_cpufreq.c (+352 lines)
		1	#include <linux/config.h>
		2	#include <linux/types.h>
		3	#include <linux/errno.h>
		4	#include <linux/kernel.h>
		5	#include <linux/delay.h>
		6	#include <linux/sched.h>
		7	#include <linux/adb.h>
		8	#include <linux/pmu.h>
		9	#include <linux/slab.h>
		10	#include <linux/cpufreq.h>
		11	#include <linux/init.h>
		12	#include <asm/prom.h>
		13	#include <asm/machdep.h>
		14	#include <asm/irq.h>
		15	#include <asm/hardirq.h>
		16	#include <asm/pmac_feature.h>
		17	#include <asm/mmu_context.h>
		18	#include <asm/sections.h>
		19	#include <asm/cputable.h>
		20	#include <asm/time.h>
		21
		22	#undef DEBUG_FREQ
		23
		24	extern void low_choose_750fx_pll(int pll);
		25	extern void low_sleep_handler(void);
		26	extern void openpic_sleep_save_intrs(void);
		27	extern void openpic_sleep_restore_intrs(void);
		28	extern void enable_kernel_altivec(void);
		29	extern void enable_kernel_fp(void);
		30
		31	static unsigned int low_freq;
		32	static unsigned int hi_freq;
		33	static unsigned int cur_freq;
		34	static int cpufreq_uses_pmu;
		35
		36	#define PMAC_CPU_LOW_SPEED 1
		37	#define PMAC_CPU_HIGH_SPEED 0
		38
		39	static inline void
		40	wakeup_decrementer(void)
		41	{
		42	set_dec(tb_ticks_per_jiffy);
		43	/* No currently-supported powerbook has a 601,
		44	* so use get_tbl, not native
		45	*/
		46	last_jiffy_stamp(0) = tb_last_stamp = get_tbl();
		47	}
		48
		49	#ifdef DEBUG_FREQ
		50	static inline void
		51	debug_calc_bogomips(void)
		52	{
		53	/* This will cause a recalc of bogomips and display the
		54	* result. We backup/restore the value to avoid affecting the
		55	* core cpufreq framework's own calculation.
		56	*/
		57	extern void calibrate_delay(void);
		58
		59	unsigned long save_lpj = loops_per_jiffy;
		60	calibrate_delay();
		61	loops_per_jiffy = save_lpj;
		62	}
		63	#endif
		64
65	/* Switch CPU speed under 750FX CPU control
66	*/
67	static int __pmac
68	cpu_750fx_cpu_speed(int low_speed)
69	{
70	#ifdef DEBUG_FREQ
71	printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
72	#endif
73	low_choose_750fx_pll(low_speed);
74	#ifdef DEBUG_FREQ
75	printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
76	debug_calc_bogomips();
77	#endif
78
79	return 0;
80	}
81
82	/* Switch CPU speed under PMU control
83	*/
84	static int __pmac
85	pmu_set_cpu_speed(unsigned int low_speed)
86	{
87	struct adb_request req;
88	unsigned long save_l2cr;
89	unsigned long save_l3cr;
90
91	#ifdef DEBUG_FREQ
92	printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
93	#endif
94	/* Disable all interrupt sources on openpic */
95	openpic_sleep_save_intrs();
96
97	/* Make sure the PMU is idle */
98	pmu_suspend();
99
100	/* Make sure the decrementer won't interrupt us */
101	asm volatile("mtdec %0" : : "r" (0x7fffffff));
102	/* Make sure any pending DEC interrupt occuring while we did
103	* the above didn't re-enable the DEC */
104	mb();
105	asm volatile("mtdec %0" : : "r" (0x7fffffff));
106
107	/* We can now disable MSR_EE */
108	local_irq_disable();
109
110	/* Giveup the FPU & vec */
111	enable_kernel_fp();
112
113	#ifdef CONFIG_ALTIVEC
114	if (cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC)
115	enable_kernel_altivec();
116	#endif /* CONFIG_ALTIVEC */
117
118	/* Save & disable L2 and L3 caches */
119	save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
120	save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
121	if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
122	_set_L3CR(save_l3cr & 0x7fffffff);
123	if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
124	_set_L2CR(save_l2cr & 0x7fffffff);
125
126	/* Send the new speed command. My assumption is that this command
127	* will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
128	*/
129	pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
130	while (!req.complete)
131	pmu_poll();
132
133	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
134
135	low_sleep_handler();
136
137	pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
138
139	/* Restore L2 cache */
140	if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
141	_set_L2CR(save_l2cr);
142	/* Restore L3 cache */
143	if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
144	_set_L3CR(save_l3cr);
145
146	/* Restore userland MMU context */
147	set_context(current->active_mm->context, current->active_mm->pgd);
148
149	pmu_unlock();
150
151	#ifdef DEBUG_FREQ
152	printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
153	#endif
154
155	/* Restore decrementer */
156	wakeup_decrementer();
157
158	/* Restore interrupts */
159	openpic_sleep_restore_intrs();
160
161	pmu_resume();
162
163	/* Let interrupts flow again ... */
164	local_irq_enable();
165
166	#ifdef DEBUG_FREQ
167	debug_calc_bogomips();
168	#endif
169
170	return 0;
171	}
172
173	static int __pmac
174	do_set_cpu_speed(int speed_mode)
175	{
176	struct cpufreq_freqs freqs;
177	int rc;
178
179	freqs.old = cur_freq;
180	freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
181	freqs.cpu = CPUFREQ_ALL_CPUS;
182
183	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
184	if (cpufreq_uses_pmu)
185	rc = pmu_set_cpu_speed(speed_mode);
186	else
187	rc = cpu_750fx_cpu_speed(speed_mode);
188	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
189	cur_freq = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
190
191	return rc;
192	}
193
194	static int __pmac
195	pmac_cpufreq_verify(struct cpufreq_policy *policy)
196	{
197	if (!policy)
198	return -EINVAL;
199
200	policy->cpu = 0; /* UP only */
201
202	cpufreq_verify_within_limits(policy, low_freq, hi_freq);
203
204	if ((policy->min > low_freq) &&
205	(policy->max < hi_freq))
206	policy->max = hi_freq;
207
208	return 0;
209	}
210
211	static int __pmac
212	pmac_cpufreq_setpolicy(struct cpufreq_policy *policy)
213	{
214	int rc;
215
216	if (!policy)
217	return -EINVAL;
218	if (policy->min > low_freq)
219	rc = do_set_cpu_speed(PMAC_CPU_HIGH_SPEED);
220	else if (policy->max < hi_freq)
221	rc = do_set_cpu_speed(PMAC_CPU_LOW_SPEED);
222	else if (policy->policy == CPUFREQ_POLICY_POWERSAVE)
223	rc = do_set_cpu_speed(PMAC_CPU_LOW_SPEED);
224	else
225	rc = do_set_cpu_speed(PMAC_CPU_HIGH_SPEED);
226
227	return rc;
228	}
229
230	unsigned int __pmac
231	pmac_get_cur_cpufreq(void)
232	{
233	return cur_freq;
234	}
235
236
237	/* Currently, we support the following machines:
238	*
239	* - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
240	* - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
241	* - iBook2 500 (PMU based, 400Mhz & 500Mhz)
242	* - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
243	*/
244	static int __init
245	pmac_cpufreq_setup(void)
246	{
247	struct device_node *cpunode;
248	struct cpufreq_driver *driver;
249	u32 *value;
250	int has_freq_ctl = 0;
251	int rc;
252
253	memset(&driver, 0, sizeof(driver));
254
255	/* Assume only one CPU */
256	cpunode = find_type_devices("cpu");
257	if (!cpunode)
258	goto out;
259
260	/* Get current cpu clock freq */
261	value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
262	if (!value)
263	goto out;
264	cur_freq = (*value) / 1000;
265
266	/* Check for newer machines */
267	if (machine_is_compatible("PowerBook3,4") \|\|
268	machine_is_compatible("PowerBook3,5") \|\|
269	machine_is_compatible("MacRISC3")) {
270	value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
271	if (!value)
272	goto out;
273	low_freq = (*value) / 1000;
274	/* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
275	* here */
276	if (low_freq < 100000)
277	low_freq *= 10;
278
279	value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
280	if (!value)
281	goto out;
282	hi_freq = (*value) / 1000;
283	has_freq_ctl = 1;
284	cpufreq_uses_pmu = 1;
285	}
286	/* Else check for iBook2 500 */
287	else if (machine_is_compatible("PowerBook4,1")) {
288	/* We only know about 500Mhz model */
289	if (cur_freq < 450000 \|\| cur_freq > 550000)
290	goto out;
291	hi_freq = cur_freq;
292	low_freq = 400000;
293	has_freq_ctl = 1;
294	cpufreq_uses_pmu = 1;
295	}
296	/* Else check for TiPb 500 */
297	else if (machine_is_compatible("PowerBook3,2")) {
298	/* We only know about 500Mhz model */
299	if (cur_freq < 450000 \|\| cur_freq > 550000)
300	goto out;
301	hi_freq = cur_freq;
302	low_freq = 300000;
303	has_freq_ctl = 1;
304	cpufreq_uses_pmu = 1;
305	}
306	/* Else check for 750FX */
307	else if (PVR_VER(mfspr(PVR)) == 0x7000) {
308	if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
309	goto out;
310	hi_freq = cur_freq;
311	value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
312	if (!value)
313	goto out;
314	low_freq = (*value) / 1000;
315	cpufreq_uses_pmu = 0;
316	has_freq_ctl = 1;
317	}
318	out:
319	if (!has_freq_ctl)
320	return -ENODEV;
321
322	/* initialization of main "cpufreq" code*/
323	driver = kmalloc(sizeof(struct cpufreq_driver) +
324	NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
325	if (!driver)
326	return -ENOMEM;
327
328	driver->policy = (struct cpufreq_policy *) (driver + 1);
329
330	#ifdef CONFIG_CPU_FREQ_24_API
331	driver->cpu_min_freq[0] = low_freq;
332	driver->cpu_cur_freq[0] = cur_freq;
333	#endif
334
335	driver->verify = &pmac_cpufreq_verify;
336	driver->setpolicy = &pmac_cpufreq_setpolicy;
337
338	driver->policy[0].cpu = 0;
339	driver->policy[0].min = low_freq;
340	driver->policy[0].max = cur_freq;
341	driver->policy[0].max_cpu_freq = hi_freq;
342	driver->policy[0].policy = (cur_freq == low_freq) ?
343	CPUFREQ_POLICY_POWERSAVE : CPUFREQ_POLICY_PERFORMANCE;
344
345	rc = cpufreq_register(driver);
346	if (rc)
347	kfree(driver);
348	return rc;
349	}
350
351	__initcall(pmac_cpufreq_setup);
352

Lines 209-222 Link Here

(-)linux-2.4.22/arch/ppc/xmon/xmon.c (-7 / +9 lines)
209	#endif /* CONFIG_SMP */	209	#endif /* CONFIG_SMP */
210	remove_bpts();	210	remove_bpts();
211	#ifdef CONFIG_PMAC_BACKLIGHT	211	#ifdef CONFIG_PMAC_BACKLIGHT
212	if( setjmp(bus_error_jmp) == 0 ) {	212	if (_machine == _MACH_Pmac) {
213	debugger_fault_handler = handle_fault;	213	if( setjmp(bus_error_jmp) == 0 ) {
214	sync();	214	debugger_fault_handler = handle_fault;
215	set_backlight_enable(1);	215	sync();
216	set_backlight_level(BACKLIGHT_MAX);	216	set_backlight_enable(1);
217	sync();	217	set_backlight_level(BACKLIGHT_MAX);
		218	sync();
		219	}
		220	debugger_fault_handler = 0;
218	}	221	}
219	debugger_fault_handler = 0;
220	#endif /* CONFIG_PMAC_BACKLIGHT */	222	#endif /* CONFIG_PMAC_BACKLIGHT */
221	cmd = cmds(excp);	223	cmd = cmds(excp);
222	if (cmd == 's') {	224	if (cmd == 's') {

Lines 1-3 Link Here

(-)linux-2.4.22/drivers/char/defkeymap.c (-4 / +7 lines)
		1
1	/* Do not edit this file! It was automatically generated by */	2	/* Do not edit this file! It was automatically generated by */
2	/* loadkeys --mktable defkeymap.map > defkeymap.c */	3	/* loadkeys --mktable defkeymap.map > defkeymap.c */
3		4
Lines 37-43 Link Here
37	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,	38	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
38	0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03e, 0xf10a,	39	0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03e, 0xf10a,
39	0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	40	0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
40	0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,	41	0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
41	0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116,	42	0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116,
42	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,	43	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
43	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	44	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
Lines 56-62 Link Here
56	0xf912, 0xf913, 0xf30b, 0xf90e, 0xf90f, 0xf910, 0xf30a, 0xf90b,	57	0xf912, 0xf913, 0xf30b, 0xf90e, 0xf90f, 0xf910, 0xf30a, 0xf90b,
57	0xf90c, 0xf90d, 0xf90a, 0xf310, 0xf206, 0xf200, 0xf07c, 0xf516,	58	0xf90c, 0xf90d, 0xf90a, 0xf310, 0xf206, 0xf200, 0xf07c, 0xf516,
58	0xf517, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	59	0xf517, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
59	0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,	60	0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
60	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,	61	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
61	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,	62	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
62	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	63	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
Lines 94-100 Link Here
94	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,	95	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
95	0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200,	96	0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200,
96	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	97	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
97	0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,	98	0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
98	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,	99	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
99	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,	100	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
100	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	101	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
Lines 132-138 Link Here
132	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,	133	0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
133	0xf302, 0xf303, 0xf300, 0xf20c, 0xf206, 0xf200, 0xf200, 0xf50a,	134	0xf302, 0xf303, 0xf300, 0xf20c, 0xf206, 0xf200, 0xf200, 0xf50a,
134	0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	135	0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
135	0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,	136	0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
136	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c,	137	0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c,
137	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,	138	0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
138	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,	139	0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
Lines 147-152 Link Here
147		148
148	unsigned int keymap_count = 7;	149	unsigned int keymap_count = 7;
149		150
		151
150	/*	152	/*
151	* Philosophy: most people do not define more strings, but they who do	153	* Philosophy: most people do not define more strings, but they who do
152	* often want quite a lot of string space. So, we statically allocate	154	* often want quite a lot of string space. So, we statically allocate
Lines 184-189 Link Here
184	'\033', '[', 'P', 0,	186	'\033', '[', 'P', 0,
185	};	187	};
186		188
		189
187	char *funcbufptr = func_buf;	190	char *funcbufptr = func_buf;
188	int funcbufsize = sizeof(func_buf);	191	int funcbufsize = sizeof(func_buf);
189	int funcbufleft = 0; /* space left */	192	int funcbufleft = 0; /* space left */

Lines 313-318 Link Here

(-)linux-2.4.22/drivers/char/drm/drm_memory.h (+102 lines)
313	return pt;	313	return pt;
314	}	314	}
315		315
		316	/* PPC specific routine used by ioremap_agp, to be replaced by some
		317	* more generic implementation
		318	*/
		319	extern int map_page(unsigned long va, unsigned long pa, int flags);
		320
		321	void DRM(ioremap_agp)(unsigned long offset, unsigned long size, drm_device_t dev)
		322	{
		323	void *pt;
		324	struct vm_struct *area;
		325	struct drm_agp_mem *agpmem;
		326	unsigned int flags = _PAGE_NO_CACHE\|_PAGE_KERNEL\|_PAGE_PRESENT\|_PAGE_RW\|_PAGE_DIRTY;
		327	int err, i;
		328
		329	printk("drm: ioremap_agp, offset: 0x%08lx, size: 0x%08lx\n", offset, size);
		330
		331	#if __REALLY_HAVE_AGP
		332	if (!size) {
		333	DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
		334	"Mapping 0 bytes at 0x%08lx\n", offset);
		335	return NULL;
		336	}
		337
		338	if (!dev->agp \|\| !dev->agp->cant_use_aperture)
		339	return DRM(ioremap)(offset, size);
		340
		341	/* XXX This has to be changed into something more generic
		342	* this implementation is really only valid on PPC
		343	*/
		344	area = get_vm_area(size, VM_IOREMAP);
		345	if (area == 0) {
		346	spin_lock(&DRM(mem_lock));
		347	++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count;
		348	spin_unlock(&DRM(mem_lock));
		349	printk("->NULL\n");
		350	return NULL;
		351	}
		352	pt = (void *)VMALLOC_VMADDR(area->addr);
		353	err = 0;
		354	for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
		355	unsigned long baddr = offset + i;
		356	unsigned long index;
		357
		358	/*
		359	* It's AGP memory - find the real physical page to map
		360	*/
		361	for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) {
		362	if (agpmem->bound <= baddr &&
		363	agpmem->bound + agpmem->pages * PAGE_SIZE > baddr)
		364	break;
		365	}
		366	if (!agpmem) {
		367	printk("drm: not matching AGP page in ioremap_agp\n");
		368	err = 1;
		369	break;
		370	}
		371	index = (baddr - agpmem->bound) >> PAGE_SHIFT;
		372	get_page(virt_to_page(__va(agpmem->memory->memory[index])));
		373	err = map_page(((unsigned long)pt)+i, agpmem->memory->memory[index], flags);
		374	}
		375	if (err) {
		376	vfree((void *)pt);
		377	spin_lock(&DRM(mem_lock));
		378	++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count;
		379	spin_unlock(&DRM(mem_lock));
380	printk("->NULL\n");
381	return NULL;
382	}
383
384	spin_lock(&DRM(mem_lock));
385	++DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
386	DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_allocated += size;
387	spin_unlock(&DRM(mem_lock));
388	printk("->pt=0x%p\n", pt);
389	return pt;
390	#else
391	return NULL;
392	#endif
393	}
394
395	void DRM(ioremap_agp_free)(void *pt, unsigned long size)
396	{
397	int alloc_count;
398	int free_count;
399
400	if (!pt)
401	DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
402	"Attempt to free NULL pointer\n");
403	else
404	vfree(pt);
405
406	spin_lock(&DRM(mem_lock));
407	DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size;
408	free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count;
409	alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
410	spin_unlock(&DRM(mem_lock));
411	if (free_count > alloc_count) {
412	DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
413	"Excess frees: %d frees, %d allocs\n",
414	free_count, alloc_count);
415	}
416	}
417
316	void DRM(ioremapfree)(void *pt, unsigned long size)	418	void DRM(ioremapfree)(void *pt, unsigned long size)
317	{	419	{
318	int alloc_count;	420	int alloc_count;

Lines 379-385 Link Here

(-)linux-2.4.22/drivers/char/drm/drm_vm.h (-10 / +22 lines)
379		379
380	if ( !priv->authenticated ) return -EACCES;	380	if ( !priv->authenticated ) return -EACCES;
381		381
382	if (!VM_OFFSET(vma)) return DRM(mmap_dma)(filp, vma);	382	/* We check for "dma". On Apple's UniNorth, it's valid to have
		383	* the AGP mapped at physical address 0
		384	* --BenH.
		385	*/
		386	if (!VM_OFFSET(vma) && (!dev->agp \|\|
		387	dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE))
		388	return DRM(mmap_dma)(filp, vma);
383		389
384	/* A sequential search of a linked list is	390	/* A sequential search of a linked list is
385	fine here because: 1) there will only be	391	fine here because: 1) there will only be
Lines 419-434 Link Here
419		425
420	switch (map->type) {	426	switch (map->type) {
421	case _DRM_AGP:	427	case _DRM_AGP:
422	#if defined(__alpha__)	428	if (!dev->agp)
423	/*	429	return -ENODEV;
424	* On Alpha we can't talk to bus dma address from the	430	if (dev->agp->cant_use_aperture) {
425	* CPU, so for memory of type DRM_AGP, we'll deal with	431	/*
426	* sorting out the real physical pages and mappings	432	* On Alpha we can't talk to bus dma address from the
427	* in nopage()	433	* CPU, so for memory of type DRM_AGP, we'll deal with
428	*/	434	* sorting out the real physical pages and mappings
429	vma->vm_ops = &DRM(vm_ops);	435	* in nopage()
430	break;	436	*/
		437	#if defined(__powerpc__)
		438	pgprot_val(vma->vm_page_prot) \|= _PAGE_NO_CACHE;
431	#endif	439	#endif
		440	vma->vm_flags \|= VM_IO;
		441	vma->vm_ops = &DRM(vm_ops);
		442	break;
		443	}
432	/* fall through to _DRM_FRAME_BUFFER... */	444	/* fall through to _DRM_FRAME_BUFFER... */
433	case _DRM_FRAME_BUFFER:	445	case _DRM_FRAME_BUFFER:
434	case _DRM_REGISTERS:	446	case _DRM_REGISTERS:

Lines 31-36 Link Here

(-)linux-2.4.22/drivers/char/drm/radeon_drv.h (-9 / +46 lines)
31	#ifndef __RADEON_DRV_H__	31	#ifndef __RADEON_DRV_H__
32	#define __RADEON_DRV_H__	32	#define __RADEON_DRV_H__
33		33
		34	#if defined(__powerpc__)
		35	#define GET_RING_HEAD(ring) in_le32((volatile u32 *)(ring)->head)
		36	#define SET_RING_HEAD(ring,val) out_le32((volatile u32 *)(ring)->head, (val))
		37	#else
		38	#define GET_RING_HEAD(ring) le32_to_cpu(*(ring)->head)
		39	#define SET_RING_HEAD(ring,val) *(ring)->head = cpu_to_le32(val)
		40	#endif
		41
34	typedef struct drm_radeon_freelist {	42	typedef struct drm_radeon_freelist {
35	unsigned int age;	43	unsigned int age;
36	drm_buf_t *buf;	44	drm_buf_t *buf;
Lines 150-161 Link Here
150	extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );	158	extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
151		159
152	static inline void	160	static inline void
153	radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )	161	radeon_update_ring_snapshot( drm_radeon_private_t dev_priv, drm_radeon_ring_buffer_t ring );
154	{
155	ring->space = ((volatile int )ring->head - ring->tail) * sizeof(u32);
156	if ( ring->space <= 0 )
157	ring->space += ring->size;
158	}
159		162
160	extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );	163	extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
161	extern int radeon_do_cleanup_cp( drm_device_t *dev );	164	extern int radeon_do_cleanup_cp( drm_device_t *dev );
Lines 539-544 Link Here
539	wmb(); \	542	wmb(); \
540	RADEON_DEREF(reg) = val; \	543	RADEON_DEREF(reg) = val; \
541	} while (0)	544	} while (0)
		545	#elif defined(__powerpc__)
		546	#define RADEON_READ(reg) in_le32((volatile u32 *)RADEON_ADDR(reg))
		547	#define RADEON_WRITE(reg,val) out_le32((volatile u32 *)RADEON_ADDR(reg), (val))
542	#else	548	#else
543	#define RADEON_READ(reg) RADEON_DEREF( reg )	549	#define RADEON_READ(reg) RADEON_DEREF( reg )
544	#define RADEON_WRITE(reg, val) do { RADEON_DEREF( reg ) = val; } while (0)	550	#define RADEON_WRITE(reg, val) do { RADEON_DEREF( reg ) = val; } while (0)
Lines 557-562 Link Here
557	wmb(); \	563	wmb(); \
558	RADEON_DEREF8( reg ) = val; \	564	RADEON_DEREF8( reg ) = val; \
559	} while (0)	565	} while (0)
		566	#elif defined(__powerpc__)
		567	#define RADEON_READ8(reg) in_8((volatile u8 *)RADEON_ADDR(reg))
		568	#define RADEON_WRITE8(reg,val) out_8((volatile u8 *)RADEON_ADDR(reg), (val))
560	#else	569	#else
561	#define RADEON_READ8(reg) RADEON_DEREF8( reg )	570	#define RADEON_READ8(reg) RADEON_DEREF8( reg )
562	#define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0)	571	#define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0)
Lines 652-658 Link Here
652	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \	661	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \
653	if ( ring->space < ring->high_mark ) { \	662	if ( ring->space < ring->high_mark ) { \
654	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \	663	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
655	radeon_update_ring_snapshot( ring ); \	664	radeon_update_ring_snapshot( dev_priv, ring ); \
656	if ( ring->space >= ring->high_mark ) \	665	if ( ring->space >= ring->high_mark ) \
657	goto __ring_space_done; \	666	goto __ring_space_done; \
658	udelay( 1 ); \	667	udelay( 1 ); \
Lines 694-705 Link Here
694	* Ring control	703	* Ring control
695	*/	704	*/
696		705
		706	#if defined(__powerpc__)
		707	#define radeon_flush_write_combine() do { mb(); (void)in_le32(ring); mb(); } while(0)
		708	#else
697	#define radeon_flush_write_combine() mb()	709	#define radeon_flush_write_combine() mb()
698		710	#endif
699		711
700	#define RADEON_VERBOSE 0	712	#define RADEON_VERBOSE 0
		713	#define RADEON_DEBUG
701		714
		715	#ifdef RADEON_DEBUG
		716	#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring; int dbg;
		717	#define DEBUG_INIT(n) dbg = n
		718	#define DEBUG_INC() do { if (dbg <= 0) printk("Argh 1 ! (%s:%d)\n", __FILE__, __LINE__); \
		719	dbg--; } while(0)
		720	#define DEBUG_END() do { if (dbg != 0) printk("Argh 2/%d ! (%s:%d)\n", dbg, __FILE__, __LINE__); \
		721	dbg--; } while(0)
		722	#else
702	#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring;	723	#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring;
		724	#define DEBUG_INIT()
		725	#define DEBUG_INC()
		726	#define DEBUG_END()
		727	#endif
703		728
704	#define BEGIN_RING( n ) do { \	729	#define BEGIN_RING( n ) do { \
705	if ( RADEON_VERBOSE ) { \	730	if ( RADEON_VERBOSE ) { \
Lines 713-718 Link Here
713	ring = dev_priv->ring.start; \	738	ring = dev_priv->ring.start; \
714	write = dev_priv->ring.tail; \	739	write = dev_priv->ring.tail; \
715	mask = dev_priv->ring.tail_mask; \	740	mask = dev_priv->ring.tail_mask; \
		741	DEBUG_INIT(n); \
716	} while (0)	742	} while (0)
717		743
718	#define ADVANCE_RING() do { \	744	#define ADVANCE_RING() do { \
Lines 720-725 Link Here
720	DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \	746	DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
721	write, dev_priv->ring.tail ); \	747	write, dev_priv->ring.tail ); \
722	} \	748	} \
		749	DEBUG_END(); \
723	radeon_flush_write_combine(); \	750	radeon_flush_write_combine(); \
724	dev_priv->ring.tail = write; \	751	dev_priv->ring.tail = write; \
725	RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \	752	RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \
Lines 730-739 Link Here
730	DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \	757	DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
731	(unsigned int)(x), write ); \	758	(unsigned int)(x), write ); \
732	} \	759	} \
733	ring[write++] = (x); \	760	DEBUG_INC(); \
		761	ring[write++] = cpu_to_le32(x); \
734	write &= mask; \	762	write &= mask; \
735	} while (0)	763	} while (0)
736		764
737	#define RADEON_PERFORMANCE_BOXES 0	765	#define RADEON_PERFORMANCE_BOXES 0
738		766
		767	static inline void
		768	radeon_update_ring_snapshot( drm_radeon_private_t dev_priv, drm_radeon_ring_buffer_t ring )
		769	{
		770	// ring->space = (GET_RING_HEAD(ring) - ring->tail) * sizeof(u32);
		771	ring->space = (RADEON_READ(0x710) - ring->tail) * sizeof(u32);
		772	if ( ring->space <= 0 )
		773	ring->space += ring->size;
		774	}
		775
739	#endif /* __RADEON_DRV_H__ */	776	#endif /* __RADEON_DRV_H__ */

Lines 849-855 Link Here

(-)linux-2.4.22/drivers/char/drm/radeon_state.c (-16 / +20 lines)
849	u32 data = (u32 )	849	u32 data = (u32 )
850	((char *)dev_priv->buffers->handle	850	((char *)dev_priv->buffers->handle
851	+ buf->offset + start);	851	+ buf->offset + start);
852	data[dwords++] = RADEON_CP_PACKET2;	852	data[dwords++] = cpu_to_le32(RADEON_CP_PACKET2);
853	}	853	}
854		854
855	buf_priv->dispatched = 1;	855	buf_priv->dispatched = 1;
Lines 913-930 Link Here
913	data = (u32 )((char )dev_priv->buffers->handle	913	data = (u32 )((char )dev_priv->buffers->handle
914	+ buf->offset + start);	914	+ buf->offset + start);
915		915
916	data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );	916	data[0] = cpu_to_le32(CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ));
917		917
918	data[1] = offset;	918	data[1] = cpu_to_le32(offset);
919	data[2] = RADEON_MAX_VB_VERTS;	919	data[2] = cpu_to_le32(RADEON_MAX_VB_VERTS);
920	data[3] = format;	920	data[3] = cpu_to_le32(format);
921	data[4] = (prim \| RADEON_PRIM_WALK_IND \|	921	data[4] = cpu_to_le32((prim \| RADEON_PRIM_WALK_IND \|
922	RADEON_COLOR_ORDER_RGBA \|	922	RADEON_COLOR_ORDER_RGBA \|
923	RADEON_VTX_FMT_RADEON_MODE \|	923	RADEON_VTX_FMT_RADEON_MODE \|
924	(count << RADEON_NUM_VERTICES_SHIFT) );	924	(count << RADEON_NUM_VERTICES_SHIFT) ));
925		925
926	if ( count & 0x1 ) {	926	if ( count & 0x1 ) {
		927	#ifdef __LITTLE_ENDIAN
927	data[dwords-1] &= 0x0000ffff;	928	data[dwords-1] &= 0x0000ffff;
		929	#else
		930	data[dwords-1] &= 0xffff0000;
		931	#endif
928	}	932	}
929		933
930	do {	934	do {
Lines 1067-1088 Link Here
1067	*/	1071	*/
1068	buffer = (u32 )((char )dev_priv->buffers->handle + buf->offset);	1072	buffer = (u32 )((char )dev_priv->buffers->handle + buf->offset);
1069		1073
1070	buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );	1074	buffer[0] = cpu_to_le32(CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ));
1071	buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL \|	1075	buffer[1] = cpu_to_le32((RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
1072	RADEON_GMC_BRUSH_NONE \|	1076	RADEON_GMC_BRUSH_NONE \|
1073	(format << 8) \|	1077	(format << 8) \|
1074	RADEON_GMC_SRC_DATATYPE_COLOR \|	1078	RADEON_GMC_SRC_DATATYPE_COLOR \|
1075	RADEON_ROP3_S \|	1079	RADEON_ROP3_S \|
1076	RADEON_DP_SRC_SOURCE_HOST_DATA \|	1080	RADEON_DP_SRC_SOURCE_HOST_DATA \|
1077	RADEON_GMC_CLR_CMP_CNTL_DIS \|	1081	RADEON_GMC_CLR_CMP_CNTL_DIS \|
1078	RADEON_GMC_WR_MSK_DIS);	1082	RADEON_GMC_WR_MSK_DIS));
1079		1083
1080	buffer[2] = (tex->pitch << 22) \| (tex->offset >> 10);	1084	buffer[2] = cpu_to_le32((tex->pitch << 22) \| (tex->offset >> 10));
1081	buffer[3] = 0xffffffff;	1085	buffer[3] = cpu_to_le32(0xffffffff);
1082	buffer[4] = 0xffffffff;	1086	buffer[4] = cpu_to_le32(0xffffffff);
1083	buffer[5] = (y << 16) \| image->x;	1087	buffer[5] = cpu_to_le32((y << 16) \| image->x);
1084	buffer[6] = (height << 16) \| image->width;	1088	buffer[6] = cpu_to_le32((height << 16) \| image->width);
1085	buffer[7] = dwords;	1089	buffer[7] = cpu_to_le32(dwords);
1086		1090
1087	buffer += 8;	1091	buffer += 8;
1088		1092

Lines 38-47 Link Here

(-)linux-2.4.22/drivers/ide/ppc/pmac.c (-4 / +103 lines)
38	#include <asm/pmac_feature.h>	38	#include <asm/pmac_feature.h>
39	#include <asm/sections.h>	39	#include <asm/sections.h>
40	#include <asm/irq.h>	40	#include <asm/irq.h>
41	#ifdef CONFIG_PMAC_PBOOK
42	#include <linux/adb.h>	41	#include <linux/adb.h>
43	#include <linux/pmu.h>	42	#include <linux/pmu.h>
44	#endif
45	#include "ide_modes.h"	43	#include "ide_modes.h"
46	#include "ide-timing.h"	44	#include "ide-timing.h"
47		45
Lines 357-362 Link Here
357	};	355	};
358	#endif /* CONFIG_PMAC_PBOOK */	356	#endif /* CONFIG_PMAC_PBOOK */
359		357
		358	#ifdef CONFIG_PMU_HD_BLINK
		359
		360	/* Set to 50ms */
		361	#define PMU_HD_BLINK_TIME (HZ/20)
		362
		363	static struct adb_request pmu_blink_on, pmu_blink_off;
		364	static spinlock_t pmu_blink_lock;
		365	static unsigned long pmu_blink_stoptime;
		366	static int pmu_blink_ledstate;
		367	static struct timer_list pmu_blink_timer;
		368
		369	static void
		370	pmu_hd_blink_timeout(unsigned long data)
		371	{
		372	unsigned long flags;
		373
		374	spin_lock_irqsave(&pmu_blink_lock, flags);
		375
		376	/* We may have been triggered again in a racy way, check
		377	* that we really want to switch it off
		378	*/
		379	if (time_after(pmu_blink_stoptime, jiffies))
		380	goto done;
		381
		382	/* Previous req. not complete, try 50ms more */
		383	if (pmu_blink_off.complete == 0)
		384	mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
		385	else if (pmu_blink_ledstate) {
		386	pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
		387	pmu_blink_ledstate = 0;
		388	}
		389	done:
		390	spin_unlock_irqrestore(&pmu_blink_lock, flags);
		391	}
		392
		393	static void
		394	pmu_hd_kick_blink(void *data, int rw)
		395	{
		396	unsigned long flags;
		397
		398	pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
		399	wmb();
		400	mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
		401	if (pmu_blink_ledstate == 1)
		402	return;
		403	spin_lock_irqsave(&pmu_blink_lock, flags);
		404	if (pmu_blink_on.complete && !pmu_blink_ledstate) {
		405	pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
		406	pmu_blink_ledstate = 1;
		407	}
		408	spin_unlock_irqrestore(&pmu_blink_lock, flags);
		409	}
		410
		411	static int
		412	pmu_hd_blink_init(void)
		413	{
		414	struct device_node *dt;
		415	const char *model;
		416
		417	if (pmu_get_model() != PMU_KEYLARGO_BASED)
		418	return 0;
		419
		420	dt = find_devices("device-tree");
		421	if (dt == NULL)
422	return 0;
423	model = (const char *)get_property(dt, "model", NULL);
424	if (model == NULL)
425	return 0;
426	if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
427	strncmp(model, "iBook", strlen("iBook")) != 0)
428	return 0;
429
430	pmu_blink_on.complete = 1;
431	pmu_blink_off.complete = 1;
432	spin_lock_init(&pmu_blink_lock);
433	init_timer(&pmu_blink_timer);
434	pmu_blink_timer.function = pmu_hd_blink_timeout;
435
436	return 1;
437	}
438
439	#endif /* CONFIG_PMU_HD_BLINK */
440
360	/*	441	/*
361	* N.B. this can't be an initfunc, because the media-bay task can	442	* N.B. this can't be an initfunc, because the media-bay task can
362	* call ide_[un]register at any time.	443	* call ide_[un]register at any time.
Lines 462-468 Link Here
462	ide_hwif_t *hwif = HWIF(drive);	543	ide_hwif_t *hwif = HWIF(drive);
463	int result = 1;	544	int result = 1;
464		545
465	disable_irq(hwif->irq); /* disable_irq_nosync ?? */	546	disable_irq_nosync(hwif->irq);
466	udelay(1);	547	udelay(1);
467	SELECT_DRIVE(drive);	548	SELECT_DRIVE(drive);
468	SELECT_MASK(drive, 0);	549	SELECT_MASK(drive, 0);
Lines 945-953 Link Here
945	unsigned long base, regbase;	1026	unsigned long base, regbase;
946	int irq;	1027	int irq;
947	ide_hwif_t *hwif;	1028	ide_hwif_t *hwif;
948		1029	#ifdef CONFIG_PMU_HD_BLINK
		1030	int has_blink;
		1031	#endif
949	if (_machine != _MACH_Pmac)	1032	if (_machine != _MACH_Pmac)
950	return;	1033	return;
		1034
951	pp = &atas;	1035	pp = &atas;
952	rp = &removables;	1036	rp = &removables;
953	p = find_devices("ATA");	1037	p = find_devices("ATA");
Lines 957-962 Link Here
957	p = find_type_devices("ide");	1041	p = find_type_devices("ide");
958	if (p == NULL)	1042	if (p == NULL)
959	p = find_type_devices("ata");	1043	p = find_type_devices("ata");
		1044
		1045	if (p == NULL)
		1046	return;
		1047
		1048	#ifdef CONFIG_PMU_HD_BLINK
		1049	has_blink = pmu_hd_blink_init();
		1050	#endif /* CONFIG_PMU_HD_BLINK */
		1051
960	/* Move removable devices such as the media-bay CDROM	1052	/* Move removable devices such as the media-bay CDROM
961	on the PB3400 to the end of the list. */	1053	on the PB3400 to the end of the list. */
962	for (; p != NULL; p = nextp) {	1054	for (; p != NULL; p = nextp) {
Lines 1163-1168 Link Here
1163	hwif->selectproc = pmac_ide_selectproc;	1255	hwif->selectproc = pmac_ide_selectproc;
1164	hwif->speedproc = pmac_ide_tune_chipset;	1256	hwif->speedproc = pmac_ide_tune_chipset;
1165		1257
		1258	#ifdef CONFIG_PMU_HD_BLINK
		1259	if (has_blink)
		1260	hwif->led_act = pmu_hd_kick_blink;
		1261	#endif /* CONFIG_PMU_HD_BLINK */
		1262
1166	printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s\n",	1263	printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s\n",
1167	i, model_name[pmif->kind], pmif->aapl_bus_id,	1264	i, model_name[pmif->kind], pmif->aapl_bus_id,
1168	in_bay ? " (mediabay)" : "");	1265	in_bay ? " (mediabay)" : "");
Lines 1207-1212 Link Here
1207	#ifdef CONFIG_PMAC_PBOOK	1304	#ifdef CONFIG_PMAC_PBOOK
1208	pmu_register_sleep_notifier(&idepmac_sleep_notifier);	1305	pmu_register_sleep_notifier(&idepmac_sleep_notifier);
1209	#endif /* CONFIG_PMAC_PBOOK */	1306	#endif /* CONFIG_PMAC_PBOOK */
		1307
		1308	mdelay(IDE_WAKEUP_DELAY_MS);
1210	}	1309	}
1211		1310
1212	#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC	1311	#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC

Lines 51-57 Link Here

(-)linux-2.4.22/drivers/ide/setup-pci.c (-4 / +5 lines)
51	{	51	{
52	int h;	52	int h;
53	ide_hwif_t *hwif;	53	ide_hwif_t *hwif;
54		54	int reserved = ide_reserved_hwifs();
		55
55	/*	56	/*
56	* Look for a hwif with matching io_base specified using	57	* Look for a hwif with matching io_base specified using
57	* parameters to ide_setup().	58	* parameters to ide_setup().
Lines 90-107 Link Here
90	*/	91	*/
91	if (bootable) {	92	if (bootable) {
92	for (h = 0; h < MAX_HWIFS; ++h) {	93	for (h = 0; h < MAX_HWIFS; ++h) {
93	hwif = &ide_hwifs[h];	94	hwif = ide_hwifs + h;
94	if (hwif->chipset == ide_unknown)	95	if (hwif->chipset == ide_unknown)
95	return hwif; /* pick an unused entry */	96	return hwif; /* pick an unused entry */
96	}	97	}
97	} else {	98	} else {
98	for (h = 2; h < MAX_HWIFS; ++h) {	99	for (h = reserved; h < MAX_HWIFS; ++h) {
99	hwif = ide_hwifs + h;	100	hwif = ide_hwifs + h;
100	if (hwif->chipset == ide_unknown)	101	if (hwif->chipset == ide_unknown)
101	return hwif; /* pick an unused entry */	102	return hwif; /* pick an unused entry */
102	}	103	}
103	}	104	}
104	for (h = 0; h < 2; ++h) {	105	for (h = 0; h < reserved; ++h) {
105	hwif = ide_hwifs + h;	106	hwif = ide_hwifs + h;
106	if (hwif->chipset == ide_unknown)	107	if (hwif->chipset == ide_unknown)
107	return hwif; /* pick an unused entry */	108	return hwif; /* pick an unused entry */

Line 0 Link Here

(-)linux-2.4.22/drivers/macintosh/therm_pismo.c (+269 lines)
		1	/*
		2	* Device driver for the i2c thermostat found on some laptops
		3	*
		4	* Copyright (C) 2001 Benjamin Herrenschmidt
		5	*
		6	* Actually, there are 2 DS1775R1 on uninorth I2C busses
		7	*/
		8
		9	#include <linux/config.h>
		10	#include <linux/types.h>
		11	#include <linux/module.h>
		12	#include <linux/errno.h>
		13	#include <linux/kernel.h>
		14	#include <linux/delay.h>
		15	#include <linux/sched.h>
		16	#include <linux/i2c.h>
		17	#include <linux/slab.h>
		18	#include <linux/init.h>
		19	#include <asm/prom.h>
		20	#include <asm/machdep.h>
		21	#include <asm/io.h>
		22	#include <asm/system.h>
		23	#include <asm/sections.h>
		24
		25	#define DEBUG
		26
		27	#define I2C_THERMOSTAT_ADDR 0x49
		28	#define I2C_THERMOSTAT_ADDR2 0x48
		29	#define MAX_THERMOSTATS 4
		30
		31
		32	MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
		33	MODULE_DESCRIPTION("Driver for DS1775 thermostat on Apple laptops");
		34	MODULE_LICENSE("GPL");
		35	EXPORT_NO_SYMBOLS;
		36
		37	struct temp_range
		38	{
		39	u8 high; /* Start the fan */
		40	u8 low; /* Stop the fan */
		41	};
		42
		43	struct apple_thermal_info {
		44	u8 id; /* Implementation ID */
		45	u8 fan_count; /* Number of fans */
		46	u8 thermostat_count; /* Number of thermostats */
		47	u8 unused[5];
		48	struct temp_range ranges[4]; /* Temperature ranges (may be [])*/
		49	};
		50
		51	struct thermostat {
		52	struct i2c_client clt;
		53	int th_num;
		54	// more to come ?
		55	};
		56
		57	static struct apple_thermal_info *thinfo;
		58	static struct thermostat* thermostats[MAX_THERMOSTATS];
		59	static int therm_count;
		60
		61	static int attach_thermostat(struct i2c_adapter *adapter);
		62	static int detach_thermostat(struct i2c_client *client);
		63
		64	/* What is this supposed to be ? registered ? I hate
65	* magic numbers like that ...
66	*/
67	#define I2C_DRIVERID_THERMOSTAT (0xDEAD)
68
69	static struct i2c_driver thermostat_driver = {
70	name: "Apple Thermostat",
71	id: I2C_DRIVERID_THERMOSTAT,
72	flags: I2C_DF_NOTIFY,
73	attach_adapter: &attach_thermostat,
74	detach_client: &detach_thermostat,
75	command: NULL,
76	inc_use: NULL,
77	dec_use: NULL
78	};
79
80	static int
81	write_reg(struct thermostat* th, int reg, u8* data, int len)
82	{
83	u8 tmp[5];
84	int rc;
85
86	if (len > 4)
87	return -EINVAL;
88	tmp[0] = reg;
89	memcpy(&tmp[1], data, len);
90	rc = i2c_master_send(&th->clt, (const char *)tmp, len+1);
91	if (rc < 0)
92	return rc;
93	if (rc != (len+1))
94	return -ENODEV;
95	return 0;
96	}
97
98	static int
99	read_reg(struct thermostat* th, int reg, u8* data, int len)
100	{
101	u8 reg_addr;
102	int rc;
103
104	reg_addr = (u8)reg;
105	rc = i2c_master_send(&th->clt, &reg_addr, 1);
106	if (rc < 0)
107	return rc;
108	if (rc != 1)
109	return -ENODEV;
110	rc = i2c_master_recv(&th->clt, (char *)data, len);
111	if (rc < 0)
112	return rc;
113	if (rc != len)
114	return -ENODEV;
115	return 0;
116	}
117
118	static int
119	attach_one_thermostat(struct i2c_adapter *adapter, int addr, int num)
120	{
121	struct thermostat* th;
122	int rc;
123	u16 t, tlo, thi;
124	u8 config;
125
126	if (therm_count >= MAX_THERMOSTATS) {
127	printk(KERN_WARNING "Skipped thermostat %d (%s:%x), max count reached !\n",
128	num, adapter->name, addr);
129	return -ENODEV;
130	}
131
132	th = (struct thermostat *)kmalloc(sizeof(struct thermostat), GFP_KERNEL);
133	if (!th)
134	return -ENOMEM;
135	th->clt.addr = addr;
136	th->clt.adapter = adapter;
137	th->clt.driver = &thermostat_driver;
138	th->clt.flags = 0;
139	th->clt.data = (void *)therm_count;
140	th->th_num = num;
141	strcpy(th->clt.name, "thermostat");
142
143	rc = read_reg(th, 1, &config, 1);
144	if (rc < 0) {
145	printk(KERN_ERR "Thermostat %d (%s:%x) failed to read config !\n",
146	num, adapter->name, addr);
147	kfree(th);
148	return -ENODEV;
149	}
150	printk(KERN_INFO "Thermostat %d (%s:%x), config: %02x\n",
151	num, adapter->name, addr, config);
152
153	rc = read_reg(th, 0, (u8 *)&t, 2);
154	if (rc < 0) {
155	printk(KERN_ERR "Thermostat %d (%s:%x) failed to read temp !\n",
156	num, adapter->name, addr);
157	kfree(th);
158	return -ENODEV;
159	}
160	printk(KERN_INFO "Thermostat %d (%s:%x), temp: %04x (about: %d degree C)\n",
161	num, adapter->name, addr, t, t>>8);
162
163	thermostats[therm_count++] = th;
164
165	if (i2c_attach_client(&th->clt)) {
166	printk(KERN_ERR "Thermostat %d (%s:%x), failed to attach client !\n",
167	num, adapter->name, addr);
168	thermostats[--therm_count] = NULL;
169	kfree(th);
170	return -ENODEV;
171	}
172
173	tlo = thi = 0;
174	rc = read_reg(th, 2, (u8 *)&tlo, 2);
175	if (rc < 0) {
176	printk(KERN_WARNING "Thermostat %d (%s:%x) failed to read low threshold !\n",
177	num, adapter->name, addr);
178	}
179	rc = read_reg(th, 3, (u8 *)&thi, 2);
180	if (rc < 0) {
181	printk(KERN_WARNING "Thermostat %d (%s:%x) failed to read high threshold !\n",
182	num, adapter->name, addr);
183	}
184	printk(KERN_INFO "Thermostat %d (%s:%x), tl: %04x (%d degree C), th: %04x (%d degree C)\n",
185	num, adapter->name, addr, tlo, tlo>>8, thi, thi>>8);
186	return 0;
187	}
188
189	static int
190	attach_thermostat(struct i2c_adapter *adapter)
191	{
192	unsigned long bus_no;
193	int rc;
194
195	if (strncmp(adapter->name, "uni-n", 5))
196	return 0;
197	bus_no = simple_strtoul(adapter->name + 6, NULL, 10);
198	rc = attach_one_thermostat(adapter, I2C_THERMOSTAT_ADDR, bus_no);
199	if (!rc && thinfo->thermostat_count > 2)
200	attach_one_thermostat(adapter, I2C_THERMOSTAT_ADDR2, bus_no+2);
201
202	return rc;
203	}
204
205	static int
206	detach_thermostat(struct i2c_client *client)
207	{
208	int index = (int)client->data;
209	struct thermostat* th;
210
211	if (index >= MAX_THERMOSTATS \|\| !thermostats[index]) {
212	printk(KERN_ERR "Invalid client in deatch_thermostat()\n");
213	return -ENODEV;
214	}
215	th = thermostats[index];
216	i2c_detach_client(&th->clt);
217	thermostats[index] = NULL;
218
219	kfree(th);
220
221	return 0;
222	}
223
224	static int __init
225	thermostat_init(void)
226	{
227	struct device_node* np;
228
229	if (!machine_is_compatible("PowerBook3,1"))
230	return -ENODEV;
231
232	np = find_devices("power-mgt");
233	if (!np)
234	return -ENODEV;
235	thinfo = (struct apple_thermal_info *)get_property(np, "thermal-info", NULL);
236	if (!thinfo)
237	return -ENODEV;
238
239	#ifdef DEBUG
240	printk(KERN_DEBUG " Thermal Infos found :\n");
241	printk(KERN_DEBUG " implementation id : %d\n", thinfo->id);
242	printk(KERN_DEBUG " fan_count : %d\n", thinfo->fan_count);
243	printk(KERN_DEBUG " thermostat_count : %d\n", thinfo->thermostat_count);
244	printk(KERN_DEBUG " ranges[0] : %d,%d\n",
245	thinfo->ranges[0].high, thinfo->ranges[0].low);
246	printk(KERN_DEBUG " ranges[1] : %d,%d\n",
247	thinfo->ranges[1].high, thinfo->ranges[1].low);
248	printk(KERN_DEBUG " ranges[2] : %d,%d\n",
249	thinfo->ranges[2].high, thinfo->ranges[2].low);
250	printk(KERN_DEBUG " ranges[3] : %d,%d\n",
251	thinfo->ranges[3].high, thinfo->ranges[3].low);
252	#endif
253	/* Check against titaniums & ibooks.... */
254	if (thinfo->id != 1 && thinfo->id != 2) {
255	printk(KERN_ERR "thermostat: design id %d unknown !\n", thinfo->id);
256	return -ENODEV;
257	}
258
259	return i2c_add_driver(&thermostat_driver);
260	}
261
262	static void __exit
263	thermostat_exit(void)
264	{
265	i2c_del_driver(&thermostat_driver);
266	}
267
268	module_init(thermostat_init);
269	module_exit(thermostat_exit);

Lines 805-818 Link Here

(-)linux-2.4.22/drivers/net/sungem.h (-30 / +22 lines)
805	u64 buffer;	805	u64 buffer;
806	};	806	};
807		807
808	#define TXDCTRL_BUFSZ 0x0000000000007fff /* Buffer Size */	808	#define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */
809	#define TXDCTRL_CSTART 0x00000000001f8000 /* CSUM Start Offset */	809	#define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */
810	#define TXDCTRL_COFF 0x000000001fe00000 /* CSUM Stuff Offset */	810	#define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */
811	#define TXDCTRL_CENAB 0x0000000020000000 /* CSUM Enable */	811	#define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
812	#define TXDCTRL_EOF 0x0000000040000000 /* End of Frame */	812	#define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */
813	#define TXDCTRL_SOF 0x0000000080000000 /* Start of Frame */	813	#define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */
814	#define TXDCTRL_INTME 0x0000000100000000 /* "Interrupt Me" */	814	#define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */
815	#define TXDCTRL_NOCRC 0x0000000200000000 /* No CRC Present */	815	#define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */
816		816
817	/* GEM requires that RX descriptors are provided four at a time,	817	/* GEM requires that RX descriptors are provided four at a time,
818	* aligned. Also, the RX ring may not wrap around. This means that	818	* aligned. Also, the RX ring may not wrap around. This means that
Lines 840-852 Link Here
840	u64 buffer;	840	u64 buffer;
841	};	841	};
842		842
843	#define RXDCTRL_TCPCSUM 0x000000000000ffff /* TCP Pseudo-CSUM */	843	#define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
844	#define RXDCTRL_BUFSZ 0x000000007fff0000 /* Buffer Size */	844	#define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */
845	#define RXDCTRL_OWN 0x0000000080000000 /* GEM owns this entry */	845	#define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */
846	#define RXDCTRL_HASHVAL 0x0ffff00000000000 /* Hash Value */	846	#define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */
847	#define RXDCTRL_HPASS 0x1000000000000000 /* Passed Hash Filter */	847	#define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */
848	#define RXDCTRL_ALTMAC 0x2000000000000000 /* Matched ALT MAC */	848	#define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
849	#define RXDCTRL_BAD 0x4000000000000000 /* Frame has bad CRC */	849	#define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */
850		850
851	#define RXDCTRL_FRESH(gp) \	851	#define RXDCTRL_FRESH(gp) \
852	((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) \| \	852	((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) \| \
Lines 936-951 Link Here
936	phy_serdes,	936	phy_serdes,
937	};	937	};
938		938
939	enum gem_phy_model {
940	phymod_generic,
941	phymod_bcm5201,
942	phymod_bcm5221,
943	phymod_bcm5400,
944	phymod_bcm5401,
945	phymod_bcm5411,
946	phymod_m1011,
947	};
948
949	enum link_state {	939	enum link_state {
950	link_down = 0, /* No link, will retry */	940	link_down = 0, /* No link, will retry */
951	link_aneg, /* Autoneg in progress */	941	link_aneg, /* Autoneg in progress */
Lines 980-1000 Link Here
980	struct net_device_stats net_stats;	970	struct net_device_stats net_stats;
981		971
982	enum gem_phy_type phy_type;	972	enum gem_phy_type phy_type;
983	enum gem_phy_model phy_mod;	973	struct mii_phy phy_mii;
		974
984	int tx_fifo_sz;	975	int tx_fifo_sz;
985	int rx_fifo_sz;	976	int rx_fifo_sz;
986	int rx_pause_off;	977	int rx_pause_off;
987	int rx_pause_on;	978	int rx_pause_on;
988	int mii_phy_addr;	979	int mii_phy_addr;
989	int gigabit_capable;
990		980
991	u32 mac_rx_cfg;	981	u32 mac_rx_cfg;
992	u32 swrst_base;	982	u32 swrst_base;
993		983
994	/* Autoneg & PHY control */	984	/* Autoneg & PHY control */
995	int link_cntl;	985	int want_autoneg;
996	int link_advertise;	986	int last_forced_speed;
997	int link_fcntl;
998	enum link_state lstate;	987	enum link_state lstate;
999	struct timer_list link_timer;	988	struct timer_list link_timer;
1000	int timer_ticks;	989	int timer_ticks;
Lines 1014-1019 Link Here
1014	#endif	1003	#endif
1015	};	1004	};
1016		1005
		1006	#define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 \|\| gp->phy_type == phy_mii_mdio1) \
		1007	&& gp->phy_mii.def && gp->phy_mii.def->ops)
		1008
1017	#define ALIGNED_RX_SKB_ADDR(addr) \	1009	#define ALIGNED_RX_SKB_ADDR(addr) \
1018	((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))	1010	((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
1019	static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)	1011	static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)

Line 0 Link Here

(-)linux-2.4.22/drivers/net/sungem_phy.h (+116 lines)
		1	#ifndef __SUNGEM_PHY_H__
		2	#define __SUNGEM_PHY_H__
		3
		4	struct mii_phy;
		5
		6	/* Operations supported by any kind of PHY */
		7	struct mii_phy_ops
		8	{
		9	int (init)(struct mii_phy phy);
		10	int (suspend)(struct mii_phy phy, int wol_options);
		11	int (setup_aneg)(struct mii_phy phy, u32 advertise);
		12	int (setup_forced)(struct mii_phy phy, int speed, int fd);
		13	int (poll_link)(struct mii_phy phy);
		14	int (read_link)(struct mii_phy phy);
		15	};
		16
		17	/* Structure used to statically define an mii/gii based PHY */
		18	struct mii_phy_def
		19	{
		20	u32 phy_id; /* Concatenated ID1 << 16 \| ID2 */
		21	u32 phy_id_mask; /* Significant bits */
		22	u32 features; /* Ethtool SUPPORTED_* defines */
		23	int magic_aneg; /* Autoneg does all speed test for us */
		24	const char* name;
		25	const struct mii_phy_ops* ops;
		26	};
		27
		28	/* An instance of a PHY, partially borrowed from mii_if_info */
		29	struct mii_phy
		30	{
		31	struct mii_phy_def* def;
		32	int advertising;
		33	int mii_id;
		34
		35	/* 1: autoneg enabled, 0: disabled */
		36	int autoneg;
		37
		38	/* forced speed & duplex (no autoneg)
		39	* partner speed & duplex & pause (autoneg)
		40	*/
		41	int speed;
		42	int duplex;
		43	int pause;
		44
		45	/* Provided by host chip */
		46	struct net_device* dev;
		47	int (mdio_read) (struct net_device dev, int mii_id, int reg);
		48	void (mdio_write) (struct net_device dev, int mii_id, int reg, int val);
		49	};
		50
		51	/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
		52	* filled, the remaining fields will be filled on return
		53	*/
		54	extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
		55
		56
		57	/* MII definitions missing from mii.h */
		58
		59	#define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
		60	#define LPA_PAUSE 0x0400
		61
		62	/* More PHY registers (model specific) */
		63
		64	/* MII BCM5201 MULTIPHY interrupt register */
65	#define MII_BCM5201_INTERRUPT 0x1A
66	#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
67
68	#define MII_BCM5201_AUXMODE2 0x1B
69	#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
70
71	#define MII_BCM5201_MULTIPHY 0x1E
72
73	/* MII BCM5201 MULTIPHY register bits */
74	#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
75	#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
76
77	/* MII BCM5221 Additional registers */
78	#define MII_BCM5221_TEST 0x1f
79	#define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
80	#define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
81	#define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
82	#define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
83	#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
84
85	/* MII BCM5400 1000-BASET Control register */
86	#define MII_BCM5400_GB_CONTROL 0x09
87	#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
88
89	/* MII BCM5400 AUXCONTROL register */
90	#define MII_BCM5400_AUXCONTROL 0x18
91	#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
92
93	/* MII BCM5400 AUXSTATUS register */
94	#define MII_BCM5400_AUXSTATUS 0x19
95	#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
96	#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
97
98	/* 1000BT control (Marvell & BCM54xx at least) */
99	#define MII_1000BASETCONTROL 0x09
100	#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
101	#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
102
103	/* Marvell 88E1011 PHY control */
104	#define MII_M1011_PHY_SPEC_CONTROL 0x10
105	#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
106	#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
107
108	/* Marvell 88E1011 PHY status */
109	#define MII_M1011_PHY_SPEC_STATUS 0x11
110	#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
111	#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
112	#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
113	#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
114	#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
115
116	#endif /* __SUNGEM_PHY_H__ */

Lines 168-175 Link Here

(-)linux-2.4.22/drivers/sound/dmasound/awacs_defs.h (-1 / +17 lines)
168		168
169	#define RATE_LOW 1 /* HIGH = 48kHz, etc; LOW = 44.1kHz, etc. */	169	#define RATE_LOW 1 /* HIGH = 48kHz, etc; LOW = 44.1kHz, etc. */
170		170
171		171	/*******************/
172	/* Burgundy values */	172	/* Burgundy values */
		173	/*******************/
173		174
174	#define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)	175	#define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)
175	#define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)	176	#define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)
Lines 232-235 Link Here
232	#define DEF_BURGUNDY_ATTENLINEOUT (0xCC)	233	#define DEF_BURGUNDY_ATTENLINEOUT (0xCC)
233	#define DEF_BURGUNDY_ATTENHP (0xCC)	234	#define DEF_BURGUNDY_ATTENHP (0xCC)
234		235
		236	/*********************/
		237	/* i2s layout values */
		238	/*********************/
		239
		240	#define I2S_REG_INT_CTL 0x00
		241	#define I2S_REG_SERIAL_FORMAT 0x10
		242	#define I2S_REG_CODEC_MSG_OUT 0x20
		243	#define I2S_REG_CODEC_MSG_IN 0x30
		244	#define I2S_REG_FRAME_COUNT 0x40
		245	#define I2S_REG_FRAME_MATCH 0x50
		246	#define I2S_REG_DATAWORD_SIZES 0x60
		247	#define I2S_REG_PEAKLEVEL_SEL 0x70
		248	#define I2S_REG_PEAKLEVEL_IN0 0x80
		249	#define I2S_REG_PEAKLEVEL_IN1 0x90
		250
235	#endif /* _AWACS_DEFS_H_ */	251	#endif /* _AWACS_DEFS_H_ */

Lines 1-5 Link Here

(-)linux-2.4.22/drivers/sound/dmasound/tas3001c.h (-227 / +43 lines)
1	/*	1	/*
2	* Header file for the i2c/i2s based TA3001C sound chip used	2	* Header file for the i2c/i2s based TA3001c sound chip used
3	* on some Apple hardware. Also known as "tumbler".	3	* on some Apple hardware. Also known as "tumbler".
4	*	4	*
5	* This file is subject to the terms and conditions of the GNU General Public	5	* This file is subject to the terms and conditions of the GNU General Public
Lines 9-248 Link Here
9	* Written by Christopher C. Chimelis <chris@debian.org>	9	* Written by Christopher C. Chimelis <chris@debian.org>
10	*/	10	*/
11		11
12	#ifndef _tas3001c_h_	12	#ifndef _TAS3001C_H_
13	#define _tas3001c_h_	13	#define _TAS3001C_H_
14		14
15	/*	15	#include <linux/types.h>
16	* Macros that correspond to the registers that we write to
17	* when setting the various values.
18	*/
19	#define TAS_DRC 0x02 /* DRC */
20	#define TAS_VOLUME 0x04 /* Volume */
21	#define TAS_TREBLE 0x05 /* Treble */
22	#define TAS_BASS 0x06 /* Bass */
23	#define TAS_MIXER1 0x07 /* PCM line */
24	#define TAS_MIXER2 0x08 /* Input (Unk) */
25
26	/*
27	* Macros that define various arguments to tas_set_register()
28	*/
29	#define TAS_SET_DRC TAS_DRC, 2
30	#define TAS_SET_VOLUME TAS_VOLUME, 6
31	#define TAS_SET_TREBLE TAS_TREBLE, 1
32	#define TAS_SET_BASS TAS_BASS, 1
33	#define TAS_SET_MIXER1 TAS_MIXER1, 3
34	#define TAS_SET_MIXER2 TAS_MIXER2, 3
35		16
		17	#include "tas_common.h"
		18	#include "tas_eq_prefs.h"
36		19
37	/*	20	/*
38	* tas_volume_table contains lookup values for the volume settings	21	* Macros that correspond to the registers that we write to
39	* for tumbler. This is straight from the programming manual	22	* when setting the various values.
40	* for the chip, however, it's zero-sourced for your shopping pleasure
41	* (meaning, you'll have to compute the difference between the desired
42	* dB and the index value of the proper setting.
43	*
44	* This table should've been replaced by the formula:
45	* dB = 20 log(x)
46	* but, since there's no log() or supporting functions like exp(),
47	* my implementation of the above won't work. Yeah, I could do it
48	* the hard way, but this table is just easier :-)
49	*
50	* For reference, -70 dB = tas_volume_table[0]
51	*/	23	*/
52		24
53	static unsigned int tas_volume_table[] = {	25	#define TAS3001C_VERSION "0.3"
54	0x00000015, 0x00000016, 0x00000017, /* -70.0, -69.5, -69.0 */	26	#define TAS3001C_DATE "20011214"
55	0x00000019, 0x0000001a, 0x0000001c, /* -68.5, -68.0, -67.5 */
56	0x0000001d, 0x0000001f, 0x00000021, /* -67.0, -66.5, -66.0 */
57	0x00000023, 0x00000025, 0x00000027, /* -65.5, -65.0, -64.5 */
58	0x00000029, 0x0000002c, 0x0000002e, /* -64.0, -63.5, -63.0 */
59	0x00000031, 0x00000034, 0x00000037, /* -62.5, -62.0, -61.5 */
60	0x0000003a, 0x0000003e, 0x00000042, /* -61.0, -60.5, -60.0 */
61	0x00000045, 0x0000004a, 0x0000004e, /* -59.5, -59.0, -58.5 */
62	0x00000053, 0x00000057, 0x0000005d, /* -58.0, -57.5, -57.0 */
63	0x00000062, 0x00000068, 0x0000006e, /* -56.5, -56.0, -55.5 */
64	0x00000075, 0x0000007b, 0x00000083, /* -55.0, -54.5, -54.0 */
65	0x0000008b, 0x00000093, 0x0000009b, /* -53.5, -53.0, -52.5 */
66	0x000000a5, 0x000000ae, 0x000000b9, /* -52.0, -51.5, -51.0 */
67	0x000000c4, 0x000000cf, 0x000000dc, /* -50.5, -50.0, -49.5 */
68	0x000000e9, 0x000000f6, 0x00000105, /* -49.0, -48.5, -48.0 */
69	0x00000114, 0x00000125, 0x00000136, /* -47.5, -47.0, -46.5 */
70	0x00000148, 0x0000015c, 0x00000171, /* -46.0, -45.5, -45.0 */
71	0x00000186, 0x0000019e, 0x000001b6, /* -44.5, -44.0, -43.5 */
72	0x000001d0, 0x000001eb, 0x00000209, /* -43.0, -42.5, -42.0 */
73	0x00000227, 0x00000248, 0x0000026b, /* -41.5, -41.0, -40.5 */
74	0x0000028f, 0x000002b6, 0x000002df, /* -40.0, -39.5, -39.0 */
75	0x0000030b, 0x00000339, 0x0000036a, /* -38.5, -38.0, -37.5 */
76	0x0000039e, 0x000003d5, 0x0000040f, /* -37.0, -36.5, -36.0 */
77	0x0000044c, 0x0000048d, 0x000004d2, /* -35.5, -35.0, -34.5 */
78	0x0000051c, 0x00000569, 0x000005bb, /* -34.0, -33.5, -33.0 */
79	0x00000612, 0x0000066e, 0x000006d0, /* -32.5, -32.0, -31.5 */
80	0x00000737, 0x000007a5, 0x00000818, /* -31.0, -30.5, -30.0 */
81	0x00000893, 0x00000915, 0x0000099f, /* -29.5, -29.0, -28.5 */
82	0x00000a31, 0x00000acc, 0x00000b6f, /* -28.0, -27.5, -27.0 */
83	0x00000c1d, 0x00000cd5, 0x00000d97, /* -26.5, -26.0, -25.5 */
84	0x00000e65, 0x00000f40, 0x00001027, /* -25.0, -24.5, -24.0 */
85	0x0000111c, 0x00001220, 0x00001333, /* -23.5, -23.0, -22.5 */
86	0x00001456, 0x0000158a, 0x000016d1, /* -22.0, -21.5, -21.0 */
87	0x0000182b, 0x0000199a, 0x00001b1e, /* -20.5, -20.0, -19.5 */
88	0x00001cb9, 0x00001e6d, 0x0000203a, /* -19.0, -18.5, -18.0 */
89	0x00002223, 0x00002429, 0x0000264e, /* -17.5, -17.0, -16.5 */
90	0x00002893, 0x00002afa, 0x00002d86, /* -16.0, -15.5, -15.0 */
91	0x00003039, 0x00003314, 0x0000361b, /* -14.5, -14.0, -13.5 */
92	0x00003950, 0x00003cb5, 0x0000404e, /* -13.0, -12.5, -12.0 */
93	0x0000441d, 0x00004827, 0x00004c6d, /* -11.5, -11.0, -10.5 */
94	0x000050f4, 0x000055c0, 0x00005ad5, /* -10.0, -09.5, -09.0 */
95	0x00006037, 0x000065ea, 0x00006bf4, /* -08.5, -08.0, -07.5 */
96	0x0000725a, 0x00007920, 0x0000804e, /* -07.0, -06.5, -06.0 */
97	0x000087e8, 0x00008ff6, 0x0000987d, /* -05.5, -05.0, -04.5 */
98	0x0000a186, 0x0000ab19, 0x0000b53c, /* -04.0, -03.5, -03.0 */
99	0x0000bff9, 0x0000cb59, 0x0000d766, /* -02.5, -02.0, -01.5 */
100	0x0000e429, 0x0000f1ae, 0x00010000, /* -01.0, -00.5, 00.0 */
101	0x00010f2b, 0x00011f3d, 0x00013042, /* +00.5, +01.0, +01.5 */
102	0x00014249, 0x00015562, 0x0001699c, /* +02.0, +02.5, +03.0 */
103	0x00017f09, 0x000195bc, 0x0001adc6, /* +03.5, +04.0, +04.5 */
104	0x0001c73d, 0x0001e237, 0x0001feca, /* +05.0, +05.5, +06.0 */
105	0x00021d0e, 0x00023d1d, 0x00025f12, /* +06.5, +07.0, +07.5 */
106	0x0002830b, 0x0002a925, 0x0002d182, /* +08.0, +08.5, +09.0 */
107	0x0002fc42, 0x0003298b, 0x00035983, /* +09.5, +10.0, +10.5 */
108	0x00038c53, 0x0003c225, 0x0003fb28, /* +11.0, +11.5, +12.0 */
109	0x0004378b, 0x00047783, 0x0004bb44, /* +12.5, +13.0, +13.5 */
110	0x0005030a, 0x00054f10, 0x00059f98, /* +14.0, +14.5, +15.0 */
111	0x0005f4e5, 0x00064f40, 0x0006aef6, /* +15.5, +16.0, +16.5 */
112	0x00071457, 0x00077fbb, 0x0007f17b /* +17.0, +17.5, +18.0 */
113	};
114		27
115	/* tas_treble_table[] is a lookup table that holds the values to drop into	28	#define I2C_DRIVERNAME_TAS3001C "TAS3001c driver V " TAS3001C_VERSION
116	* the treble setting register on the TAS. Again, there is a formula for	29	#define I2C_DRIVERID_TAS3001C (I2C_DRIVERID_TAS_BASE+0)
117	* this one, but we use this instead due to lack of real math functions
118	* in the kernel.
119	*/
120	static char tas_treble_table[] = {
121	0x96, 0x95, 0x94, /* -18.0, -17.5, -17.0 */
122	0x93, 0x92, 0x91, /* -16.5, -16.0, -15.5 */
123	0x90, 0x8f, 0x8e, /* -15.0, -14.5, -14.0 */
124	0x8d, 0x8c, 0x8b, /* -13.5, -13.0, -12.5 */
125	0x8a, 0x89, 0x88, /* -12.0, -11.5, -11.0 */
126	0x87, 0x86, 0x85, /* -10.5, -10.0, -09.5 */
127	0x84, 0x83, 0x82, /* -09.0, -08.5, -08.0 */
128	0x81, 0x80, 0x7f, /* -07.5, -07.0, -06.5 */
129	0x7e, 0x7d, 0x7c, /* -06.0, -05.5, -05.0 */
130	0x7b, 0x7a, 0x79, /* -04.5, -04.0, -03.5 */
131	0x78, 0x77, 0x76, /* -03.0, -02.5, -02.0 */
132	0x75, 0x74, 0x73, /* -01.5, -01.0, -00.5 */
133	0x72, 0x71, 0x70, /* 00.0, +00.5, +01.0 */
134	0x6e, 0x6d, 0x6c, /* +01.5, +02.0, +02.5 */
135	0x6b, 0x69, 0x68, /* +03.0, +03.5, +04.0 */
136	0x66, 0x65, 0x63, /* +04.5, +05.0, +05.5 */
137	0x62, 0x60, 0x5e, /* +06.0, +06.5, +07.0 */
138	0x5c, 0x5a, 0x57, /* +07.5, +08.0, +08.5 */
139	0x55, 0x52, 0x4f, /* +09.0, +09.5, +10.0 */
140	0x4c, 0x49, 0x45, /* +10.5, +11.0, +11.5 */
141	0x42, 0x3e, 0x3a, /* +12.0, +12.5, +13.0 */
142	0x36, 0x32, 0x2d, /* +13.5, +14.0, +14.5 */
143	0x28, 0x22, 0x1c, /* +15.0, +15.5, +16.0 */
144	0x16, 0x10, 0x09, /* +16.5, +17.0, +17.5 */
145	0x01 /* +18.0 */
146	};
147		30
148	/* tas_bass_table[] is a lookup table that holds the values to drop into	31	extern struct tas_driver_hooks_t tas3001c_hooks;
149	* the bass setting register on the TAS. Again, there is a formula for	32	extern struct tas_gain_t tas3001c_gain;
150	* this one, but we use this instead due to lack of real math functions	33	extern struct tas_eq_pref_t *tas3001c_eq_prefs[];
151	* in the kernel.	34
152	*/	35	enum tas3001c_reg_t {
153	static char tas_bass_table[] = {	36	TAS3001C_REG_MCR = 0x01,
154	0x86, 0x82, 0x7f, /* -18.0, -17.5, -17.0 */	37	TAS3001C_REG_DRC = 0x02,
155	0x7d, 0x7a, 0x78, /* -16.5, -16.0, -15.5 */	38
156	0x76, 0x74, 0x72, /* -15.0, -14.5, -14.0 */	39	TAS3001C_REG_VOLUME = 0x04,
157	0x70, 0x6e, 0x6d, /* -13.5, -13.0, -12.5 */	40	TAS3001C_REG_TREBLE = 0x05,
158	0x6b, 0x69, 0x66, /* -12.0, -11.5, -11.0 */	41	TAS3001C_REG_BASS = 0x06,
159	0x64, 0x61, 0x5f, /* -10.5, -10.0, -09.5 */	42	TAS3001C_REG_MIXER1 = 0x07,
160	0x5d, 0x5c, 0x5a, /* -09.0, -08.5, -08.0 */	43	TAS3001C_REG_MIXER2 = 0x08,
161	0x59, 0x58, 0x56, /* -07.5, -07.0, -06.5 */	44
162	0x55, 0x54, 0x53, /* -06.0, -05.5, -05.0 */	45	TAS3001C_REG_LEFT_BIQUAD0 = 0x0a,
163	0x51, 0x4f, 0x4d, /* -04.5, -04.0, -03.5 */	46	TAS3001C_REG_LEFT_BIQUAD1 = 0x0b,
164	0x4b, 0x49, 0x46, /* -03.0, -02.5, -02.0 */	47	TAS3001C_REG_LEFT_BIQUAD2 = 0x0c,
165	0x44, 0x42, 0x40, /* -01.5, -01.0, -00.5 */	48	TAS3001C_REG_LEFT_BIQUAD3 = 0x0d,
166	0x3e, 0x3c, 0x3b, /* 00.0, +00.5, +01.0 */	49	TAS3001C_REG_LEFT_BIQUAD4 = 0x0e,
167	0x39, 0x38, 0x36, /* +01.5, +02.0, +02.5 */	50	TAS3001C_REG_LEFT_BIQUAD5 = 0x0f,
168	0x35, 0x33, 0x31, /* +03.0, +03.5, +04.0 */	51	TAS3001C_REG_LEFT_BIQUAD6 = 0x10,
169	0x30, 0x2e, 0x2c, /* +04.5, +05.0, +05.5 */	52
170	0x2b, 0x29, 0x28, /* +06.0, +06.5, +07.0 */	53	TAS3001C_REG_RIGHT_BIQUAD0 = 0x13,
171	0x26, 0x25, 0x23, /* +07.5, +08.0, +08.5 */	54	TAS3001C_REG_RIGHT_BIQUAD1 = 0x14,
172	0x21, 0x1f, 0x1c, /* +09.0, +09.5, +10.0 */	55	TAS3001C_REG_RIGHT_BIQUAD2 = 0x15,
173	0x19, 0x18, 0x17, /* +10.5, +11.0, +11.5 */	56	TAS3001C_REG_RIGHT_BIQUAD3 = 0x16,
174	0x16, 0x14, 0x13, /* +12.0, +12.5, +13.0 */	57	TAS3001C_REG_RIGHT_BIQUAD4 = 0x17,
175	0x12, 0x10, 0x0f, /* +13.5, +14.0, +14.5 */	58	TAS3001C_REG_RIGHT_BIQUAD5 = 0x18,
176	0x0d, 0x0b, 0x0a, /* +15.0, +15.5, +16.0 */	59	TAS3001C_REG_RIGHT_BIQUAD6 = 0x19,
177	0x08, 0x06, 0x03, /* +16.5, +17.0, +17.5 */
178	0x01 /* +18.0 */
179	};
180		60
181	/* tas_input_table[] is a lookup table that holds the values to drop into	61	TAS3001C_REG_MAX = 0x20
182	* the setting registers on the TAS for "mixers 1 & 2" (which are the input
183	* lines). Again, there is a formula for these, but we use this instead
184	* due to lack of real math functions in the kernel.
185	*/
186	static unsigned int tas_input_table[] = {
187	0x00014b, 0x00015f, 0x000174, /* -70.0, -69.5, -69.0 */
188	0x00018a, 0x0001a1, 0x0001ba, /* -68.5, -68.0, -67.5 */
189	0x0001d4, 0x0001f0, 0x00020d, /* -67.0, -66.5, -66.0 */
190	0x00022c, 0x00024d, 0x000270, /* -65.5, -65.0, -64.5 */
191	0x000295, 0x0002bc, 0x0002e6, /* -64.0, -63.5, -63.0 */
192	0x000312, 0x000340, 0x000372, /* -62.5, -62.0, -61.5 */
193	0x0003a6, 0x0003dd, 0x000418, /* -61.0, -60.5, -60.0 */
194	0x000456, 0x000498, 0x0004de, /* -59.5, -59.0, -58.5 */
195	0x000528, 0x000576, 0x0005c9, /* -58.0, -57.5, -57.0 */
196	0x000620, 0x00067d, 0x0006e0, /* -56.5, -56.0, -55.5 */
197	0x000748, 0x0007b7, 0x00082c, /* -55.0, -54.5, -54.0 */
198	0x0008a8, 0x00092b, 0x0009b6, /* -53.5, -53.0, -52.5 */
199	0x000a49, 0x000ae5, 0x000b8b, /* -52.0, -51.5, -51.0 */
200	0x000c3a, 0x000cf3, 0x000db8, /* -50.5, -50.0, -49.5 */
201	0x000e88, 0x000f64, 0x00104e, /* -49.0, -48.5, -48.0 */
202	0x001145, 0x00124b, 0x001361, /* -47.5, -47.0, -46.5 */
203	0x001487, 0x0015be, 0x001708, /* -46.0, -45.5, -45.0 */
204	0x001865, 0x0019d8, 0x001b60, /* -44.5, -44.0, -43.5 */
205	0x001cff, 0x001eb7, 0x002089, /* -43.0, -42.5, -42.0 */
206	0x002276, 0x002481, 0x0026ab, /* -41.5, -41.0, -40.5 */
207	0x0028f5, 0x002b63, 0x002df5, /* -40.0, -39.5, -39.0 */
208	0x0030ae, 0x003390, 0x00369e, /* -38.5, -38.0, -37.5 */
209	0x0039db, 0x003d49, 0x0040ea, /* -37.0, -36.5, -36.0 */
210	0x0044c3, 0x0048d6, 0x004d27, /* -35.5, -35.0, -34.5 */
211	0x0051b9, 0x005691, 0x005bb2, /* -34.0, -33.5, -33.0 */
212	0x006121, 0x0066e3, 0x006cfb, /* -32.5, -32.0, -31.5 */
213	0x007370, 0x007a48, 0x008186, /* -31.0, -30.5, -30.0 */
214	0x008933, 0x009154, 0x0099f1, /* -29.5, -29.0, -28.5 */
215	0x00a310, 0x00acba, 0x00b6f6, /* -28.0, -27.5, -27.0 */
216	0x00c1cd, 0x00cd49, 0x00d973, /* -26.5, -26.0, -25.5 */
217	0x00e655, 0x00f3fb, 0x010270, /* -25.0, -24.5, -24.0 */
218	0x0111c0, 0x0121f9, 0x013328, /* -23.5, -23.0, -22.5 */
219	0x01455b, 0x0158a2, 0x016d0e, /* -22.0, -21.5, -21.0 */
220	0x0182af, 0x019999, 0x01b1de, /* -20.5, -20.0, -19.5 */
221	0x01cb94, 0x01e6cf, 0x0203a7, /* -19.0, -18.5, -18.0 */
222	0x022235, 0x024293, 0x0264db, /* -17.5, -17.0, -16.5 */
223	0x02892c, 0x02afa3, 0x02d862, /* -16.0, -15.5, -15.0 */
224	0x03038a, 0x033142, 0x0361af, /* -14.5, -14.0, -13.5 */
225	0x0394fa, 0x03cb50, 0x0404de, /* -13.0, -12.5, -12.0 */
226	0x0441d5, 0x048268, 0x04c6d0, /* -11.5, -11.0, -10.5 */
227	0x050f44, 0x055c04, 0x05ad50, /* -10.0, -09.5, -09.0 */
228	0x06036e, 0x065ea5, 0x06bf44, /* -08.5, -08.0, -07.5 */
229	0x07259d, 0x079207, 0x0804dc, /* -07.0, -06.5, -06.0 */
230	0x087e80, 0x08ff59, 0x0987d5, /* -05.5, -05.0, -04.5 */
231	0x0a1866, 0x0ab189, 0x0b53be, /* -04.0, -03.5, -03.0 */
232	0x0bff91, 0x0cb591, 0x0d765a, /* -02.5, -02.0, -01.5 */
233	0x0e4290, 0x0f1adf, 0x100000, /* -01.0, -00.5, 00.0 */
234	0x10f2b4, 0x11f3c9, 0x13041a, /* +00.5, +01.0, +01.5 */
235	0x14248e, 0x15561a, 0x1699c0, /* +02.0, +02.5, +03.0 */
236	0x17f094, 0x195bb8, 0x1adc61, /* +03.5, +04.0, +04.5 */
237	0x1c73d5, 0x1e236d, 0x1fec98, /* +05.0, +05.5, +06.0 */
238	0x21d0d9, 0x23d1cd, 0x25f125, /* +06.5, +07.0, +07.5 */
239	0x2830af, 0x2a9254, 0x2d1818, /* +08.0, +08.5, +09.0 */
240	0x2fc420, 0x3298b0, 0x35982f, /* +09.5, +10.0, +10.5 */
241	0x38c528, 0x3c224c, 0x3fb278, /* +11.0, +11.5, +12.0 */
242	0x437880, 0x477828, 0x4bb446, /* +12.5, +13.0, +13.5 */
243	0x5030a1, 0x54f106, 0x59f980, /* +14.0, +14.5, +15.0 */
244	0x5f4e52, 0x64f403, 0x6aef5d, /* +15.5, +16.0, +16.5 */
245	0x714575, 0x77fbaa, 0x7f17af /* +17.0, +17.5, +18.0 */
246	};	62	};
247		63
248	#endif /* _tas3001c_h_ */	64	#endif /* _TAS3001C_H_ */