Attachment #219403 for bug #304811

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	return 0;
#endif
}

/**
 * r600_iotcl_wait_idle - flush host path cache on wait idle ioctl
 * rdev: radeon device structure
 * bo: buffer object struct which userspace is waiting for idle
 *
 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
 * through ring buffer, this leads to corruption in rendering, see
 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
 * directly perform HDP flush by writing register through MMIO.
 */
#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL		0x5480
void r600_iotcl_wait_idle(struct radeon_device *rdev, struct radeon_object *robj)
{
	WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
}




	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &r100_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};

/*

	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &r100_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};



	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &r100_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};



	.set_pcie_lanes = NULL,
	.set_clock_gating = &radeon_atom_set_clock_gating,
	.bandwidth_update = &rs600_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};



	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &rs690_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};



	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &rv515_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};



	.set_surface_reg = r100_set_surface_reg,
	.clear_surface_reg = r100_clear_surface_reg,
	.bandwidth_update = &rv515_bandwidth_update,
       	.ioctl_wait_idle = NULL,
};

/*

int r600_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset, uint64_t dst_offset,
		   unsigned num_pages, struct radeon_fence *fence);
extern void r600_iotcl_wait_idle(struct radeon_device *rdev, struct radeon_object *bo);

static struct radeon_asic r600_asic = {
	.init = &r600_init,

	.set_surface_reg = r600_set_surface_reg,
	.clear_surface_reg = r600_clear_surface_reg,
	.bandwidth_update = &rv515_bandwidth_update,
       	.ioctl_wait_idle = r600_iotcl_wait_idle,
};

/*

	.set_surface_reg = r600_set_surface_reg,
	.clear_surface_reg = r600_clear_surface_reg,
	.bandwidth_update = &rv515_bandwidth_update,
       	.ioctl_wait_idle = r600_iotcl_wait_idle,
};

#endif

Lines 306-311 int radeon_gem_wait_idle_ioctl(struct dr Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/radeon_gem.c (+3 lines)
306	}	306	}
307	robj = gobj->driver_private;	307	robj = gobj->driver_private;
308	r = radeon_object_wait(robj);	308	r = radeon_object_wait(robj);
		309	/* callback hw specific functions if any */
		310	if (robj->rdev->asic->ioctl_wait_idle)
		311	robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
309	mutex_lock(&dev->struct_mutex);	312	mutex_lock(&dev->struct_mutex);
310	drm_gem_object_unreference(gobj);	313	drm_gem_object_unreference(gobj);
311	mutex_unlock(&dev->struct_mutex);	314	mutex_unlock(&dev->struct_mutex);

Lines 639-644 struct radeon_asic { Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/radeon.h (+7 lines)
639	uint32_t offset, uint32_t obj_size);	639	uint32_t offset, uint32_t obj_size);
640	int (clear_surface_reg)(struct radeon_device rdev, int reg);	640	int (clear_surface_reg)(struct radeon_device rdev, int reg);
641	void (bandwidth_update)(struct radeon_device rdev);	641	void (bandwidth_update)(struct radeon_device rdev);
		642	/* ioctl hw specific callback. Some hw might want to perform special
		643	* operation on specific ioctl. For instance on wait idle some hw
		644	* might want to perform and HDP flush through MMIO as it seems that
		645	* some R6XX/R7XX hw doesn't take HDP flush into account if programmed
		646	* through ring.
		647	*/
		648	void (ioctl_wait_idle)(struct radeon_device rdev, struct radeon_object *robj);
642	};	649	};
643		650
644	/*	651	/*




#include "radeon_drm.h"
#include "radeon.h"

struct radeon_object {
	struct ttm_buffer_object	tobj;
	struct list_head		list;
	struct radeon_device		*rdev;
	struct drm_gem_object		*gobj;
	struct ttm_bo_kmap_obj		kmap;
	unsigned			pin_count;
	uint64_t			gpu_addr;
	void				*kptr;
	bool				is_iomem;
	uint32_t			tiling_flags;
	uint32_t			pitch;
	int				surface_reg;
};

int radeon_ttm_init(struct radeon_device *rdev);
void radeon_ttm_fini(struct radeon_device *rdev);




	struct ttm_bo_device		bdev;
};

struct radeon_object {
	struct ttm_buffer_object	tobj;
	struct list_head		list;
	struct radeon_device		*rdev;
	struct drm_gem_object		*gobj;
	struct ttm_bo_kmap_obj		kmap;
	unsigned			pin_count;
	uint64_t			gpu_addr;
	void				*kptr;
	bool				is_iomem;
	uint32_t			tiling_flags;
	uint32_t			pitch;
	int				surface_reg;
};

#endif

Return to bug 304811

Lines 1855-1857 int r600_debugfs_mc_info_init(struct rad Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/r600.c (+16 lines)
1855	return 0;	1855	return 0;
1856	#endif	1856	#endif
1857	}	1857	}
		1858
		1859	/**
		1860	* r600_iotcl_wait_idle - flush host path cache on wait idle ioctl
		1861	* rdev: radeon device structure
		1862	* bo: buffer object struct which userspace is waiting for idle
		1863	*
		1864	* Some R6XX/R7XX doesn't seems to take into account HDP flush performed
		1865	* through ring buffer, this leads to corruption in rendering, see
		1866	* http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
		1867	* directly perform HDP flush by writing register through MMIO.
		1868	*/
		1869	#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
		1870	void r600_iotcl_wait_idle(struct radeon_device rdev, struct radeon_object robj)
		1871	{
		1872	WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
		1873	}

Lines 162-167 static struct radeon_asic r300_asic = { Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/radeon_asic.h (+10 lines)
162	.set_surface_reg = r100_set_surface_reg,	162	.set_surface_reg = r100_set_surface_reg,
163	.clear_surface_reg = r100_clear_surface_reg,	163	.clear_surface_reg = r100_clear_surface_reg,
164	.bandwidth_update = &r100_bandwidth_update,	164	.bandwidth_update = &r100_bandwidth_update,
		165	.ioctl_wait_idle = NULL,
165	};	166	};
166		167
167	/*	168	/*
Lines 201-206 static struct radeon_asic r420_asic = { Link Here
201	.set_surface_reg = r100_set_surface_reg,	202	.set_surface_reg = r100_set_surface_reg,
202	.clear_surface_reg = r100_clear_surface_reg,	203	.clear_surface_reg = r100_clear_surface_reg,
203	.bandwidth_update = &r100_bandwidth_update,	204	.bandwidth_update = &r100_bandwidth_update,
		205	.ioctl_wait_idle = NULL,
204	};	206	};
205		207
206		208
Lines 245-250 static struct radeon_asic rs400_asic = { Link Here
245	.set_surface_reg = r100_set_surface_reg,	247	.set_surface_reg = r100_set_surface_reg,
246	.clear_surface_reg = r100_clear_surface_reg,	248	.clear_surface_reg = r100_clear_surface_reg,
247	.bandwidth_update = &r100_bandwidth_update,	249	.bandwidth_update = &r100_bandwidth_update,
		250	.ioctl_wait_idle = NULL,
248	};	251	};
249		252
250		253
Lines 291-296 static struct radeon_asic rs600_asic = { Link Here
291	.set_pcie_lanes = NULL,	294	.set_pcie_lanes = NULL,
292	.set_clock_gating = &radeon_atom_set_clock_gating,	295	.set_clock_gating = &radeon_atom_set_clock_gating,
293	.bandwidth_update = &rs600_bandwidth_update,	296	.bandwidth_update = &rs600_bandwidth_update,
		297	.ioctl_wait_idle = NULL,
294	};	298	};
295		299
296		300
Lines 334-339 static struct radeon_asic rs690_asic = { Link Here
334	.set_surface_reg = r100_set_surface_reg,	338	.set_surface_reg = r100_set_surface_reg,
335	.clear_surface_reg = r100_clear_surface_reg,	339	.clear_surface_reg = r100_clear_surface_reg,
336	.bandwidth_update = &rs690_bandwidth_update,	340	.bandwidth_update = &rs690_bandwidth_update,
		341	.ioctl_wait_idle = NULL,
337	};	342	};
338		343
339		344
Lines 381-386 static struct radeon_asic rv515_asic = { Link Here
381	.set_surface_reg = r100_set_surface_reg,	386	.set_surface_reg = r100_set_surface_reg,
382	.clear_surface_reg = r100_clear_surface_reg,	387	.clear_surface_reg = r100_clear_surface_reg,
383	.bandwidth_update = &rv515_bandwidth_update,	388	.bandwidth_update = &rv515_bandwidth_update,
		389	.ioctl_wait_idle = NULL,
384	};	390	};
385		391
386		392
Lines 419-424 static struct radeon_asic r520_asic = { Link Here
419	.set_surface_reg = r100_set_surface_reg,	425	.set_surface_reg = r100_set_surface_reg,
420	.clear_surface_reg = r100_clear_surface_reg,	426	.clear_surface_reg = r100_clear_surface_reg,
421	.bandwidth_update = &rv515_bandwidth_update,	427	.bandwidth_update = &rv515_bandwidth_update,
		428	.ioctl_wait_idle = NULL,
422	};	429	};
423		430
424	/*	431	/*
Lines 455-460 int r600_ring_test(struct radeon_device Link Here
455	int r600_copy_blit(struct radeon_device *rdev,	462	int r600_copy_blit(struct radeon_device *rdev,
456	uint64_t src_offset, uint64_t dst_offset,	463	uint64_t src_offset, uint64_t dst_offset,
457	unsigned num_pages, struct radeon_fence *fence);	464	unsigned num_pages, struct radeon_fence *fence);
		465	extern void r600_iotcl_wait_idle(struct radeon_device rdev, struct radeon_object bo);
458		466
459	static struct radeon_asic r600_asic = {	467	static struct radeon_asic r600_asic = {
460	.init = &r600_init,	468	.init = &r600_init,
Lines 484-489 static struct radeon_asic r600_asic = { Link Here
484	.set_surface_reg = r600_set_surface_reg,	492	.set_surface_reg = r600_set_surface_reg,
485	.clear_surface_reg = r600_clear_surface_reg,	493	.clear_surface_reg = r600_clear_surface_reg,
486	.bandwidth_update = &rv515_bandwidth_update,	494	.bandwidth_update = &rv515_bandwidth_update,
		495	.ioctl_wait_idle = r600_iotcl_wait_idle,
487	};	496	};
488		497
489	/*	498	/*
Lines 523-528 static struct radeon_asic rv770_asic = { Link Here
523	.set_surface_reg = r600_set_surface_reg,	532	.set_surface_reg = r600_set_surface_reg,
524	.clear_surface_reg = r600_clear_surface_reg,	533	.clear_surface_reg = r600_clear_surface_reg,
525	.bandwidth_update = &rv515_bandwidth_update,	534	.bandwidth_update = &rv515_bandwidth_update,
		535	.ioctl_wait_idle = r600_iotcl_wait_idle,
526	};	536	};
527		537
528	#endif	538	#endif

Lines 34-53 Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/radeon_object.c (-14 lines)
34	#include "radeon_drm.h"	34	#include "radeon_drm.h"
35	#include "radeon.h"	35	#include "radeon.h"
36		36
37	struct radeon_object {
38	struct ttm_buffer_object tobj;
39	struct list_head list;
40	struct radeon_device *rdev;
41	struct drm_gem_object *gobj;
42	struct ttm_bo_kmap_obj kmap;
43	unsigned pin_count;
44	uint64_t gpu_addr;
45	void *kptr;
46	bool is_iomem;
47	uint32_t tiling_flags;
48	uint32_t pitch;
49	int surface_reg;
50	};
51		37
52	int radeon_ttm_init(struct radeon_device *rdev);	38	int radeon_ttm_init(struct radeon_device *rdev);
53	void radeon_ttm_fini(struct radeon_device *rdev);	39	void radeon_ttm_fini(struct radeon_device *rdev);

Lines 43-46 struct radeon_mman { Link Here

(-)linux-2.6.32-gentoo-r3/drivers/gpu/drm/radeon/radeon_object.h (+15 lines)
43	struct ttm_bo_device bdev;	43	struct ttm_bo_device bdev;
44	};	44	};
45		45
		46	struct radeon_object {
		47	struct ttm_buffer_object tobj;
		48	struct list_head list;
		49	struct radeon_device *rdev;
		50	struct drm_gem_object *gobj;
		51	struct ttm_bo_kmap_obj kmap;
		52	unsigned pin_count;
		53	uint64_t gpu_addr;
		54	void *kptr;
		55	bool is_iomem;
		56	uint32_t tiling_flags;
		57	uint32_t pitch;
		58	int surface_reg;
		59	};
		60
46	#endif	61	#endif