Attachment #106858 for bug #161963

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Lines 260-265 Link Here

(-)target-i386/cpu.h (-1 / +3 lines)
260	#define CPUID_MCA (1 << 14)	260	#define CPUID_MCA (1 << 14)
261	#define CPUID_CMOV (1 << 15)	261	#define CPUID_CMOV (1 << 15)
262	#define CPUID_PAT (1 << 16)	262	#define CPUID_PAT (1 << 16)
		263	#define CPUID_PSE36 (1 << 17)
263	#define CPUID_CLFLUSH (1 << 19)	264	#define CPUID_CLFLUSH (1 << 19)
264	/* ... */	265	/* ... */
265	#define CPUID_MMX (1 << 23)	266	#define CPUID_MMX (1 << 23)
Lines 543-549 Link Here
543	cache: it synchronizes the hflags with the segment cache values */	544	cache: it synchronizes the hflags with the segment cache values */
544	static inline void cpu_x86_load_seg_cache(CPUX86State *env,	545	static inline void cpu_x86_load_seg_cache(CPUX86State *env,
545	int seg_reg, unsigned int selector,	546	int seg_reg, unsigned int selector,
546	uint32_t base, unsigned int limit,	547	target_ulong base,
		548	unsigned int limit,
547	unsigned int flags)	549	unsigned int flags)
548	{	550	{
549	SegmentCache *sc;	551	SegmentCache *sc;




        return 0xffff;
}

#ifdef TARGET_X86_64
#define SET_ESP(val, sp_mask)\
do {\
    if ((sp_mask) == 0xffff)\
        ESP = (ESP & ~0xffff) | ((val) & 0xffff);\
    else if ((sp_mask) == 0xffffffffLL)\
        ESP = (uint32_t)(val);\
    else\
        ESP = (val);\
} while (0)
#else
#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))
#endif

/* XXX: add a is_user flag to have proper security support */
#define PUSHW(ssp, sp, sp_mask, val)\
{\

{
    SegmentCache *dt;
    target_ulong ptr, ssp;
    int type, dpl, selector, ss_dpl, cpl;
    int has_error_code, new_stack, shift;
    uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
    uint32_t old_eip, sp_mask;

    has_error_code = 0;
    if (!is_int && !is_hw) {

            raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
        switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
        if (has_error_code) {
            int type;
            uint32_t mask;
            /* push the error code */
            type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
            shift = type >> 3;

                stl_kernel(ssp, error_code);
            else
                stw_kernel(ssp, error_code);
            SET_ESP(esp, mask);
        }
        return;
    case 6: /* 286 interrupt gate */

        cpu_x86_load_seg_cache(env, R_SS, ss, 
                               ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
    }
    SET_ESP(esp, sp_mask);

    selector = (selector & ~3) | dpl;
    cpu_x86_load_seg_cache(env, R_CS, selector, 

        PUSHW(ssp, esp, esp_mask, next_eip);
    }

    SET_ESP(esp, esp_mask);
    env->eip = new_eip;
    env->segs[R_CS].selector = new_cs;
    env->segs[R_CS].base = (new_cs << 4);

            if (new_eip > limit)
                raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
            /* from this point, not restartable */
            SET_ESP(sp, sp_mask);
            cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
                                   get_seg_base(e1, e2), limit, e2);
            EIP = new_eip;

                       get_seg_limit(e1, e2),
                       e2);
        cpu_x86_set_cpl(env, dpl);
        SET_ESP(sp, sp_mask);
        EIP = offset;
    }
#ifdef USE_KQEMU


        sp += addend;
    }
    SET_ESP(sp, sp_mask);
    env->eip = new_eip;
    if (is_iret) {
        /* NOTE: 'cpl' is the _old_ CPL */

Lines 135-140 Link Here

(-)target-i386/helper2.c (+2 lines)
135		135
136	/* these features are needed for Win64 and aren't fully implemented */	136	/* these features are needed for Win64 and aren't fully implemented */
137	env->cpuid_features \|= CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA;	137	env->cpuid_features \|= CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA;
		138	/* this feature is needed for Solaris and isn't fully implemented */
		139	env->cpuid_features \|= CPUID_PSE36;
138	#endif	140	#endif
139	}	141	}
140	cpu_reset(env);	142	cpu_reset(env);

Return to bug 161963

Lines 553-558 Link Here

(-)target-i386/helper.c (-9 / +24 lines)
553	return 0xffff;	553	return 0xffff;
554	}	554	}
555		555
		556	#ifdef TARGET_X86_64
		557	#define SET_ESP(val, sp_mask)\
		558	do {\
		559	if ((sp_mask) == 0xffff)\
		560	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
		561	else if ((sp_mask) == 0xffffffffLL)\
		562	ESP = (uint32_t)(val);\
		563	else\
		564	ESP = (val);\
		565	} while (0)
		566	#else
		567	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
		568	#endif
		569
556	/* XXX: add a is_user flag to have proper security support */	570	/* XXX: add a is_user flag to have proper security support */
557	#define PUSHW(ssp, sp, sp_mask, val)\	571	#define PUSHW(ssp, sp, sp_mask, val)\
558	{\	572	{\
Lines 584-593 Link Here
584	{	598	{
585	SegmentCache *dt;	599	SegmentCache *dt;
586	target_ulong ptr, ssp;	600	target_ulong ptr, ssp;
587	int type, dpl, selector, ss_dpl, cpl, sp_mask;	601	int type, dpl, selector, ss_dpl, cpl;
588	int has_error_code, new_stack, shift;	602	int has_error_code, new_stack, shift;
589	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;	603	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
590	uint32_t old_eip;	604	uint32_t old_eip, sp_mask;
591		605
592	has_error_code = 0;	606	has_error_code = 0;
593	if (!is_int && !is_hw) {	607	if (!is_int && !is_hw) {
Lines 623-629 Link Here
623	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);	637	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
624	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);	638	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
625	if (has_error_code) {	639	if (has_error_code) {
626	int mask, type;	640	int type;
		641	uint32_t mask;
627	/* push the error code */	642	/* push the error code */
628	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;	643	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
629	shift = type >> 3;	644	shift = type >> 3;
Lines 637-643 Link Here
637	stl_kernel(ssp, error_code);	652	stl_kernel(ssp, error_code);
638	else	653	else
639	stw_kernel(ssp, error_code);	654	stw_kernel(ssp, error_code);
640	ESP = (esp & mask) \| (ESP & ~mask);	655	SET_ESP(esp, mask);
641	}	656	}
642	return;	657	return;
643	case 6: /* 286 interrupt gate */	658	case 6: /* 286 interrupt gate */
Lines 765-771 Link Here
765	cpu_x86_load_seg_cache(env, R_SS, ss,	780	cpu_x86_load_seg_cache(env, R_SS, ss,
766	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);	781	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
767	}	782	}
768	ESP = (ESP & ~sp_mask) \| (esp & sp_mask);	783	SET_ESP(esp, sp_mask);
769		784
770	selector = (selector & ~3) \| dpl;	785	selector = (selector & ~3) \| dpl;
771	cpu_x86_load_seg_cache(env, R_CS, selector,	786	cpu_x86_load_seg_cache(env, R_CS, selector,
Lines 2015-2021 Link Here
2015	PUSHW(ssp, esp, esp_mask, next_eip);	2030	PUSHW(ssp, esp, esp_mask, next_eip);
2016	}	2031	}
2017		2032
2018	ESP = (ESP & ~esp_mask) \| (esp & esp_mask);	2033	SET_ESP(esp, esp_mask);
2019	env->eip = new_eip;	2034	env->eip = new_eip;
2020	env->segs[R_CS].selector = new_cs;	2035	env->segs[R_CS].selector = new_cs;
2021	env->segs[R_CS].base = (new_cs << 4);	2036	env->segs[R_CS].base = (new_cs << 4);
Lines 2101-2107 Link Here
2101	if (new_eip > limit)	2116	if (new_eip > limit)
2102	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);	2117	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2103	/* from this point, not restartable */	2118	/* from this point, not restartable */
2104	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);	2119	SET_ESP(sp, sp_mask);
2105	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,	2120	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2106	get_seg_base(e1, e2), limit, e2);	2121	get_seg_base(e1, e2), limit, e2);
2107	EIP = new_eip;	2122	EIP = new_eip;
Lines 2230-2236 Link Here
2230	get_seg_limit(e1, e2),	2245	get_seg_limit(e1, e2),
2231	e2);	2246	e2);
2232	cpu_x86_set_cpl(env, dpl);	2247	cpu_x86_set_cpl(env, dpl);
2233	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);	2248	SET_ESP(sp, sp_mask);
2234	EIP = offset;	2249	EIP = offset;
2235	}	2250	}
2236	#ifdef USE_KQEMU	2251	#ifdef USE_KQEMU
Lines 2459-2465 Link Here
2459		2474
2460	sp += addend;	2475	sp += addend;
2461	}	2476	}
2462	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);	2477	SET_ESP(sp, sp_mask);
2463	env->eip = new_eip;	2478	env->eip = new_eip;
2464	if (is_iret) {	2479	if (is_iret) {
2465	/* NOTE: 'cpl' is the _old_ CPL */	2480	/* NOTE: 'cpl' is the _old_ CPL */