Attachment #97993 for bug #148090

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 add several PCI ID for the PCI-E adapters ;
 new identification strings ;
 the RTL_GIGA_MAC_VER_ defines have been renamed to closely match the
 out-of-tree driver. It makes the comparison less hairy ;
 various magic ;
 the PCI region for the device with PCI ID 0x8136 is guessed.
 Explanation: the in-kernel Linux driver is written to allow MM register
 accesses and avoid the IO tax. The relevant BAR register was found at
 base address 1 for the plain-old PCI 8169. User reported lspci show that
 it is found at base address 2 for the new Gigabit PCI-E 816{8/9}.
 Typically:
 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.: Unknown device 8168 (rev 01)
         Subsystem: Unknown device 1631:e015
         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
         Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
         Latency: 0, cache line size 20
         Interrupt: pin A routed to IRQ 16
         Region 0: I/O ports at b800 [size=256]
         Region 2: Memory at ff7ff000 (64-bit, non-prefetchable) [size=4K]
         ^^^^^^^^
 So far I have not received any lspci report for the 0x8136 and
 Realtek's driver do not help: be it under BSD or Linux, their r1000 driver
 include a USE_IO_SPACE #define but the bar address is always hardcoded
 to 1 in the MM case. :o/
 the 8168 has been reported to require an extra alignment for its receive
 buffers. The status of the 8167 and 8136 is not known in this regard.
++ b/drivers/net/r8169.c
-- a/drivers/net/r8169.c

#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

enum mac_version {
	RTL_GIGA_MAC_VER_01 = 0x00,
	RTL_GIGA_MAC_VER_02 = 0x01,
	RTL_GIGA_MAC_VER_03 = 0x02,
	RTL_GIGA_MAC_VER_04 = 0x03,
	RTL_GIGA_MAC_VER_05 = 0x04,
	RTL_GIGA_MAC_VER_11 = 0x0b,
	RTL_GIGA_MAC_VER_12 = 0x0c,
	RTL_GIGA_MAC_VER_13 = 0x0d,
	RTL_GIGA_MAC_VER_14 = 0x0e,
	RTL_GIGA_MAC_VER_15 = 0x0f
};

enum phy_version {

	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
};


#define _R(NAME,MAC,MASK) \
	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }


	u8 mac_version;
	u32 RxConfigMask;	/* Clears the bits supported by this chip */
} rtl_chip_info[] = {
	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_02, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_03, 0xff7e1880),
	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880),
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880),
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
};
#undef _R

enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

static const struct {
	unsigned int region;
	unsigned int align;
} rtl_cfg_info[] = {
	[RTL_CFG_0] = { 1, NET_IP_ALIGN },
	[RTL_CFG_1] = { 2, NET_IP_ALIGN },
	[RTL_CFG_2] = { 2, 8 }
};

static struct pci_device_id rtl8169_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_1 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_1 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_2 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
	{0,},
};


	PHY_Cap_100_Full = 0x0100,

	/* PHY_1000_CTRL_REG = 9 */
	PHY_Cap_1000_Half = 0x0100,
	PHY_Cap_1000_Full = 0x0200,

	PHY_Cap_Null = 0x0,

	dma_addr_t RxPhyAddr;
	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */
	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
	unsigned align;
	unsigned rx_buf_sz;
	struct timer_list timer;
	u16 cp_cmd;

	auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
		       PHY_Cap_100_Half | PHY_Cap_100_Full);
	giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
	giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half | PHY_Cap_Null);

	if (autoneg == AUTONEG_ENABLE) {
		auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
			      PHY_Cap_100_Half | PHY_Cap_100_Full);
		giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;
	} else {
		if (speed == SPEED_10)
			auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
		else if (speed == SPEED_100)
			auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
		else if (speed == SPEED_1000)
			giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;

		if (duplex == DUPLEX_HALF)
			auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);

		if (duplex == DUPLEX_FULL)
			auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);

		/* This tweak comes straight from Realtek's driver. */
		if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
		    (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
			auto_nego = PHY_Cap_100_Half | 0x01;
		}
	}

	/* The 8100e/8101e do Fast Ethernet only. */
	if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
		if ((giga_ctrl & (PHY_Cap_1000_Full | PHY_Cap_1000_Half)) &&
		    netif_msg_link(tp)) {
			printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
			       dev->name);
		}
		giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half);
	}

	auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;

		u32 mask;
		int mac_version;
	} mac_info[] = {
		{ 0x38800000,	RTL_GIGA_MAC_VER_15 },
		{ 0x38000000,	RTL_GIGA_MAC_VER_12 },
		{ 0x34000000,	RTL_GIGA_MAC_VER_13 },
		{ 0x30800000,	RTL_GIGA_MAC_VER_14 },
		{ 0x30000000,   RTL_GIGA_MAC_VER_11 },
		{ 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0x10000000,	RTL_GIGA_MAC_VER_04 },
		{ 0x04000000,	RTL_GIGA_MAC_VER_03 },
		{ 0x00800000,	RTL_GIGA_MAC_VER_02 },
		{ 0x00000000,	RTL_GIGA_MAC_VER_01 }	/* Catch-all */
	}, *p = mac_info;
	u32 reg;



static void rtl8169_print_mac_version(struct rtl8169_private *tp)
{
	dprintk("mac_version = 0x%02x\n", tp->mac_version);
		int version;
		char *msg;
	} mac_print[] = {
		{ RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
		{ RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
		{ RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
		{ 0, NULL }
	}, *p;

	for (p = mac_print; p->msg; p++) {
		if (tp->mac_version == p->version) {
			dprintk("mac_version == %s (%04d)\n", p->msg,
				  p->version);
			return;
		}
	}
	dprintk("mac_version == Unknown\n");
}

static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)

	rtl8169_print_mac_version(tp);
	rtl8169_print_phy_version(tp);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
		return;
	if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
		return;


	/* Shazam ! */

	if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
		mdio_write(ioaddr, 31, 0x0001);
		mdio_write(ioaddr,  9, 0x273a);
		mdio_write(ioaddr, 14, 0x7bfb);

	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
	assert(tp->phy_version < RTL_GIGA_PHY_VER_H);

	if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))

	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

	if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
	    (tp->phy_version >= RTL_GIGA_PHY_VER_H))
		return;


	struct rtl8169_private *tp = netdev_priv(dev);
	struct timer_list *timer = &tp->timer;

	if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
	    (tp->phy_version >= RTL_GIGA_PHY_VER_H))
		return;


	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
	RTL_W8(0x82, 0x01);

	if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
		dprintk("Set PCI Latency=0x40\n");
		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");

static int __devinit
rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const unsigned int region = rtl_cfg_info[ent->driver_data].region;
	struct rtl8169_private *tp;
	struct net_device *dev;
	void __iomem *ioaddr;

	}

	/* make sure PCI base addr 1 is MMIO */
	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
		if (netif_msg_probe(tp)) {
			dev_err(&pdev->dev,
				"region #%d not an MMIO resource, aborting\n",
				region);
		}
		rc = -ENODEV;
		goto err_out_mwi_3;
	}

	/* check for weird/broken PCI region reporting */
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
		if (netif_msg_probe(tp)) {
			dev_err(&pdev->dev,
				"Invalid PCI region size(s), aborting\n");

	pci_set_master(pdev);

	/* ioremap MMIO region */
	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
	if (!ioaddr) {
		if (netif_msg_probe(tp))
			dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");

	tp->intr_mask = 0xffff;
	tp->pci_dev = pdev;
	tp->mmio_addr = ioaddr;
	tp->align = rtl_cfg_info[ent->driver_data].align;

	spin_lock_init(&tp->lock);


	if (rc < 0)
		goto err_out_unmap_5;

	if (netif_msg_probe(tp)) {
		printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
		       dev->name, rtl_chip_info[tp->chipset].name);
	}

	pci_set_drvdata(pdev, dev);

	if (netif_msg_probe(tp)) {

		       "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
		       "IRQ %d\n",
		       dev->name,
		       rtl_chip_info[tp->chipset].name,
		       dev->base_addr,
		       dev->dev_addr[0], dev->dev_addr[1],
		       dev->dev_addr[2], dev->dev_addr[3],

{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
	u32 i;

	/* Soft reset the chip. */

		udelay(10);
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
		pci_write_config_word(pdev, 0x68, 0x00);
		pci_write_config_word(pdev, 0x69, 0x08);
	}

	/* Undocumented stuff. */
	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
		u16 cmd;

		/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
		if ((RTL_R8(Config2) & 0x07) & 0x01)
			RTL_W32(0x7c, 0x0007ffff);

		RTL_W32(0x7c, 0x0007ff00);

		pci_read_config_word(pdev, PCI_COMMAND, &cmd);
		cmd = cmd & 0xef;
		pci_write_config_word(pdev, PCI_COMMAND, cmd);
	}


	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	RTL_W8(EarlyTxThres, EarlyTxThld);

	/* Low hurts. Let's disable the filtering. */

	RTL_W32(TxConfig,
		(TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
						TxInterFrameGapShift));
	tp->cp_cmd |= RTL_R16(CPlusCmd);
	RTL_W16(CPlusCmd, tp->cp_cmd);

	tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;

	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
		dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
			"Bit-3 and bit-14 MUST be 1\n");
		tp->cp_cmd |= (1 << 14);
		RTL_W16(CPlusCmd, tp->cp_cmd);
	}

	RTL_W16(CPlusCmd, tp->cp_cmd);

	/*
	 * Undocumented corner. Supposedly:
	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets

	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	RTL_W8(Cfg9346, Cfg9346_Lock);
	udelay(10);


}

static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
				struct RxDesc *desc, int rx_buf_sz,
				unsigned int align)
{
	struct sk_buff *skb;
	dma_addr_t mapping;
	int ret = 0;

	skb = dev_alloc_skb(rx_buf_sz + align);
	if (!skb)
		goto err_out;

	skb_reserve(skb, align);
	*sk_buff = skb;

	mapping = pci_map_single(pdev, skb->data, rx_buf_sz,


		if (tp->Rx_skbuff[i])
			continue;

		ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
			tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
		if (ret < 0)
			break;
	}

}

static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
				      struct RxDesc *desc, int rx_buf_sz,
				      unsigned int align)
{
	int ret = -1;

	if (pkt_size < rx_copybreak) {
		struct sk_buff *skb;

		skb = dev_alloc_skb(pkt_size + align);
		if (skb) {
			skb_reserve(skb, align);
			eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
			*sk_buff = skb;
			rtl8169_mark_to_asic(desc, rx_buf_sz);

			}

			rtl8169_rx_csum(skb, desc);

			pci_dma_sync_single_for_cpu(tp->pci_dev,
				le64_to_cpu(desc->addr), tp->rx_buf_sz,
				PCI_DMA_FROMDEVICE);

			if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
						tp->rx_buf_sz, tp->align)) {
				pci_action = pci_unmap_single;
				tp->Rx_skbuff[entry] = NULL;
			}

	tmp = rtl8169_rx_config | rx_mode |
	      (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);

	if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
	    (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
		mc_filter[0] = 0xffffffff;
		mc_filter[1] = 0xffffffff;
	}

	RTL_W32(RxConfig, tmp);
	RTL_W32(MAR0 + 0, mc_filter[0]);
	RTL_W32(MAR0 + 4, mc_filter[1]);

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