https://bugs.gentoo.org/761715
https://github.com/MariaDB/server/pull/1981

From: alexfanqi <alex.fan.q@gmail.com>
Date: Tue, 1 Feb 2022 10:42:58 +1100
Subject: [PATCH] implement cycle accuracy timer for riscv

Status: upstream not likely accept for unsupported arch

Signed-off-by: alexfanqi <alex.fan.q@gmail.com>
---
 include/my_rdtsc.h |  1 +
 mysys/my_rdtsc.cc  | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+)

--- a/include/my_rdtsc.h
+++ b/include/my_rdtsc.h
@@ -128,5 +128,6 @@ void my_timer_init(MY_TIMER_INFO *mti);
 #define MY_TIMER_ROUTINE_GETSYSTEMTIMEASFILETIME 26
 /* #define MY_TIMER_ROUTINE_ASM_SUNPRO_X86_64       27  - No longer used */
 #define MY_TIMER_ROUTINE_ASM_AARCH64 28
+#define MY_TIMER_ROUTINE_ASM_RISCV 29
 
 #endif

--- a/mysys/my_rdtsc.cc
+++ b/mysys/my_rdtsc.cc
@@ -168,6 +168,28 @@ ulonglong my_timer_cycles(void) {
     __asm __volatile__("mrs %[rt],cntvct_el0" : [ rt ] "=r"(result));
     return result;
   }
+#elif defined(__GNUC__) && defined(__riscv)  // RISC-V
+  // Use RDCYCLE (and RDCYCLEH on riscv32)
+  {
+#if __riscv_xlen == 32
+  ulong result_lo, result_hi0, result_hi1;
+  // Implemented in assembly because Clang insisted on branching.
+  __asm __volatile__(
+      "rdcycleh %0\n"
+      "rdcycle %1\n"
+      "rdcycleh %2\n"
+      "sub %0, %0, %2\n"
+      "seqz %0, %0\n"
+      "sub %0, zero, %0\n"
+      "and %1, %1, %0\n"
+      : "=r"(result_hi0), "=r"(result_lo), "=r"(result_hi1));
+  return (static_cast<ulonglong>(result_hi1) << 32) | result_lo;
+#else
+  ulonglong result;
+  __asm __volatile__("rdcycle %0" : "=r"(result));
+  return result;
+  }
+#endif
 #elif defined(HAVE_SYS_TIMES_H) && defined(HAVE_GETHRTIME)
   /* gethrtime may appear as either cycle or nanosecond counter */
   return (ulonglong)gethrtime();
@@ -453,6 +475,8 @@ void my_timer_init(MY_TIMER_INFO *mti) {
   mti->cycles.routine = MY_TIMER_ROUTINE_ASM_GCC_SPARC64;
 #elif defined(__GNUC__) && defined(__aarch64__)
   mti->cycles.routine = MY_TIMER_ROUTINE_ASM_AARCH64;
+#elif defined(__GNUC__) && defined(__riscv)
+  mti->cycles.routine = MY_TIMER_ROUTINE_ASM_RISCV;
 #elif defined(HAVE_SYS_TIMES_H) && defined(HAVE_GETHRTIME)
   mti->cycles.routine = MY_TIMER_ROUTINE_GETHRTIME;
 #else
-- 
2.25.1