Attachment #188459 for bug #262603




			tmake_file="${tmake_file} i386/t-linux64"
			need_64bit_hwint=yes
			case X"${with_cpu}" in
			Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
				;;
			X)
				if test x$with_cpu_64 = x; then

				;;
			*)
				echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
				echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
				exit 1
				;;
			esac

		need_64bit_hwint=yes
		use_gcc_stdint=wrap
		case X"${with_cpu}" in
		Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
			;;
		X)
			if test x$with_cpu_64 = x; then

			;;
		*)
			echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
			echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
			exit 1
			;;
		esac

				esac
				# OK
				;;
			"" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | atom | generic)
				# OK
				;;
			*)




;; Atom Scheduling
;; Copyright (C) 2009 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
;;
;; Atom is an in-order core with two integer pipelines.


(define_attr "atom_unit" "sishuf,simul,jeu,complex,other" 
  (const_string "other"))

(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other"
  (const_string "other"))

(define_automaton "atom")

;;  Atom has two ports: port 0 and port 1 connecting to all execution units
(define_cpu_unit "atom-port-0,atom-port-1" "atom")

;;  EU: Execution Unit
;;  Atom EUs are connected by port 0 or port 1. 

(define_cpu_unit "atom-eu-0, atom-eu-1,
                  atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4"
                  "atom")

;; Some EUs have duplicated copied and can be accessed via either
;; port 0 or port 1
;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)")

;;; Some instructions is dual-pipe execution, need both ports
;;; Complex multi-op macro-instructoins need both ports and all EUs
(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)")
(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 + 
                                    atom-imul-1 + atom-imul-2 + atom-imul-3 +
                                    atom-imul-4)")

;;; Most of simple instructions have 1 cycle latency. Some of them
;;; issue in port 0, some in port 0 and some in either port.
(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)")
(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)")
(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)")

;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)")

;;; fmul insn can have 4 or 5 cycles latency
(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4")
(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3")

;;; fadd can has 5 cycles latency depends on instruction forms
(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5")

;;; imul insn has 5 cycles latency
(define_reservation "atom-imul-32" 
                    "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4, 
                     atom-port-0")
;;; imul instruction excludes other non-FP instructions.
(exclusion_set "atom-eu-0, atom-eu-1" 
               "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")

;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on 
;;; instruction forms
(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)")
(define_reservation "atom-dual-2c"
                    "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)")
(define_reservation "atom-dual-5c"
                    "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)")

;;; Complex macro-instruction has variants of latency, and uses both ports.
(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)")

(define_insn_reservation  "atom_other" 9
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "other")
            (eq_attr "atom_unit" "!jeu")))
  "atom-complex, atom-all-eu*8")

;; return has type "other" with atom_unit "jeu"
(define_insn_reservation  "atom_other_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "other")
            (eq_attr "atom_unit" "jeu")))
  "atom-dual-1c")

(define_insn_reservation  "atom_multi" 9
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "multi"))
  "atom-complex, atom-all-eu*8")

;; Normal alu insns without carry
(define_insn_reservation  "atom_alu" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "none")
                 (eq_attr "use_carry" "0"))))
  "atom-simple-either")

;; Normal alu insns without carry
(define_insn_reservation  "atom_alu_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "!none")
                 (eq_attr "use_carry" "0"))))
  "atom-simple-either")

;; Alu insn consuming CF, such as add/sbb
(define_insn_reservation  "atom_alu_carry" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "none")
                 (eq_attr "use_carry" "1"))))
  "atom-simple-either")

;; Alu insn consuming CF, such as add/sbb
(define_insn_reservation  "atom_alu_carry_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "!none")
                (eq_attr "use_carry" "1"))))
  "atom-simple-either")

(define_insn_reservation  "atom_alu1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu1")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_alu1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu1")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_negnot" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "negnot")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_negnot_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "negnot")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_imov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_imov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; 16<-16, 32<-32
(define_insn_reservation  "atom_imovx" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "none")
                 (ior (and (match_operand:HI 0 "register_operand")
                           (match_operand:HI 1 "general_operand"))
                      (and (match_operand:SI 0 "register_operand")
                           (match_operand:SI 1 "general_operand"))))))
  "atom-simple-either")

;; 16<-16, 32<-32, mem
(define_insn_reservation  "atom_imovx_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "!none")
                 (ior (and (match_operand:HI 0 "register_operand")
                           (match_operand:HI 1 "general_operand"))
                      (and (match_operand:SI 0 "register_operand")
                           (match_operand:SI 1 "general_operand"))))))
  "atom-simple-either")

;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
(define_insn_reservation  "atom_imovx_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "none")
                 (ior (match_operand:QI 0 "register_operand")
                      (ior (and (match_operand:SI 0 "register_operand")
                                (not (match_operand:SI 1 "general_operand")))
                           (match_operand:DI 0 "register_operand"))))))
  "atom-simple-0")

;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
(define_insn_reservation  "atom_imovx_2_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "!none")
                 (ior (match_operand:QI 0 "register_operand")
                      (ior (and (match_operand:SI 0 "register_operand")
                                (not (match_operand:SI 1 "general_operand")))
                           (match_operand:DI 0 "register_operand"))))))
  "atom-simple-0")

;; 16<-8
(define_insn_reservation  "atom_imovx_3" 3
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (match_operand:HI 0 "register_operand")
                 (match_operand:QI 1 "general_operand"))))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_lea" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "lea")
            (eq_attr "mode" "!HI")))
  "atom-simple-either")

;; lea 16bit address is complex insn
(define_insn_reservation  "atom_lea_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "lea")
            (eq_attr "mode" "HI")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_incdec" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "incdec")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_incdec_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "incdec")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; simple shift instruction use SHIFT eu, none memory
(define_insn_reservation  "atom_ishift" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
  "atom-simple-0")

;; simple shift instruction use SHIFT eu, memory
(define_insn_reservation  "atom_ishift_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
  "atom-simple-0")

;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles
(define_insn_reservation  "atom_ishift_3" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (eq_attr "prefix_0f" "1")))
  "atom-complex, atom-all-eu*6")

(define_insn_reservation  "atom_ishift1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_ishift1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_imul" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
  "atom-imul-32")

(define_insn_reservation  "atom_imul_mem" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
  "atom-imul-32")

;; latency set to 10 as common 64x64 imul
(define_insn_reservation  "atom_imul_3" 10
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (eq_attr "mode" "!SI")))
  "atom-complex, atom-all-eu*9")

(define_insn_reservation  "atom_idiv" 65
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "idiv"))
  "atom-complex, atom-all-eu*32, nothing*32")

(define_insn_reservation  "atom_icmp" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmp")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_icmp_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmp")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_test" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "test")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_test_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "test")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_ibr" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ibr")
            (eq_attr "memory" "!load")))
  "atom-simple-1")

;; complex if jump target is from address
(define_insn_reservation  "atom_ibr_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ibr")
            (eq_attr "memory" "load")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_setcc" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "setcc")
            (eq_attr "memory" "!store")))
  "atom-simple-either")

;; 2 cycles complex if target is in memory
(define_insn_reservation  "atom_setcc_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "setcc")
            (eq_attr "memory" "store")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_icmov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_icmov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; UCODE if segreg, ignored
(define_insn_reservation  "atom_push" 2
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "push"))
  "atom-dual-2c")

;; pop r64 is 1 cycle. UCODE if segreg, ignored
(define_insn_reservation  "atom_pop" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "pop")
            (eq_attr "mode" "DI")))
  "atom-dual-1c")

;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
(define_insn_reservation  "atom_pop_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "pop")
            (eq_attr "mode" "!DI")))
  "atom-dual-2c")

;; UCODE if segreg, ignored
(define_insn_reservation  "atom_call" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "call"))
  "atom-dual-1c")

(define_insn_reservation  "atom_callv" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "callv"))
  "atom-dual-1c")

(define_insn_reservation  "atom_leave" 3
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "leave"))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_str" 3
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "str"))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_sselog" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_sselog_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_sselog1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_sselog1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

;; not pmad, not psad
(define_insn_reservation  "atom_sseiadd" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "!simul")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-simple-either")

;; pmad, psad and 64
(define_insn_reservation  "atom_sseiadd_2" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "simul" )
                      (eq_attr "mode" "DI")))))
  "atom-fmul-4c")

;; pmad, psad and 128
(define_insn_reservation  "atom_sseiadd_3" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "simul" )
                      (eq_attr "mode" "TI")))))
  "atom-fmul-5c")

;; if paddq(64 bit op), phadd/phsub
(define_insn_reservation  "atom_sseiadd_4" 6
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (ior (match_operand:V2DI 0 "register_operand")
                 (eq_attr "atom_unit" "complex"))))
  "atom-complex, atom-all-eu*5")

;; if immediate op. 
(define_insn_reservation  "atom_sseishft" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (and (eq_attr "atom_unit" "!sishuf")
                 (match_operand 2 "immediate_operand"))))
  "atom-simple-either")

;; if palignr or psrldq
(define_insn_reservation  "atom_sseishft_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (and (eq_attr "atom_unit" "sishuf")
                 (match_operand 2 "immediate_operand"))))
  "atom-simple-0")

;; if reg/mem op
(define_insn_reservation  "atom_sseishft_3" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (not (match_operand 2 "immediate_operand"))))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_sseimul" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "sseimul"))
  "atom-simple-0")

;; rcpss or rsqrtss
(define_insn_reservation  "atom_sse" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
  "atom-fmul-4c")

;; movshdup, movsldup. Suggest to type sseishft
(define_insn_reservation  "atom_sse_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (eq_attr "atom_sse_attr" "movdup")))
  "atom-simple-0")

;; lfence
(define_insn_reservation  "atom_sse_3" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (eq_attr "atom_sse_attr" "lfence")))
  "atom-simple-either")

;; sfence,clflush,mfence, prefetch
(define_insn_reservation  "atom_sse_4" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (ior (eq_attr "atom_sse_attr" "fence")
                 (eq_attr "atom_sse_attr" "prefetch"))))
  "atom-simple-0")

;; rcpps, rsqrtss, sqrt, ldmxcsr
(define_insn_reservation  "atom_sse_5" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (ior (ior (eq_attr "atom_sse_attr" "sqrt")
                      (eq_attr "atom_sse_attr" "mxcsr"))
                 (and (eq_attr "atom_sse_attr" "rcp")
                      (eq_attr "mode" "V4SF")))))
  "atom-complex, atom-all-eu*6")

;; xmm->xmm
(define_insn_reservation  "atom_ssemov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy"))))
  "atom-simple-either")

;; reg->xmm
(define_insn_reservation  "atom_ssemov_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r"))))
  "atom-simple-0")

;; xmm->reg
(define_insn_reservation  "atom_ssemov_3" 3
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy"))))
  "atom-eu-0-3-1")

;; mov mem
(define_insn_reservation  "atom_ssemov_4" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
  "atom-simple-0")

;; movu mem
(define_insn_reservation  "atom_ssemov_5" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
  "atom-complex, atom-all-eu")

;; no memory simple
(define_insn_reservation  "atom_sseadd" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (and (eq_attr "memory" "none")
                 (and (eq_attr "mode" "!V2DF")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-fadd-5c")

;; memory simple
(define_insn_reservation  "atom_sseadd_mem" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (and (eq_attr "memory" "!none")
                 (and (eq_attr "mode" "!V2DF")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-dual-5c")

;; maxps, minps, *pd, hadd, hsub
(define_insn_reservation  "atom_sseadd_3" 8
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
  "atom-complex, atom-all-eu*7")

;; Except dppd/dpps
(define_insn_reservation  "atom_ssemul" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemul")
            (eq_attr "mode" "!SF")))
  "atom-fmul-5c")

;; Except dppd/dpps, 4 cycle if mulss
(define_insn_reservation  "atom_ssemul_2" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemul")
            (eq_attr "mode" "SF")))
  "atom-fmul-4c")

(define_insn_reservation  "atom_ssecmp" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssecmp"))
  "atom-simple-either")

(define_insn_reservation  "atom_ssecomi" 10
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssecomi"))
  "atom-complex, atom-all-eu*9")

;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
(define_insn_reservation  "atom_ssecvt" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (ior (and (match_operand:V2SI 0 "register_operand")
                      (match_operand:V4SF 1 "register_operand"))
                 (and (match_operand:V4SF 0 "register_operand")
                      (match_operand:V2SI 1 "register_operand")))))
  "atom-fadd-5c")

;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
(define_insn_reservation  "atom_ssecvt_2" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (ior (and (match_operand:V2SI 0 "register_operand")
                      (match_operand:V4SF 1 "memory_operand"))
                 (and (match_operand:V4SF 0 "register_operand")
                      (match_operand:V2SI 1 "memory_operand")))))
  "atom-dual-5c")

;; otherwise. 7 cycles average for cvtss2sd
(define_insn_reservation  "atom_ssecvt_3" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (not (ior (and (match_operand:V2SI 0 "register_operand")
                           (match_operand:V4SF 1 "nonimmediate_operand"))
                      (and (match_operand:V4SF 0 "register_operand")
                           (match_operand:V2SI 1 "nonimmediate_operand"))))))
  "atom-complex, atom-all-eu*6")

;; memory and cvtsi2sd
(define_insn_reservation  "atom_sseicvt" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseicvt")
            (and (match_operand:V2DF 0 "register_operand")
                 (match_operand:SI 1 "memory_operand"))))
  "atom-dual-5c")

;; otherwise. 8 cycles average for cvtsd2si
(define_insn_reservation  "atom_sseicvt_2" 8
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseicvt")
            (not (and (match_operand:V2DF 0 "register_operand")
                      (match_operand:SI 1 "memory_operand")))))
  "atom-complex, atom-all-eu*7")

(define_insn_reservation  "atom_ssediv" 62
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssediv"))
  "atom-complex, atom-all-eu*12, nothing*49")

;; simple for fmov
(define_insn_reservation  "atom_fmov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "fmov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

;; simple for fmov
(define_insn_reservation  "atom_fmov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "fmov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; Define bypass here

;; There will be no stall from lea to non-mem EX insns
(define_bypass 0 "atom_lea"
                 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec, atom_setcc, atom_icmov, atom_pop")

(define_bypass 0 "atom_lea"
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "!ix86_agi_dependent")

;; There will be 3 cycles stall from EX insns to AGAN insns LEA
(define_bypass 4 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
                  atom_rotate1, atom_setcc, atom_icmov, atom_pop,
                  atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "atom_lea")

;; There will be 3 cycles stall from EX insns to insns need addr calculation
(define_bypass 4 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
                  atom_rotate1, atom_setcc, atom_icmov, atom_pop,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imul_mem, atom_icmp_mem,
                  atom_test_mem, atom_icmov_mem, atom_sselog_mem,
                  atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem,
                  atom_ishift_mem, atom_ishift1_mem, 
                  atom_rotate_mem, atom_rotate1_mem"
                  "ix86_agi_dependent")

;; Stall from imul to lea is 8 cycles.
(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea")

;; Stall from imul to memory address is 8 cycles.
(define_bypass 9 "atom_imul, atom_imul_mem" 
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
                  atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem,
                  atom_rotate1_mem, atom_imul_mem, atom_icmp_mem,
                  atom_test_mem, atom_icmov_mem, atom_sselog_mem,
                  atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem"
                  "ix86_agi_dependent")

;; There will be 0 cycle stall from cmp/test to jcc

;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry,
                  atom_alu1, atom_negnot, atom_incdec, atom_ishift,
                  atom_ishift1, atom_rotate, atom_rotate1"
                 "atom_icmov, atom_alu_carry")

Lines 119-124 ix86_target_macros_internal (int isa_flag, Link Here

(-)a/gcc/config/i386/i386-c.c (+7 lines)
119	def_or_undef (parse_in, "__core2");	119	def_or_undef (parse_in, "__core2");
120	def_or_undef (parse_in, "__core2__");	120	def_or_undef (parse_in, "__core2__");
121	break;	121	break;
		122	case PROCESSOR_ATOM:
		123	def_or_undef (parse_in, "__atom");
		124	def_or_undef (parse_in, "__atom__");
		125	break;
122	/* use PROCESSOR_max to not set/unset the arch macro. */	126	/* use PROCESSOR_max to not set/unset the arch macro. */
123	case PROCESSOR_max:	127	case PROCESSOR_max:
124	break;	128	break;
Lines 187-192 ix86_target_macros_internal (int isa_flag, Link Here
187	case PROCESSOR_CORE2:	191	case PROCESSOR_CORE2:
188	def_or_undef (parse_in, "__tune_core2__");	192	def_or_undef (parse_in, "__tune_core2__");
189	break;	193	break;
		194	case PROCESSOR_ATOM:
		195	def_or_undef (parse_in, "__tune_atom__");
		196	break;
190	case PROCESSOR_GENERIC32:	197	case PROCESSOR_GENERIC32:
191	case PROCESSOR_GENERIC64:	198	case PROCESSOR_GENERIC64:
192	break;	199	break;




  1,                                    /* cond_not_taken_branch_cost.  */
};

static const
struct processor_costs atom_cost = {
  COSTS_N_INSNS (1),			/* cost of an add instruction */
  COSTS_N_INSNS (1) + 1,		/* cost of a lea instruction */
  COSTS_N_INSNS (1),			/* variable shift costs */
  COSTS_N_INSNS (1),			/* constant shift costs */
  {COSTS_N_INSNS (3),			/* cost of starting multiply for QI */
   COSTS_N_INSNS (4),			/*                               HI */
   COSTS_N_INSNS (3),			/*                               SI */
   COSTS_N_INSNS (4),			/*                               DI */
   COSTS_N_INSNS (2)},			/*                               other */
  0,					/* cost of multiply per each bit set */
  {COSTS_N_INSNS (18),			/* cost of a divide/mod for QI */
   COSTS_N_INSNS (26),			/*                          HI */
   COSTS_N_INSNS (42),			/*                          SI */
   COSTS_N_INSNS (74),			/*                          DI */
   COSTS_N_INSNS (74)},			/*                          other */
  COSTS_N_INSNS (1),			/* cost of movsx */
  COSTS_N_INSNS (1),			/* cost of movzx */
  8,					/* "large" insn */
  17,					/* MOVE_RATIO */
  2,					/* cost for loading QImode using movzbl */
  {4, 4, 4},				/* cost of loading integer registers
					   in QImode, HImode and SImode.
					   Relative to reg-reg move (2).  */
  {4, 4, 4},				/* cost of storing integer registers */
  4,					/* cost of reg,reg fld/fst */
  {12, 12, 12},				/* cost of loading fp registers
					   in SFmode, DFmode and XFmode */
  {6, 6, 8},				/* cost of storing fp registers
					   in SFmode, DFmode and XFmode */
  2,					/* cost of moving MMX register */
  {8, 8},				/* cost of loading MMX registers
					   in SImode and DImode */
  {8, 8},				/* cost of storing MMX registers
					   in SImode and DImode */
  2,					/* cost of moving SSE register */
  {8, 8, 8},				/* cost of loading SSE registers
					   in SImode, DImode and TImode */
  {8, 8, 8},				/* cost of storing SSE registers
					   in SImode, DImode and TImode */
  5,					/* MMX or SSE register to integer */
  32,					/* size of l1 cache.  */
  256,					/* size of l2 cache.  */
  64,					/* size of prefetch block */
  6,					/* number of parallel prefetches */
  3,					/* Branch cost */
  COSTS_N_INSNS (8),			/* cost of FADD and FSUB insns.  */
  COSTS_N_INSNS (8),			/* cost of FMUL instruction.  */
  COSTS_N_INSNS (20),			/* cost of FDIV instruction.  */
  COSTS_N_INSNS (8),			/* cost of FABS instruction.  */
  COSTS_N_INSNS (8),			/* cost of FCHS instruction.  */
  COSTS_N_INSNS (40),			/* cost of FSQRT instruction.  */
  {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
   {libcall, {{32, loop}, {64, rep_prefix_4_byte},
          {8192, rep_prefix_8_byte}, {-1, libcall}}}},
  {{libcall, {{8, loop}, {15, unrolled_loop},
          {2048, rep_prefix_4_byte}, {-1, libcall}}},
   {libcall, {{24, loop}, {32, unrolled_loop},
          {8192, rep_prefix_8_byte}, {-1, libcall}}}},
  1,                                    /* scalar_stmt_cost.  */
  1,                                    /* scalar load_cost.  */
  1,                                    /* scalar_store_cost.  */
  1,                                    /* vec_stmt_cost.  */
  1,                                    /* vec_to_scalar_cost.  */
  1,                                    /* scalar_to_vec_cost.  */
  1,                                    /* vec_align_load_cost.  */
  2,                                    /* vec_unalign_load_cost.  */
  1,                                    /* vec_store_cost.  */
  3,                                    /* cond_taken_branch_cost.  */
  1,                                    /* cond_not_taken_branch_cost.  */
};

/* Generic64 should produce code tuned for Nocona and K8.  */
static const
struct processor_costs generic64_cost = {

#define m_PENT4  (1<<PROCESSOR_PENTIUM4)
#define m_NOCONA  (1<<PROCESSOR_NOCONA)
#define m_CORE2  (1<<PROCESSOR_CORE2)
#define m_ATOM  (1<<PROCESSOR_ATOM)

#define m_GEODE  (1<<PROCESSOR_GEODE)
#define m_K6  (1<<PROCESSOR_K6)

  m_486 | m_PENT,

  /* X86_TUNE_UNROLL_STRLEN */
  m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_DEEP_BRANCH_PREDICTION */
  m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,

  /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
     on simulation result. But after P4 was made, no performance benefit

  ~m_386,

  /* X86_TUNE_USE_SAHF */
  m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
  | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
     partial dependencies.  */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
  | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,

  /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial

  m_386 | m_486 | m_K6_GEODE,

  /* X86_TUNE_USE_SIMODE_FIOP */
  ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),

  /* X86_TUNE_USE_MOV0 */
  m_K6,

  /* X86_TUNE_USE_CLTD */
  ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),

  /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx.  */
  m_PENT4,

  ~(m_PENT | m_PPRO),

  /* X86_TUNE_PROMOTE_QIMODE */
  m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
  | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,

  /* X86_TUNE_FAST_PREFIX */
  ~(m_PENT | m_486 | m_386),

  m_PPRO,

  /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop.  */
  m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_ADD_ESP_8 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
  | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SUB_ESP_4 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_SUB_ESP_8 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
  | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
     for DFmode copies */
  ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
    | m_GENERIC | m_GEODE),

  /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
  m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
     conflict here in between PPro/Pentium4 based chips that thread 128bit

     shows that disabling this option on P4 brings over 20% SPECfp regression,
     while enabling it on K8 brings roughly 2.4% regression that can be partly
     masked by careful scheduling of moves.  */
  m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
  | m_AMDFAM10,

  /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
  m_AMDFAM10,

  m_PPRO | m_PENT4 | m_NOCONA,

  /* X86_TUNE_MEMORY_MISMATCH_STALL */
  m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_PROLOGUE_USING_MOVE */
  m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,

  /* X86_TUNE_EPILOGUE_USING_MOVE */
  m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SHIFT1 */
  ~m_486,

  m_AMD_MULTIPLE,

  /* X86_TUNE_INTER_UNIT_MOVES */
  ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),

  /* X86_TUNE_INTER_UNIT_CONVERSIONS */
  ~(m_AMDFAM10),

  /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
     than 4 branch instructions in the 16 byte window.  */
  m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_SCHEDULE */
  m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_USE_BT */
  m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,

  /* X86_TUNE_USE_INCDEC */
  ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),

  /* X86_TUNE_PAD_RETURNS */
  m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,

  /* X86_TUNE_EXT_80387_CONSTANTS */
  m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SHORTEN_X87_SSE */
  ~m_K8,

     with a subsequent conditional jump instruction into a single
     compare-and-branch uop.  */
  m_CORE2,

  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
  m_ATOM,
};

/* Feature tests against the various architecture variations.  */

};

static const unsigned int x86_accumulate_outgoing_args
  = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
    | m_GENERIC;

static const unsigned int x86_arch_always_fancy_math_387
  = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
    | m_NOCONA | m_CORE2 | m_GENERIC;

static enum stringop_alg stringop_alg = no_stringop;

  {&core2_cost, 16, 10, 16, 10, 16},
  {&generic32_cost, 16, 7, 16, 7, 16},
  {&generic64_cost, 16, 10, 16, 10, 16},
  {&amdfam10_cost, 32, 24, 32, 7, 32},
  {&atom_cost, 16, 7, 16, 7, 16}
};

static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =

  "prescott",
  "nocona",
  "core2",
  "atom",
  "geode",
  "k6",
  "k6-2",

      {"core2", PROCESSOR_CORE2, CPU_CORE2,
	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
	| PTA_SSSE3 | PTA_CX16},
      {"atom", PROCESSOR_ATOM, CPU_ATOM,
	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
	| PTA_SSSE3 | PTA_CX16},
      {"geode", PROCESSOR_GEODE, CPU_GEODE,
	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},

  switch (ix86_tune)
    {
    case PROCESSOR_PENTIUM:
    case PROCESSOR_ATOM:
    case PROCESSOR_K6:
      return 2;


    case PROCESSOR_ATHLON:
    case PROCESSOR_K8:
    case PROCESSOR_AMDFAM10:
    case PROCESSOR_ATOM:
    case PROCESSOR_GENERIC32:
    case PROCESSOR_GENERIC64:
      memory = get_attr_memory (insn);




#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)

/* Feature tests against the various tunings.  */
enum ix86_tune_indices {

  X86_TUNE_USE_VECTOR_FP_CONVERTS,
  X86_TUNE_USE_VECTOR_CONVERTS,
  X86_TUNE_FUSE_CMP_AND_BRANCH,
  X86_TUNE_OPT_AGU,

  X86_TUNE_LAST
};

	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
#define TARGET_FUSE_CMP_AND_BRANCH \
	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]

/* Feature tests against the various architecture variations.  */
enum ix86_arch_indices {

  TARGET_CPU_DEFAULT_prescott,
  TARGET_CPU_DEFAULT_nocona,
  TARGET_CPU_DEFAULT_core2,
  TARGET_CPU_DEFAULT_atom,

  TARGET_CPU_DEFAULT_geode,
  TARGET_CPU_DEFAULT_k6,

  PROCESSOR_GENERIC32,
  PROCESSOR_GENERIC64,
  PROCESSOR_AMDFAM10,
  PROCESSOR_ATOM,
  PROCESSOR_max
};


Lines 316-322 Link Here

(-)a/gcc/config/i386/i386.md (-15 / +57 lines)
316		316
317		317
318	;; Processor type.	318	;; Processor type.
319	(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,	319	(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
320	generic64,amdfam10"	320	generic64,amdfam10"
321	(const (symbol_ref "ix86_schedule")))	321	(const (symbol_ref "ix86_schedule")))
322		322
Lines 612-617 Link Here
612	(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"	612	(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
613	(const_string "any"))	613	(const_string "any"))
614		614
		615	;; Define attribute to classify add/sub insns that consumes carry flag (CF)
		616	(define_attr "use_carry" "0,1" (const_string "0"))
		617
		618	;; Define attribute to indicate unaligned ssemov insns
		619	(define_attr "movu" "0,1" (const_string "0"))
		620
615	;; Describe a user's asm statement.	621	;; Describe a user's asm statement.
616	(define_asm_attributes	622	(define_asm_attributes
617	[(set_attr "length" "128")	623	[(set_attr "length" "128")
Lines 727-732 Link Here
727	(include "k6.md")	733	(include "k6.md")
728	(include "athlon.md")	734	(include "athlon.md")
729	(include "geode.md")	735	(include "geode.md")
		736	(include "atom.md")
730		737
731		738
732	;; Operand and operator predicates and constraints	739	;; Operand and operator predicates and constraints
Lines 5816-5821 Link Here
5816	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"	5823	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5817	"adc{q}\t{%2, %0\|%0, %2}"	5824	"adc{q}\t{%2, %0\|%0, %2}"
5818	[(set_attr "type" "alu")	5825	[(set_attr "type" "alu")
		5826	(set_attr "use_carry" "1")
5819	(set_attr "pent_pair" "pu")	5827	(set_attr "pent_pair" "pu")
5820	(set_attr "mode" "DI")])	5828	(set_attr "mode" "DI")])
5821		5829
Lines 5890-5895 Link Here
5890	"ix86_binary_operator_ok (PLUS, QImode, operands)"	5898	"ix86_binary_operator_ok (PLUS, QImode, operands)"
5891	"adc{b}\t{%2, %0\|%0, %2}"	5899	"adc{b}\t{%2, %0\|%0, %2}"
5892	[(set_attr "type" "alu")	5900	[(set_attr "type" "alu")
		5901	(set_attr "use_carry" "1")
5893	(set_attr "pent_pair" "pu")	5902	(set_attr "pent_pair" "pu")
5894	(set_attr "mode" "QI")])	5903	(set_attr "mode" "QI")])
5895		5904
Lines 5902-5907 Link Here
5902	"ix86_binary_operator_ok (PLUS, HImode, operands)"	5911	"ix86_binary_operator_ok (PLUS, HImode, operands)"
5903	"adc{w}\t{%2, %0\|%0, %2}"	5912	"adc{w}\t{%2, %0\|%0, %2}"
5904	[(set_attr "type" "alu")	5913	[(set_attr "type" "alu")
		5914	(set_attr "use_carry" "1")
5905	(set_attr "pent_pair" "pu")	5915	(set_attr "pent_pair" "pu")
5906	(set_attr "mode" "HI")])	5916	(set_attr "mode" "HI")])
5907		5917
Lines 5914-5919 Link Here
5914	"ix86_binary_operator_ok (PLUS, SImode, operands)"	5924	"ix86_binary_operator_ok (PLUS, SImode, operands)"
5915	"adc{l}\t{%2, %0\|%0, %2}"	5925	"adc{l}\t{%2, %0\|%0, %2}"
5916	[(set_attr "type" "alu")	5926	[(set_attr "type" "alu")
		5927	(set_attr "use_carry" "1")
5917	(set_attr "pent_pair" "pu")	5928	(set_attr "pent_pair" "pu")
5918	(set_attr "mode" "SI")])	5929	(set_attr "mode" "SI")])
5919		5930
Lines 5927-5932 Link Here
5927	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"	5938	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5928	"adc{l}\t{%2, %k0\|%k0, %2}"	5939	"adc{l}\t{%2, %k0\|%k0, %2}"
5929	[(set_attr "type" "alu")	5940	[(set_attr "type" "alu")
		5941	(set_attr "use_carry" "1")
5930	(set_attr "pent_pair" "pu")	5942	(set_attr "pent_pair" "pu")
5931	(set_attr "mode" "SI")])	5943	(set_attr "mode" "SI")])
5932		5944
Lines 6156-6164 Link Here
6156	(set_attr "mode" "SI")])	6168	(set_attr "mode" "SI")])
6157		6169
6158	(define_insn "*adddi_1_rex64"	6170	(define_insn "*adddi_1_rex64"
6159	[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")	6171	[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
6160	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")	6172	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r")
6161	(match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))	6173	(match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le")))
6162	(clobber (reg:CC FLAGS_REG))]	6174	(clobber (reg:CC FLAGS_REG))]
6163	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"	6175	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
6164	{	6176	{
Lines 6179-6184 Link Here
6179	}	6191	}
6180		6192
6181	default:	6193	default:
		6194	/* Use add as much as possible to replace lea for AGU optimization. */
		6195	if (which_alternative == 2 && TARGET_OPT_AGU)
		6196	return "add{q}\t{%1, %0\|%0, %1}";
		6197
6182	gcc_assert (rtx_equal_p (operands[0], operands[1]));	6198	gcc_assert (rtx_equal_p (operands[0], operands[1]));
6183		6199
6184	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.	6200	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Lines 6197-6204 Link Here
6197	}	6213	}
6198	}	6214	}
6199	[(set (attr "type")	6215	[(set (attr "type")
6200	(cond [(eq_attr "alternative" "2")	6216	(cond [(and (eq_attr "alternative" "2")
		6217	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
6201	(const_string "lea")	6218	(const_string "lea")
		6219	(eq_attr "alternative" "3")
		6220	(const_string "lea")
6202	; Current assemblers are broken and do not allow @GOTOFF in	6221	; Current assemblers are broken and do not allow @GOTOFF in
6203	; ought but a memory context.	6222	; ought but a memory context.
6204	(match_operand:DI 2 "pic_symbolic_operand" "")	6223	(match_operand:DI 2 "pic_symbolic_operand" "")
Lines 6215-6222 Link Here
6215	(plus:DI (match_operand:DI 1 "register_operand" "")	6234	(plus:DI (match_operand:DI 1 "register_operand" "")
6216	(match_operand:DI 2 "x86_64_nonmemory_operand" "")))	6235	(match_operand:DI 2 "x86_64_nonmemory_operand" "")))
6217	(clobber (reg:CC FLAGS_REG))]	6236	(clobber (reg:CC FLAGS_REG))]
6218	"TARGET_64BIT && reload_completed	6237	"TARGET_64BIT && reload_completed"
6219	&& true_regnum (operands[0]) != true_regnum (operands[1])"
6220	[(set (match_dup 0)	6238	[(set (match_dup 0)
6221	(plus:DI (match_dup 1)	6239	(plus:DI (match_dup 1)
6222	(match_dup 2)))]	6240	(match_dup 2)))]
Lines 6420-6428 Link Here
6420		6438
6421		6439
6422	(define_insn "*addsi_1"	6440	(define_insn "*addsi_1"
6423	[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")	6441	[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r")
6424	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")	6442	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r")
6425	(match_operand:SI 2 "general_operand" "g,ri,li")))	6443	(match_operand:SI 2 "general_operand" "g,ri,0,li")))
6426	(clobber (reg:CC FLAGS_REG))]	6444	(clobber (reg:CC FLAGS_REG))]
6427	"ix86_binary_operator_ok (PLUS, SImode, operands)"	6445	"ix86_binary_operator_ok (PLUS, SImode, operands)"
6428	{	6446	{
Lines 6443-6448 Link Here
6443	}	6461	}
6444		6462
6445	default:	6463	default:
		6464	/* Use add as much as possible to replace lea for AGU optimization. */
		6465	if (which_alternative == 2 && TARGET_OPT_AGU)
		6466	return "add{l}\t{%1, %0\|%0, %1}";
		6467
6446	gcc_assert (rtx_equal_p (operands[0], operands[1]));	6468	gcc_assert (rtx_equal_p (operands[0], operands[1]));
6447		6469
6448	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.	6470	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Lines 6459-6465 Link Here
6459	}	6481	}
6460	}	6482	}
6461	[(set (attr "type")	6483	[(set (attr "type")
6462	(cond [(eq_attr "alternative" "2")	6484	(cond [(and (eq_attr "alternative" "2")
		6485	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
		6486	(const_string "lea")
		6487	(eq_attr "alternative" "3")
6463	(const_string "lea")	6488	(const_string "lea")
6464	; Current assemblers are broken and do not allow @GOTOFF in	6489	; Current assemblers are broken and do not allow @GOTOFF in
6465	; ought but a memory context.	6490	; ought but a memory context.
Lines 6477-6484 Link Here
6477	(plus (match_operand 1 "register_operand" "")	6502	(plus (match_operand 1 "register_operand" "")
6478	(match_operand 2 "nonmemory_operand" "")))	6503	(match_operand 2 "nonmemory_operand" "")))
6479	(clobber (reg:CC FLAGS_REG))]	6504	(clobber (reg:CC FLAGS_REG))]
6480	"reload_completed	6505	"reload_completed"
6481	&& true_regnum (operands[0]) != true_regnum (operands[1])"
6482	[(const_int 0)]	6506	[(const_int 0)]
6483	{	6507	{
6484	rtx pat;	6508	rtx pat;
Lines 7580-7585 Link Here
7580	"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"	7604	"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
7581	"sbb{q}\t{%2, %0\|%0, %2}"	7605	"sbb{q}\t{%2, %0\|%0, %2}"
7582	[(set_attr "type" "alu")	7606	[(set_attr "type" "alu")
		7607	(set_attr "use_carry" "1")
7583	(set_attr "pent_pair" "pu")	7608	(set_attr "pent_pair" "pu")
7584	(set_attr "mode" "DI")])	7609	(set_attr "mode" "DI")])
7585		7610
Lines 7628-7633 Link Here
7628	"ix86_binary_operator_ok (MINUS, QImode, operands)"	7653	"ix86_binary_operator_ok (MINUS, QImode, operands)"
7629	"sbb{b}\t{%2, %0\|%0, %2}"	7654	"sbb{b}\t{%2, %0\|%0, %2}"
7630	[(set_attr "type" "alu")	7655	[(set_attr "type" "alu")
		7656	(set_attr "use_carry" "1")
7631	(set_attr "pent_pair" "pu")	7657	(set_attr "pent_pair" "pu")
7632	(set_attr "mode" "QI")])	7658	(set_attr "mode" "QI")])
7633		7659
Lines 7640-7645 Link Here
7640	"ix86_binary_operator_ok (MINUS, HImode, operands)"	7666	"ix86_binary_operator_ok (MINUS, HImode, operands)"
7641	"sbb{w}\t{%2, %0\|%0, %2}"	7667	"sbb{w}\t{%2, %0\|%0, %2}"
7642	[(set_attr "type" "alu")	7668	[(set_attr "type" "alu")
		7669	(set_attr "use_carry" "1")
7643	(set_attr "pent_pair" "pu")	7670	(set_attr "pent_pair" "pu")
7644	(set_attr "mode" "HI")])	7671	(set_attr "mode" "HI")])
7645		7672
Lines 7652-7657 Link Here
7652	"ix86_binary_operator_ok (MINUS, SImode, operands)"	7679	"ix86_binary_operator_ok (MINUS, SImode, operands)"
7653	"sbb{l}\t{%2, %0\|%0, %2}"	7680	"sbb{l}\t{%2, %0\|%0, %2}"
7654	[(set_attr "type" "alu")	7681	[(set_attr "type" "alu")
		7682	(set_attr "use_carry" "1")
7655	(set_attr "pent_pair" "pu")	7683	(set_attr "pent_pair" "pu")
7656	(set_attr "mode" "SI")])	7684	(set_attr "mode" "SI")])
7657		7685
Lines 15275-15280 Link Here
15275	"reload_completed"	15303	"reload_completed"
15276	"ret"	15304	"ret"
15277	[(set_attr "length" "1")	15305	[(set_attr "length" "1")
		15306	(set_attr "atom_unit" "jeu")
15278	(set_attr "length_immediate" "0")	15307	(set_attr "length_immediate" "0")
15279	(set_attr "modrm" "0")])	15308	(set_attr "modrm" "0")])
15280		15309
Lines 15287-15292 Link Here
15287	"reload_completed"	15316	"reload_completed"
15288	"rep\;ret"	15317	"rep\;ret"
15289	[(set_attr "length" "1")	15318	[(set_attr "length" "1")
		15319	(set_attr "atom_unit" "jeu")
15290	(set_attr "length_immediate" "0")	15320	(set_attr "length_immediate" "0")
15291	(set_attr "prefix_rep" "1")	15321	(set_attr "prefix_rep" "1")
15292	(set_attr "modrm" "0")])	15322	(set_attr "modrm" "0")])
Lines 15297-15302 Link Here
15297	"reload_completed"	15327	"reload_completed"
15298	"ret\t%0"	15328	"ret\t%0"
15299	[(set_attr "length" "3")	15329	[(set_attr "length" "3")
		15330	(set_attr "atom_unit" "jeu")
15300	(set_attr "length_immediate" "2")	15331	(set_attr "length_immediate" "2")
15301	(set_attr "modrm" "0")])	15332	(set_attr "modrm" "0")])
15302		15333
Lines 16418-16423 Link Here
16418	"TARGET_SSE_MATH"	16449	"TARGET_SSE_MATH"
16419	"%vrcpss\t{%1, %d0\|%d0, %1}"	16450	"%vrcpss\t{%1, %d0\|%d0, %1}"
16420	[(set_attr "type" "sse")	16451	[(set_attr "type" "sse")
		16452	(set_attr "atom_sse_attr" "rcp")
16421	(set_attr "prefix" "maybe_vex")	16453	(set_attr "prefix" "maybe_vex")
16422	(set_attr "mode" "SF")])	16454	(set_attr "mode" "SF")])
16423		16455
Lines 16777-16782 Link Here
16777	"TARGET_SSE_MATH"	16809	"TARGET_SSE_MATH"
16778	"%vrsqrtss\t{%1, %d0\|%d0, %1}"	16810	"%vrsqrtss\t{%1, %d0\|%d0, %1}"
16779	[(set_attr "type" "sse")	16811	[(set_attr "type" "sse")
		16812	(set_attr "atom_sse_attr" "rcp")
16780	(set_attr "prefix" "maybe_vex")	16813	(set_attr "prefix" "maybe_vex")
16781	(set_attr "mode" "SF")])	16814	(set_attr "mode" "SF")])
16782		16815
Lines 16797-16802 Link Here
16797	"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"	16830	"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16798	"%vsqrts<ssemodefsuffix>\t{%1, %d0\|%d0, %1}"	16831	"%vsqrts<ssemodefsuffix>\t{%1, %d0\|%d0, %1}"
16799	[(set_attr "type" "sse")	16832	[(set_attr "type" "sse")
		16833	(set_attr "atom_sse_attr" "sqrt")
16800	(set_attr "prefix" "maybe_vex")	16834	(set_attr "prefix" "maybe_vex")
16801	(set_attr "mode" "<MODE>")	16835	(set_attr "mode" "<MODE>")
16802	(set_attr "athlon_decode" "*")	16836	(set_attr "athlon_decode" "*")
Lines 19850-19855 Link Here
19850	; Since we don't have the proper number of operands for an alu insn,	19884	; Since we don't have the proper number of operands for an alu insn,
19851	; fill in all the blanks.	19885	; fill in all the blanks.
19852	[(set_attr "type" "alu")	19886	[(set_attr "type" "alu")
		19887	(set_attr "use_carry" "1")
19853	(set_attr "pent_pair" "pu")	19888	(set_attr "pent_pair" "pu")
19854	(set_attr "memory" "none")	19889	(set_attr "memory" "none")
19855	(set_attr "imm_disp" "false")	19890	(set_attr "imm_disp" "false")
Lines 19865-19870 Link Here
19865	""	19900	""
19866	"sbb{q}\t%0, %0"	19901	"sbb{q}\t%0, %0"
19867	[(set_attr "type" "alu")	19902	[(set_attr "type" "alu")
		19903	(set_attr "use_carry" "1")
19868	(set_attr "pent_pair" "pu")	19904	(set_attr "pent_pair" "pu")
19869	(set_attr "memory" "none")	19905	(set_attr "memory" "none")
19870	(set_attr "imm_disp" "false")	19906	(set_attr "imm_disp" "false")
Lines 19908-19913 Link Here
19908	; Since we don't have the proper number of operands for an alu insn,	19944	; Since we don't have the proper number of operands for an alu insn,
19909	; fill in all the blanks.	19945	; fill in all the blanks.
19910	[(set_attr "type" "alu")	19946	[(set_attr "type" "alu")
		19947	(set_attr "use_carry" "1")
19911	(set_attr "pent_pair" "pu")	19948	(set_attr "pent_pair" "pu")
19912	(set_attr "memory" "none")	19949	(set_attr "memory" "none")
19913	(set_attr "imm_disp" "false")	19950	(set_attr "imm_disp" "false")
Lines 19923-19928 Link Here
19923	""	19960	""
19924	"sbb{l}\t%0, %0"	19961	"sbb{l}\t%0, %0"
19925	[(set_attr "type" "alu")	19962	[(set_attr "type" "alu")
		19963	(set_attr "use_carry" "1")
19926	(set_attr "pent_pair" "pu")	19964	(set_attr "pent_pair" "pu")
19927	(set_attr "memory" "none")	19965	(set_attr "memory" "none")
19928	(set_attr "imm_disp" "false")	19966	(set_attr "imm_disp" "false")
Lines 20255-20261 Link Here
20255	}	20293	}
20256	}	20294	}
20257	[(set (attr "type")	20295	[(set (attr "type")
20258	(cond [(eq_attr "alternative" "0")	20296	(cond [(and (eq_attr "alternative" "0")
		20297	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
20259	(const_string "alu")	20298	(const_string "alu")
20260	(match_operand:SI 2 "const0_operand" "")	20299	(match_operand:SI 2 "const0_operand" "")
20261	(const_string "imov")	20300	(const_string "imov")
Lines 20298-20304 Link Here
20298	}	20337	}
20299	}	20338	}
20300	[(set (attr "type")	20339	[(set (attr "type")
20301	(cond [(eq_attr "alternative" "0")	20340	(cond [(and (eq_attr "alternative" "0")
		20341	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
20302	(const_string "alu")	20342	(const_string "alu")
20303	(match_operand:DI 2 "const0_operand" "")	20343	(match_operand:DI 2 "const0_operand" "")
20304	(const_string "imov")	20344	(const_string "imov")
Lines 21790-21795 Link Here
21790	return patterns[locality];	21830	return patterns[locality];
21791	}	21831	}
21792	[(set_attr "type" "sse")	21832	[(set_attr "type" "sse")
		21833	(set_attr "atom_sse_attr" "prefetch")
21793	(set_attr "memory" "none")])	21834	(set_attr "memory" "none")])
21794		21835
21795	(define_insn "*prefetch_sse_rex"	21836	(define_insn "*prefetch_sse_rex"
Lines 21808-21813 Link Here
21808	return patterns[locality];	21849	return patterns[locality];
21809	}	21850	}
21810	[(set_attr "type" "sse")	21851	[(set_attr "type" "sse")
		21852	(set_attr "atom_sse_attr" "prefetch")
21811	(set_attr "memory" "none")])	21853	(set_attr "memory" "none")])
21812		21854
21813	(define_insn "*prefetch_3dnow"	21855	(define_insn "*prefetch_3dnow"




   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<MODE>")])


   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "mode" "<MODE>")])

(define_insn "avx_movdqu<avxmodesuffix>"

  "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "vmovdqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<avxvecmode>")])


  "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "movdqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


		     UNSPEC_MOVNT))]
  "TARGET_SSE2"
  "movntdq\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


		   UNSPEC_MOVNT))]
  "TARGET_SSE2"
  "movnti\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "mode" "V2DF")])

(define_insn "avx_lddqu<avxmodesuffix>"

  "TARGET_AVX"
  "vlddqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssecvt")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<avxvecmode>")])


		      UNSPEC_LDDQU))]
  "TARGET_SSE3"
  "lddqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix_rep" "1")
   (set_attr "mode" "TI")])


  "TARGET_SSE"
  "%vrcpps\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "rcp")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "V4SF")])


  "TARGET_SSE"
  "rcpss\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "rcp")
   (set_attr "mode" "SF")])

(define_expand "sqrtv8sf2"

  "TARGET_SSE"
  "%vsqrtps\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "sqrt")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "V4SF")])


  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "sqrt")
   (set_attr "mode" "<ssescalarmode>")])

(define_expand "rsqrtv8sf2"

	 (const_int 1)))]
  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "mode" "<ssescalarmode>")])

;; These versions of the min/max patterns implement exactly the operations

  "TARGET_SSE3"
  "addsubpd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "atom_unit" "complex")
   (set_attr "mode" "V2DF")])

(define_insn "avx_h<plusminus_insn>v4df3"

  "TARGET_SSE3"
  "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_rep" "1")
   (set_attr "mode" "V4SF")])


  "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
  "pmaddwd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


   movq\t{%H1, %0|%0, %H1}
   mov{q}\t{%H1, %0|%0, %H1}"
  [(set_attr "type" "ssemov,sseishft,ssemov,imov")
   (set_attr "atom_unit" "*,sishuf,*,*")
   (set_attr "memory" "*,none,*,*")
   (set_attr "mode" "V2SF,TI,TI,DI")])


   psrldq\t{$8, %0|%0, 8}
   movq\t{%H1, %0|%0, %H1}"
  [(set_attr "type" "ssemov,sseishft,ssemov")
   (set_attr "atom_unit" "*,sishuf,*")
   (set_attr "memory" "*,none,*")
   (set_attr "mode" "V2SF,TI,TI")])


  "TARGET_SSE2"
  "psadbw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


	  UNSPEC_MOVMSK))]
  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "<MODE>")])


		   UNSPEC_MOVMSK))]
  "TARGET_SSE2"
  "%vpmovmskb\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "SI")])

  "TARGET_SSE2 && !TARGET_64BIT"
  ;; @@@ check ordering of operands in intel/nonintel syntax
  "%vmaskmovdqu\t{%2, %1|%1, %2}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

  "TARGET_SSE2 && TARGET_64BIT"
  ;; @@@ check ordering of operands in intel/nonintel syntax
  "%vmaskmovdqu\t{%2, %1|%1, %2}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

  "TARGET_SSE"
  "%vldmxcsr\t%0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "mxcsr")
   (set_attr "prefix" "maybe_vex")
   (set_attr "memory" "load")])


  "TARGET_SSE"
  "%vstmxcsr\t%0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "mxcsr")
   (set_attr "prefix" "maybe_vex")
   (set_attr "memory" "store")])


  "TARGET_SSE || TARGET_3DNOW_A"
  "sfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_insn "sse2_clflush"

  "TARGET_SSE2"
  "clflush\t%a0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_expand "sse2_mfence"

  "TARGET_64BIT || TARGET_SSE2"
  "mfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_expand "sse2_lfence"

  "TARGET_SSE2"
  "lfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "lfence")
   (set_attr "memory" "unknown")])

(define_insn "sse3_mwait"

  "TARGET_SSSE3"
  "phaddw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phaddd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phaddsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "pmaddubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "pmaddubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
  [(set_attr "type" "sseishft")
   (set_attr "atom_unit" "sishuf")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
  [(set_attr "type" "sseishft")
   (set_attr "atom_unit" "sishuf")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


		     UNSPEC_MOVNTDQA))]
  "TARGET_SSE4_1"
  "%vmovntdqa\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_extra" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

Return to bug 262603

Lines 1074-1080 i[34567]86--linux \| i[34567]86--kfreebsd-gnu \| i[34567]86--knetbsd-gnu \| i Link Here

(-)a/gcc/config.gcc (-5 / +5 lines)
1074	tmake_file="${tmake_file} i386/t-linux64"	1074	tmake_file="${tmake_file} i386/t-linux64"
1075	need_64bit_hwint=yes	1075	need_64bit_hwint=yes
1076	case X"${with_cpu}" in	1076	case X"${with_cpu}" in
1077	Xgeneric\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)	1077	Xgeneric\|Xatom\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)
1078	;;	1078	;;
1079	X)	1079	X)
1080	if test x$with_cpu_64 = x; then	1080	if test x$with_cpu_64 = x; then
Lines 1083-1089 i[34567]86--linux \| i[34567]86--kfreebsd-gnu \| i[34567]86--knetbsd-gnu \| i Link Here
1083	;;	1083	;;
1084	*)	1084	*)
1085	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2	1085	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1086	echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2	1086	echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1087	exit 1	1087	exit 1
1088	;;	1088	;;
1089	esac	1089	esac
Lines 1189-1195 i[34567]86--solaris2) Link Here
1189	need_64bit_hwint=yes	1189	need_64bit_hwint=yes
1190	use_gcc_stdint=wrap	1190	use_gcc_stdint=wrap
1191	case X"${with_cpu}" in	1191	case X"${with_cpu}" in
1192	Xgeneric\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)	1192	Xgeneric\|Xatom\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)
1193	;;	1193	;;
1194	X)	1194	X)
1195	if test x$with_cpu_64 = x; then	1195	if test x$with_cpu_64 = x; then
Lines 1198-1204 i[34567]86--solaris2) Link Here
1198	;;	1198	;;
1199	*)	1199	*)
1200	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2	1200	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1201	echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2	1201	echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1202	exit 1	1202	exit 1
1203	;;	1203	;;
1204	esac	1204	esac
Lines 2801-2807 case "${target}" in Link Here
2801	esac	2801	esac
2802	# OK	2802	# OK
2803	;;	2803	;;
2804	"" \| amdfam10 \| barcelona \| k8 \| opteron \| athlon64 \| athlon-fx \| nocona \| core2 \| generic)	2804	"" \| amdfam10 \| barcelona \| k8 \| opteron \| athlon64 \| athlon-fx \| nocona \| core2 \| atom \| generic)
2805	# OK	2805	# OK
2806	;;	2806	;;
2807	*)	2807	*)

Lines 1036-1041 struct processor_costs core2_cost = { Link Here

(-)a/gcc/config/i386/i386.c (-27 / +120 lines)
1036	1, /* cond_not_taken_branch_cost. */	1036	1, /* cond_not_taken_branch_cost. */
1037	};	1037	};
1038		1038
		1039	static const
		1040	struct processor_costs atom_cost = {
		1041	COSTS_N_INSNS (1), /* cost of an add instruction */
		1042	COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
		1043	COSTS_N_INSNS (1), /* variable shift costs */
		1044	COSTS_N_INSNS (1), /* constant shift costs */
		1045	{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
		1046	COSTS_N_INSNS (4), /* HI */
		1047	COSTS_N_INSNS (3), /* SI */
		1048	COSTS_N_INSNS (4), /* DI */
		1049	COSTS_N_INSNS (2)}, /* other */
		1050	0, /* cost of multiply per each bit set */
		1051	{COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
		1052	COSTS_N_INSNS (26), /* HI */
		1053	COSTS_N_INSNS (42), /* SI */
		1054	COSTS_N_INSNS (74), /* DI */
		1055	COSTS_N_INSNS (74)}, /* other */
		1056	COSTS_N_INSNS (1), /* cost of movsx */
		1057	COSTS_N_INSNS (1), /* cost of movzx */
		1058	8, /* "large" insn */
		1059	17, /* MOVE_RATIO */
		1060	2, /* cost for loading QImode using movzbl */
		1061	{4, 4, 4}, /* cost of loading integer registers
		1062	in QImode, HImode and SImode.
		1063	Relative to reg-reg move (2). */
		1064	{4, 4, 4}, /* cost of storing integer registers */
		1065	4, /* cost of reg,reg fld/fst */
		1066	{12, 12, 12}, /* cost of loading fp registers
		1067	in SFmode, DFmode and XFmode */
		1068	{6, 6, 8}, /* cost of storing fp registers
		1069	in SFmode, DFmode and XFmode */
		1070	2, /* cost of moving MMX register */
		1071	{8, 8}, /* cost of loading MMX registers
		1072	in SImode and DImode */
		1073	{8, 8}, /* cost of storing MMX registers
		1074	in SImode and DImode */
		1075	2, /* cost of moving SSE register */
		1076	{8, 8, 8}, /* cost of loading SSE registers
		1077	in SImode, DImode and TImode */
		1078	{8, 8, 8}, /* cost of storing SSE registers
		1079	in SImode, DImode and TImode */
		1080	5, /* MMX or SSE register to integer */
		1081	32, /* size of l1 cache. */
		1082	256, /* size of l2 cache. */
		1083	64, /* size of prefetch block */
		1084	6, /* number of parallel prefetches */
		1085	3, /* Branch cost */
		1086	COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
		1087	COSTS_N_INSNS (8), /* cost of FMUL instruction. */
		1088	COSTS_N_INSNS (20), /* cost of FDIV instruction. */
		1089	COSTS_N_INSNS (8), /* cost of FABS instruction. */
		1090	COSTS_N_INSNS (8), /* cost of FCHS instruction. */
		1091	COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
		1092	{{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
		1093	{libcall, {{32, loop}, {64, rep_prefix_4_byte},
		1094	{8192, rep_prefix_8_byte}, {-1, libcall}}}},
		1095	{{libcall, {{8, loop}, {15, unrolled_loop},
		1096	{2048, rep_prefix_4_byte}, {-1, libcall}}},
		1097	{libcall, {{24, loop}, {32, unrolled_loop},
		1098	{8192, rep_prefix_8_byte}, {-1, libcall}}}},
		1099	1, /* scalar_stmt_cost. */
		1100	1, /* scalar load_cost. */
		1101	1, /* scalar_store_cost. */
		1102	1, /* vec_stmt_cost. */
1103	1, /* vec_to_scalar_cost. */
1104	1, /* scalar_to_vec_cost. */
1105	1, /* vec_align_load_cost. */
1106	2, /* vec_unalign_load_cost. */
1107	1, /* vec_store_cost. */
1108	3, /* cond_taken_branch_cost. */
1109	1, /* cond_not_taken_branch_cost. */
1110	};
1111
1039	/* Generic64 should produce code tuned for Nocona and K8. */	1112	/* Generic64 should produce code tuned for Nocona and K8. */
1040	static const	1113	static const
1041	struct processor_costs generic64_cost = {	1114	struct processor_costs generic64_cost = {
Lines 1194-1199 const struct processor_costs *ix86_cost = &pentium_cost; Link Here
1194	#define m_PENT4 (1<<PROCESSOR_PENTIUM4)	1267	#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195	#define m_NOCONA (1<<PROCESSOR_NOCONA)	1268	#define m_NOCONA (1<<PROCESSOR_NOCONA)
1196	#define m_CORE2 (1<<PROCESSOR_CORE2)	1269	#define m_CORE2 (1<<PROCESSOR_CORE2)
		1270	#define m_ATOM (1<<PROCESSOR_ATOM)
1197		1271
1198	#define m_GEODE (1<<PROCESSOR_GEODE)	1272	#define m_GEODE (1<<PROCESSOR_GEODE)
1199	#define m_K6 (1<<PROCESSOR_K6)	1273	#define m_K6 (1<<PROCESSOR_K6)
Lines 1231-1240 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1231	m_486 \| m_PENT,	1305	m_486 \| m_PENT,
1232		1306
1233	/* X86_TUNE_UNROLL_STRLEN */	1307	/* X86_TUNE_UNROLL_STRLEN */
1234	m_486 \| m_PENT \| m_PPRO \| m_AMD_MULTIPLE \| m_K6 \| m_CORE2 \| m_GENERIC,	1308	m_486 \| m_PENT \| m_ATOM \| m_PPRO \| m_AMD_MULTIPLE \| m_K6
		1309	\| m_CORE2 \| m_GENERIC,
1235		1310
1236	/* X86_TUNE_DEEP_BRANCH_PREDICTION */	1311	/* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237	m_PPRO \| m_K6_GEODE \| m_AMD_MULTIPLE \| m_PENT4 \| m_GENERIC,	1312	m_ATOM \| m_PPRO \| m_K6_GEODE \| m_AMD_MULTIPLE \| m_PENT4 \| m_GENERIC,
1238		1313
1239	/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based	1314	/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240	on simulation result. But after P4 was made, no performance benefit	1315	on simulation result. But after P4 was made, no performance benefit
Lines 1246-1257 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1246	~m_386,	1321	~m_386,
1247		1322
1248	/* X86_TUNE_USE_SAHF */	1323	/* X86_TUNE_USE_SAHF */
1249	m_PPRO \| m_K6_GEODE \| m_K8 \| m_AMDFAM10 \| m_PENT4	1324	m_ATOM \| m_PPRO \| m_K6_GEODE \| m_K8 \| m_AMDFAM10 \| m_PENT4
1250	\| m_NOCONA \| m_CORE2 \| m_GENERIC,	1325	\| m_NOCONA \| m_CORE2 \| m_GENERIC,
1251		1326
1252	/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid	1327	/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253	partial dependencies. */	1328	partial dependencies. */
1254	m_AMD_MULTIPLE \| m_PPRO \| m_PENT4 \| m_NOCONA	1329	m_AMD_MULTIPLE \| m_ATOM \| m_PPRO \| m_PENT4 \| m_NOCONA
1255	\| m_CORE2 \| m_GENERIC \| m_GEODE /* m_386 \| m_K6 */,	1330	\| m_CORE2 \| m_GENERIC \| m_GEODE /* m_386 \| m_K6 */,
1256		1331
1257	/* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial	1332	/* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
Lines 1271-1283 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1271	m_386 \| m_486 \| m_K6_GEODE,	1346	m_386 \| m_486 \| m_K6_GEODE,
1272		1347
1273	/* X86_TUNE_USE_SIMODE_FIOP */	1348	/* X86_TUNE_USE_SIMODE_FIOP */
1274	~(m_PPRO \| m_AMD_MULTIPLE \| m_PENT \| m_CORE2 \| m_GENERIC),	1349	~(m_PPRO \| m_AMD_MULTIPLE \| m_PENT \| m_ATOM \| m_CORE2 \| m_GENERIC),
1275		1350
1276	/* X86_TUNE_USE_MOV0 */	1351	/* X86_TUNE_USE_MOV0 */
1277	m_K6,	1352	m_K6,
1278		1353
1279	/* X86_TUNE_USE_CLTD */	1354	/* X86_TUNE_USE_CLTD */
1280	~(m_PENT \| m_K6 \| m_CORE2 \| m_GENERIC),	1355	~(m_PENT \| m_ATOM \| m_K6 \| m_CORE2 \| m_GENERIC),
1281		1356
1282	/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */	1357	/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1283	m_PENT4,	1358	m_PENT4,
Lines 1292-1299 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1292	~(m_PENT \| m_PPRO),	1367	~(m_PENT \| m_PPRO),
1293		1368
1294	/* X86_TUNE_PROMOTE_QIMODE */	1369	/* X86_TUNE_PROMOTE_QIMODE */
1295	m_K6_GEODE \| m_PENT \| m_386 \| m_486 \| m_AMD_MULTIPLE \| m_CORE2	1370	m_K6_GEODE \| m_PENT \| m_ATOM \| m_386 \| m_486 \| m_AMD_MULTIPLE
1296	\| m_GENERIC /* \| m_PENT4 ? */,	1371	\| m_CORE2 \| m_GENERIC /* \| m_PENT4 ? */,
1297		1372
1298	/* X86_TUNE_FAST_PREFIX */	1373	/* X86_TUNE_FAST_PREFIX */
1299	~(m_PENT \| m_486 \| m_386),	1374	~(m_PENT \| m_486 \| m_386),
Lines 1317-1342 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1317	m_PPRO,	1392	m_PPRO,
1318		1393
1319	/* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */	1394	/* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320	m_AMD_MULTIPLE \| m_K6_GEODE \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1395	m_ATOM \| m_AMD_MULTIPLE \| m_K6_GEODE \| m_PENT4 \| m_NOCONA
		1396	\| m_CORE2 \| m_GENERIC,
1321		1397
1322	/* X86_TUNE_ADD_ESP_8 */	1398	/* X86_TUNE_ADD_ESP_8 */
1323	m_AMD_MULTIPLE \| m_PPRO \| m_K6_GEODE \| m_386	1399	m_AMD_MULTIPLE \| m_ATOM \| m_PPRO \| m_K6_GEODE \| m_386
1324	\| m_486 \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1400	\| m_486 \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,
1325		1401
1326	/* X86_TUNE_SUB_ESP_4 */	1402	/* X86_TUNE_SUB_ESP_4 */
1327	m_AMD_MULTIPLE \| m_PPRO \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1403	m_AMD_MULTIPLE \| m_ATOM \| m_PPRO \| m_PENT4 \| m_NOCONA \| m_CORE2
		1404	\| m_GENERIC,
1328		1405
1329	/* X86_TUNE_SUB_ESP_8 */	1406	/* X86_TUNE_SUB_ESP_8 */
1330	m_AMD_MULTIPLE \| m_PPRO \| m_386 \| m_486	1407	m_AMD_MULTIPLE \| m_ATOM \| m_PPRO \| m_386 \| m_486
1331	\| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1408	\| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,
1332		1409
1333	/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred	1410	/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334	for DFmode copies */	1411	for DFmode copies */
1335	~(m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2	1412	~(m_AMD_MULTIPLE \| m_ATOM \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2
1336	\| m_GENERIC \| m_GEODE),	1413	\| m_GENERIC \| m_GEODE),
1337		1414
1338	/* X86_TUNE_PARTIAL_REG_DEPENDENCY */	1415	/* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339	m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1416	m_AMD_MULTIPLE \| m_ATOM \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,
1340		1417
1341	/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a	1418	/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342	conflict here in between PPro/Pentium4 based chips that thread 128bit	1419	conflict here in between PPro/Pentium4 based chips that thread 128bit
Lines 1347-1353 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1347	shows that disabling this option on P4 brings over 20% SPECfp regression,	1424	shows that disabling this option on P4 brings over 20% SPECfp regression,
1348	while enabling it on K8 brings roughly 2.4% regression that can be partly	1425	while enabling it on K8 brings roughly 2.4% regression that can be partly
1349	masked by careful scheduling of moves. */	1426	masked by careful scheduling of moves. */
1350	m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2 \| m_GENERIC \| m_AMDFAM10,	1427	m_ATOM \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2 \| m_GENERIC
		1428	\| m_AMDFAM10,
1351		1429
1352	/* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */	1430	/* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1353	m_AMDFAM10,	1431	m_AMDFAM10,
Lines 1365-1377 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1365	m_PPRO \| m_PENT4 \| m_NOCONA,	1443	m_PPRO \| m_PENT4 \| m_NOCONA,
1366		1444
1367	/* X86_TUNE_MEMORY_MISMATCH_STALL */	1445	/* X86_TUNE_MEMORY_MISMATCH_STALL */
1368	m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1446	m_AMD_MULTIPLE \| m_ATOM \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,
1369		1447
1370	/* X86_TUNE_PROLOGUE_USING_MOVE */	1448	/* X86_TUNE_PROLOGUE_USING_MOVE */
1371	m_ATHLON_K8 \| m_PPRO \| m_CORE2 \| m_GENERIC,	1449	m_ATHLON_K8 \| m_ATOM \| m_PPRO \| m_CORE2 \| m_GENERIC,
1372		1450
1373	/* X86_TUNE_EPILOGUE_USING_MOVE */	1451	/* X86_TUNE_EPILOGUE_USING_MOVE */
1374	m_ATHLON_K8 \| m_PPRO \| m_CORE2 \| m_GENERIC,	1452	m_ATHLON_K8 \| m_ATOM \| m_PPRO \| m_CORE2 \| m_GENERIC,
1375		1453
1376	/* X86_TUNE_SHIFT1 */	1454	/* X86_TUNE_SHIFT1 */
1377	~m_486,	1455	~m_486,
Lines 1380-1408 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1380	m_AMD_MULTIPLE,	1458	m_AMD_MULTIPLE,
1381		1459
1382	/* X86_TUNE_INTER_UNIT_MOVES */	1460	/* X86_TUNE_INTER_UNIT_MOVES */
1383	~(m_AMD_MULTIPLE \| m_GENERIC),	1461	~(m_AMD_MULTIPLE \| m_ATOM \| m_GENERIC),
1384		1462
1385	/* X86_TUNE_INTER_UNIT_CONVERSIONS */	1463	/* X86_TUNE_INTER_UNIT_CONVERSIONS */
1386	~(m_AMDFAM10),	1464	~(m_AMDFAM10),
1387		1465
1388	/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more	1466	/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389	than 4 branch instructions in the 16 byte window. */	1467	than 4 branch instructions in the 16 byte window. */
1390	m_PPRO \| m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_CORE2 \| m_GENERIC,	1468	m_ATOM \| m_PPRO \| m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_CORE2
		1469	\| m_GENERIC,
1391		1470
1392	/* X86_TUNE_SCHEDULE */	1471	/* X86_TUNE_SCHEDULE */
1393	m_PPRO \| m_AMD_MULTIPLE \| m_K6_GEODE \| m_PENT \| m_CORE2 \| m_GENERIC,	1472	m_PPRO \| m_AMD_MULTIPLE \| m_K6_GEODE \| m_PENT \| m_ATOM \| m_CORE2
		1473	\| m_GENERIC,
1394		1474
1395	/* X86_TUNE_USE_BT */	1475	/* X86_TUNE_USE_BT */
1396	m_AMD_MULTIPLE \| m_CORE2 \| m_GENERIC,	1476	m_AMD_MULTIPLE \| m_ATOM \| m_CORE2 \| m_GENERIC,
1397		1477
1398	/* X86_TUNE_USE_INCDEC */	1478	/* X86_TUNE_USE_INCDEC */
1399	~(m_PENT4 \| m_NOCONA \| m_GENERIC),	1479	~(m_PENT4 \| m_NOCONA \| m_GENERIC \| m_ATOM),
1400		1480
1401	/* X86_TUNE_PAD_RETURNS */	1481	/* X86_TUNE_PAD_RETURNS */
1402	m_AMD_MULTIPLE \| m_CORE2 \| m_GENERIC,	1482	m_AMD_MULTIPLE \| m_CORE2 \| m_GENERIC,
1403		1483
1404	/* X86_TUNE_EXT_80387_CONSTANTS */	1484	/* X86_TUNE_EXT_80387_CONSTANTS */
1405	m_K6_GEODE \| m_ATHLON_K8 \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2 \| m_GENERIC,	1485	m_K6_GEODE \| m_ATHLON_K8 \| m_ATOM \| m_PENT4 \| m_NOCONA \| m_PPRO
		1486	\| m_CORE2 \| m_GENERIC,
1406		1487
1407	/* X86_TUNE_SHORTEN_X87_SSE */	1488	/* X86_TUNE_SHORTEN_X87_SSE */
1408	~m_K8,	1489	~m_K8,
Lines 1447-1452 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { Link Here
1447	with a subsequent conditional jump instruction into a single	1528	with a subsequent conditional jump instruction into a single
1448	compare-and-branch uop. */	1529	compare-and-branch uop. */
1449	m_CORE2,	1530	m_CORE2,
		1531
		1532	/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
		1533	will impact LEA instruction selection. */
		1534	m_ATOM,
1450	};	1535	};
1451		1536
1452	/* Feature tests against the various architecture variations. */	1537	/* Feature tests against the various architecture variations. */
Lines 1472-1481 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = { Link Here
1472	};	1557	};
1473		1558
1474	static const unsigned int x86_accumulate_outgoing_args	1559	static const unsigned int x86_accumulate_outgoing_args
1475	= m_AMD_MULTIPLE \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2 \| m_GENERIC;	1560	= m_AMD_MULTIPLE \| m_ATOM \| m_PENT4 \| m_NOCONA \| m_PPRO \| m_CORE2
		1561	\| m_GENERIC;
1476		1562
1477	static const unsigned int x86_arch_always_fancy_math_387	1563	static const unsigned int x86_arch_always_fancy_math_387
1478	= m_PENT \| m_PPRO \| m_AMD_MULTIPLE \| m_PENT4	1564	= m_PENT \| m_ATOM \| m_PPRO \| m_AMD_MULTIPLE \| m_PENT4
1479	\| m_NOCONA \| m_CORE2 \| m_GENERIC;	1565	\| m_NOCONA \| m_CORE2 \| m_GENERIC;
1480		1566
1481	static enum stringop_alg stringop_alg = no_stringop;	1567	static enum stringop_alg stringop_alg = no_stringop;
Lines 1958-1964 static const struct ptt processor_target_table[PROCESSOR_max] = Link Here
1958	{&core2_cost, 16, 10, 16, 10, 16},	2044	{&core2_cost, 16, 10, 16, 10, 16},
1959	{&generic32_cost, 16, 7, 16, 7, 16},	2045	{&generic32_cost, 16, 7, 16, 7, 16},
1960	{&generic64_cost, 16, 10, 16, 10, 16},	2046	{&generic64_cost, 16, 10, 16, 10, 16},
1961	{&amdfam10_cost, 32, 24, 32, 7, 32}	2047	{&amdfam10_cost, 32, 24, 32, 7, 32},
		2048	{&atom_cost, 16, 7, 16, 7, 16}
1962	};	2049	};
1963		2050
1964	static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =	2051	static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
Lines 1976-1981 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = Link Here
1976	"prescott",	2063	"prescott",
1977	"nocona",	2064	"nocona",
1978	"core2",	2065	"core2",
		2066	"atom",
1979	"geode",	2067	"geode",
1980	"k6",	2068	"k6",
1981	"k6-2",	2069	"k6-2",
Lines 2534-2539 override_options (bool main_args_p) Link Here
2534	{"core2", PROCESSOR_CORE2, CPU_CORE2,	2622	{"core2", PROCESSOR_CORE2, CPU_CORE2,
2535	PTA_64BIT \| PTA_MMX \| PTA_SSE \| PTA_SSE2 \| PTA_SSE3	2623	PTA_64BIT \| PTA_MMX \| PTA_SSE \| PTA_SSE2 \| PTA_SSE3
2536	\| PTA_SSSE3 \| PTA_CX16},	2624	\| PTA_SSSE3 \| PTA_CX16},
		2625	{"atom", PROCESSOR_ATOM, CPU_ATOM,
		2626	PTA_64BIT \| PTA_MMX \| PTA_SSE \| PTA_SSE2 \| PTA_SSE3
		2627	\| PTA_SSSE3 \| PTA_CX16},
2537	{"geode", PROCESSOR_GEODE, CPU_GEODE,	2628	{"geode", PROCESSOR_GEODE, CPU_GEODE,
2538	PTA_MMX \| PTA_3DNOW \| PTA_3DNOW_A \|PTA_PREFETCH_SSE},	2629	PTA_MMX \| PTA_3DNOW \| PTA_3DNOW_A \|PTA_PREFETCH_SSE},
2539	{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},	2630	{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
Lines 19026-19031 ix86_issue_rate (void) Link Here
19026	switch (ix86_tune)	19117	switch (ix86_tune)
19027	{	19118	{
19028	case PROCESSOR_PENTIUM:	19119	case PROCESSOR_PENTIUM:
		19120	case PROCESSOR_ATOM:
19029	case PROCESSOR_K6:	19121	case PROCESSOR_K6:
19030	return 2;	19122	return 2;
19031		19123
Lines 19226-19231 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) Link Here
19226	case PROCESSOR_ATHLON:	19318	case PROCESSOR_ATHLON:
19227	case PROCESSOR_K8:	19319	case PROCESSOR_K8:
19228	case PROCESSOR_AMDFAM10:	19320	case PROCESSOR_AMDFAM10:
		19321	case PROCESSOR_ATOM:
19229	case PROCESSOR_GENERIC32:	19322	case PROCESSOR_GENERIC32:
19230	case PROCESSOR_GENERIC64:	19323	case PROCESSOR_GENERIC64:
19231	memory = get_attr_memory (insn);	19324	memory = get_attr_memory (insn);

Lines 231-236 extern const struct processor_costs ix86_size_cost; Link Here

(-)a/gcc/config/i386/i386.h (+5 lines)
231	#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)	231	#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
232	#define TARGET_GENERIC (TARGET_GENERIC32 \|\| TARGET_GENERIC64)	232	#define TARGET_GENERIC (TARGET_GENERIC32 \|\| TARGET_GENERIC64)
233	#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)	233	#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
		234	#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
234		235
235	/* Feature tests against the various tunings. */	236	/* Feature tests against the various tunings. */
236	enum ix86_tune_indices {	237	enum ix86_tune_indices {
Lines 295-300 enum ix86_tune_indices { Link Here
295	X86_TUNE_USE_VECTOR_FP_CONVERTS,	296	X86_TUNE_USE_VECTOR_FP_CONVERTS,
296	X86_TUNE_USE_VECTOR_CONVERTS,	297	X86_TUNE_USE_VECTOR_CONVERTS,
297	X86_TUNE_FUSE_CMP_AND_BRANCH,	298	X86_TUNE_FUSE_CMP_AND_BRANCH,
		299	X86_TUNE_OPT_AGU,
298		300
299	X86_TUNE_LAST	301	X86_TUNE_LAST
300	};	302	};
Lines 382-387 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; Link Here
382	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]	384	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
383	#define TARGET_FUSE_CMP_AND_BRANCH \	385	#define TARGET_FUSE_CMP_AND_BRANCH \
384	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]	386	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
		387	#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
385		388
386	/* Feature tests against the various architecture variations. */	389	/* Feature tests against the various architecture variations. */
387	enum ix86_arch_indices {	390	enum ix86_arch_indices {
Lines 567-572 enum target_cpu_default Link Here
567	TARGET_CPU_DEFAULT_prescott,	570	TARGET_CPU_DEFAULT_prescott,
568	TARGET_CPU_DEFAULT_nocona,	571	TARGET_CPU_DEFAULT_nocona,
569	TARGET_CPU_DEFAULT_core2,	572	TARGET_CPU_DEFAULT_core2,
		573	TARGET_CPU_DEFAULT_atom,
570		574
571	TARGET_CPU_DEFAULT_geode,	575	TARGET_CPU_DEFAULT_geode,
572	TARGET_CPU_DEFAULT_k6,	576	TARGET_CPU_DEFAULT_k6,
Lines 2272-2277 enum processor_type Link Here
2272	PROCESSOR_GENERIC32,	2276	PROCESSOR_GENERIC32,
2273	PROCESSOR_GENERIC64,	2277	PROCESSOR_GENERIC64,
2274	PROCESSOR_AMDFAM10,	2278	PROCESSOR_AMDFAM10,
		2279	PROCESSOR_ATOM,
2275	PROCESSOR_max	2280	PROCESSOR_max
2276	};	2281	};
2277		2282

Lines 338-343 Link Here

(-)a/gcc/config/i386/sse.md (-9 / +47 lines)
338	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"	338	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
339	"vmovup<avxmodesuffixf2c>\t{%1, %0\|%0, %1}"	339	"vmovup<avxmodesuffixf2c>\t{%1, %0\|%0, %1}"
340	[(set_attr "type" "ssemov")	340	[(set_attr "type" "ssemov")
		341	(set_attr "movu" "1")
341	(set_attr "prefix" "vex")	342	(set_attr "prefix" "vex")
342	(set_attr "mode" "<MODE>")])	343	(set_attr "mode" "<MODE>")])
343		344
Lines 363-368 Link Here
363	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"	364	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
364	"movup<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	365	"movup<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
365	[(set_attr "type" "ssemov")	366	[(set_attr "type" "ssemov")
		367	(set_attr "movu" "1")
366	(set_attr "mode" "<MODE>")])	368	(set_attr "mode" "<MODE>")])
367		369
368	(define_insn "avx_movdqu<avxmodesuffix>"	370	(define_insn "avx_movdqu<avxmodesuffix>"
Lines 373-378 Link Here
373	"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"	375	"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
374	"vmovdqu\t{%1, %0\|%0, %1}"	376	"vmovdqu\t{%1, %0\|%0, %1}"
375	[(set_attr "type" "ssemov")	377	[(set_attr "type" "ssemov")
		378	(set_attr "movu" "1")
376	(set_attr "prefix" "vex")	379	(set_attr "prefix" "vex")
377	(set_attr "mode" "<avxvecmode>")])	380	(set_attr "mode" "<avxvecmode>")])
378		381
Lines 383-388 Link Here
383	"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"	386	"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
384	"movdqu\t{%1, %0\|%0, %1}"	387	"movdqu\t{%1, %0\|%0, %1}"
385	[(set_attr "type" "ssemov")	388	[(set_attr "type" "ssemov")
		389	(set_attr "movu" "1")
386	(set_attr "prefix_data16" "1")	390	(set_attr "prefix_data16" "1")
387	(set_attr "mode" "TI")])	391	(set_attr "mode" "TI")])
388		392
Lines 424-430 Link Here
424	UNSPEC_MOVNT))]	428	UNSPEC_MOVNT))]
425	"TARGET_SSE2"	429	"TARGET_SSE2"
426	"movntdq\t{%1, %0\|%0, %1}"	430	"movntdq\t{%1, %0\|%0, %1}"
427	[(set_attr "type" "ssecvt")	431	[(set_attr "type" "ssemov")
428	(set_attr "prefix_data16" "1")	432	(set_attr "prefix_data16" "1")
429	(set_attr "mode" "TI")])	433	(set_attr "mode" "TI")])
430		434
Lines 434-440 Link Here
434	UNSPEC_MOVNT))]	438	UNSPEC_MOVNT))]
435	"TARGET_SSE2"	439	"TARGET_SSE2"
436	"movnti\t{%1, %0\|%0, %1}"	440	"movnti\t{%1, %0\|%0, %1}"
437	[(set_attr "type" "ssecvt")	441	[(set_attr "type" "ssemov")
438	(set_attr "mode" "V2DF")])	442	(set_attr "mode" "V2DF")])
439		443
440	(define_insn "avx_lddqu<avxmodesuffix>"	444	(define_insn "avx_lddqu<avxmodesuffix>"
Lines 445-450 Link Here
445	"TARGET_AVX"	449	"TARGET_AVX"
446	"vlddqu\t{%1, %0\|%0, %1}"	450	"vlddqu\t{%1, %0\|%0, %1}"
447	[(set_attr "type" "ssecvt")	451	[(set_attr "type" "ssecvt")
		452	(set_attr "movu" "1")
448	(set_attr "prefix" "vex")	453	(set_attr "prefix" "vex")
449	(set_attr "mode" "<avxvecmode>")])	454	(set_attr "mode" "<avxvecmode>")])
450		455
Lines 454-460 Link Here
454	UNSPEC_LDDQU))]	459	UNSPEC_LDDQU))]
455	"TARGET_SSE3"	460	"TARGET_SSE3"
456	"lddqu\t{%1, %0\|%0, %1}"	461	"lddqu\t{%1, %0\|%0, %1}"
457	[(set_attr "type" "ssecvt")	462	[(set_attr "type" "ssemov")
		463	(set_attr "movu" "1")
458	(set_attr "prefix_rep" "1")	464	(set_attr "prefix_rep" "1")
459	(set_attr "mode" "TI")])	465	(set_attr "mode" "TI")])
460		466
Lines 761-766 Link Here
761	"TARGET_SSE"	767	"TARGET_SSE"
762	"%vrcpps\t{%1, %0\|%0, %1}"	768	"%vrcpps\t{%1, %0\|%0, %1}"
763	[(set_attr "type" "sse")	769	[(set_attr "type" "sse")
		770	(set_attr "atom_sse_attr" "rcp")
764	(set_attr "prefix" "maybe_vex")	771	(set_attr "prefix" "maybe_vex")
765	(set_attr "mode" "V4SF")])	772	(set_attr "mode" "V4SF")])
766		773
Lines 787-792 Link Here
787	"TARGET_SSE"	794	"TARGET_SSE"
788	"rcpss\t{%1, %0\|%0, %1}"	795	"rcpss\t{%1, %0\|%0, %1}"
789	[(set_attr "type" "sse")	796	[(set_attr "type" "sse")
		797	(set_attr "atom_sse_attr" "rcp")
790	(set_attr "mode" "SF")])	798	(set_attr "mode" "SF")])
791		799
792	(define_expand "sqrtv8sf2"	800	(define_expand "sqrtv8sf2"
Lines 832-837 Link Here
832	"TARGET_SSE"	840	"TARGET_SSE"
833	"%vsqrtps\t{%1, %0\|%0, %1}"	841	"%vsqrtps\t{%1, %0\|%0, %1}"
834	[(set_attr "type" "sse")	842	[(set_attr "type" "sse")
		843	(set_attr "atom_sse_attr" "sqrt")
835	(set_attr "prefix" "maybe_vex")	844	(set_attr "prefix" "maybe_vex")
836	(set_attr "mode" "V4SF")])	845	(set_attr "mode" "V4SF")])
837		846
Lines 876-881 Link Here
876	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	885	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
877	"sqrts<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	886	"sqrts<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
878	[(set_attr "type" "sse")	887	[(set_attr "type" "sse")
		888	(set_attr "atom_sse_attr" "sqrt")
879	(set_attr "mode" "<ssescalarmode>")])	889	(set_attr "mode" "<ssescalarmode>")])
880		890
881	(define_expand "rsqrtv8sf2"	891	(define_expand "rsqrtv8sf2"
Lines 1039-1045 Link Here
1039	(const_int 1)))]	1049	(const_int 1)))]
1040	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	1050	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1041	"<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0\|%0, %2}"	1051	"<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0\|%0, %2}"
1042	[(set_attr "type" "sse")	1052	[(set_attr "type" "sseadd")
1043	(set_attr "mode" "<ssescalarmode>")])	1053	(set_attr "mode" "<ssescalarmode>")])
1044		1054
1045	;; These versions of the min/max patterns implement exactly the operations	1055	;; These versions of the min/max patterns implement exactly the operations
Lines 1175-1180 Link Here
1175	"TARGET_SSE3"	1185	"TARGET_SSE3"
1176	"addsubpd\t{%2, %0\|%0, %2}"	1186	"addsubpd\t{%2, %0\|%0, %2}"
1177	[(set_attr "type" "sseadd")	1187	[(set_attr "type" "sseadd")
		1188	(set_attr "atom_unit" "complex")
1178	(set_attr "mode" "V2DF")])	1189	(set_attr "mode" "V2DF")])
1179		1190
1180	(define_insn "avx_h<plusminus_insn>v4df3"	1191	(define_insn "avx_h<plusminus_insn>v4df3"
Lines 1298-1303 Link Here
1298	"TARGET_SSE3"	1309	"TARGET_SSE3"
1299	"h<plusminus_mnemonic>ps\t{%2, %0\|%0, %2}"	1310	"h<plusminus_mnemonic>ps\t{%2, %0\|%0, %2}"
1300	[(set_attr "type" "sseadd")	1311	[(set_attr "type" "sseadd")
		1312	(set_attr "atom_unit" "complex")
1301	(set_attr "prefix_rep" "1")	1313	(set_attr "prefix_rep" "1")
1302	(set_attr "mode" "V4SF")])	1314	(set_attr "mode" "V4SF")])
1303		1315
Lines 5066-5071 Link Here
5066	"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"	5078	"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5067	"pmaddwd\t{%2, %0\|%0, %2}"	5079	"pmaddwd\t{%2, %0\|%0, %2}"
5068	[(set_attr "type" "sseiadd")	5080	[(set_attr "type" "sseiadd")
		5081	(set_attr "atom_unit" "simul")
5069	(set_attr "prefix_data16" "1")	5082	(set_attr "prefix_data16" "1")
5070	(set_attr "mode" "TI")])	5083	(set_attr "mode" "TI")])
5071		5084
Lines 7025-7030 Link Here
7025	movq\t{%H1, %0\|%0, %H1}	7038	movq\t{%H1, %0\|%0, %H1}
7026	mov{q}\t{%H1, %0\|%0, %H1}"	7039	mov{q}\t{%H1, %0\|%0, %H1}"
7027	[(set_attr "type" "ssemov,sseishft,ssemov,imov")	7040	[(set_attr "type" "ssemov,sseishft,ssemov,imov")
		7041	(set_attr "atom_unit" ",sishuf,,*")
7028	(set_attr "memory" ",none,,*")	7042	(set_attr "memory" ",none,,*")
7029	(set_attr "mode" "V2SF,TI,TI,DI")])	7043	(set_attr "mode" "V2SF,TI,TI,DI")])
7030		7044
Lines 7057-7062 Link Here
7057	psrldq\t{$8, %0\|%0, 8}	7071	psrldq\t{$8, %0\|%0, 8}
7058	movq\t{%H1, %0\|%0, %H1}"	7072	movq\t{%H1, %0\|%0, %H1}"
7059	[(set_attr "type" "ssemov,sseishft,ssemov")	7073	[(set_attr "type" "ssemov,sseishft,ssemov")
		7074	(set_attr "atom_unit" ",sishuf,")
7060	(set_attr "memory" ",none,")	7075	(set_attr "memory" ",none,")
7061	(set_attr "mode" "V2SF,TI,TI")])	7076	(set_attr "mode" "V2SF,TI,TI")])
7062		7077
Lines 7614-7619 Link Here
7614	"TARGET_SSE2"	7629	"TARGET_SSE2"
7615	"psadbw\t{%2, %0\|%0, %2}"	7630	"psadbw\t{%2, %0\|%0, %2}"
7616	[(set_attr "type" "sseiadd")	7631	[(set_attr "type" "sseiadd")
		7632	(set_attr "atom_unit" "simul")
7617	(set_attr "prefix_data16" "1")	7633	(set_attr "prefix_data16" "1")
7618	(set_attr "mode" "TI")])	7634	(set_attr "mode" "TI")])
7619		7635
Lines 7635-7641 Link Here
7635	UNSPEC_MOVMSK))]	7651	UNSPEC_MOVMSK))]
7636	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	7652	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
7637	"%vmovmskp<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	7653	"%vmovmskp<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
7638	[(set_attr "type" "ssecvt")	7654	[(set_attr "type" "ssemov")
7639	(set_attr "prefix" "maybe_vex")	7655	(set_attr "prefix" "maybe_vex")
7640	(set_attr "mode" "<MODE>")])	7656	(set_attr "mode" "<MODE>")])
7641		7657
Lines 7645-7651 Link Here
7645	UNSPEC_MOVMSK))]	7661	UNSPEC_MOVMSK))]
7646	"TARGET_SSE2"	7662	"TARGET_SSE2"
7647	"%vpmovmskb\t{%1, %0\|%0, %1}"	7663	"%vpmovmskb\t{%1, %0\|%0, %1}"
7648	[(set_attr "type" "ssecvt")	7664	[(set_attr "type" "ssemov")
7649	(set_attr "prefix_data16" "1")	7665	(set_attr "prefix_data16" "1")
7650	(set_attr "prefix" "maybe_vex")	7666	(set_attr "prefix" "maybe_vex")
7651	(set_attr "mode" "SI")])	7667	(set_attr "mode" "SI")])
Lines 7668-7674 Link Here
7668	"TARGET_SSE2 && !TARGET_64BIT"	7684	"TARGET_SSE2 && !TARGET_64BIT"
7669	;; @@@ check ordering of operands in intel/nonintel syntax	7685	;; @@@ check ordering of operands in intel/nonintel syntax
7670	"%vmaskmovdqu\t{%2, %1\|%1, %2}"	7686	"%vmaskmovdqu\t{%2, %1\|%1, %2}"
7671	[(set_attr "type" "ssecvt")	7687	[(set_attr "type" "ssemov")
7672	(set_attr "prefix_data16" "1")	7688	(set_attr "prefix_data16" "1")
7673	(set_attr "prefix" "maybe_vex")	7689	(set_attr "prefix" "maybe_vex")
7674	(set_attr "mode" "TI")])	7690	(set_attr "mode" "TI")])
Lines 7682-7688 Link Here
7682	"TARGET_SSE2 && TARGET_64BIT"	7698	"TARGET_SSE2 && TARGET_64BIT"
7683	;; @@@ check ordering of operands in intel/nonintel syntax	7699	;; @@@ check ordering of operands in intel/nonintel syntax
7684	"%vmaskmovdqu\t{%2, %1\|%1, %2}"	7700	"%vmaskmovdqu\t{%2, %1\|%1, %2}"
7685	[(set_attr "type" "ssecvt")	7701	[(set_attr "type" "ssemov")
7686	(set_attr "prefix_data16" "1")	7702	(set_attr "prefix_data16" "1")
7687	(set_attr "prefix" "maybe_vex")	7703	(set_attr "prefix" "maybe_vex")
7688	(set_attr "mode" "TI")])	7704	(set_attr "mode" "TI")])
Lines 7693-7698 Link Here
7693	"TARGET_SSE"	7709	"TARGET_SSE"
7694	"%vldmxcsr\t%0"	7710	"%vldmxcsr\t%0"
7695	[(set_attr "type" "sse")	7711	[(set_attr "type" "sse")
		7712	(set_attr "atom_sse_attr" "mxcsr")
7696	(set_attr "prefix" "maybe_vex")	7713	(set_attr "prefix" "maybe_vex")
7697	(set_attr "memory" "load")])	7714	(set_attr "memory" "load")])
7698		7715
Lines 7702-7707 Link Here
7702	"TARGET_SSE"	7719	"TARGET_SSE"
7703	"%vstmxcsr\t%0"	7720	"%vstmxcsr\t%0"
7704	[(set_attr "type" "sse")	7721	[(set_attr "type" "sse")
		7722	(set_attr "atom_sse_attr" "mxcsr")
7705	(set_attr "prefix" "maybe_vex")	7723	(set_attr "prefix" "maybe_vex")
7706	(set_attr "memory" "store")])	7724	(set_attr "memory" "store")])
7707		7725
Lines 7720-7725 Link Here
7720	"TARGET_SSE \|\| TARGET_3DNOW_A"	7738	"TARGET_SSE \|\| TARGET_3DNOW_A"
7721	"sfence"	7739	"sfence"
7722	[(set_attr "type" "sse")	7740	[(set_attr "type" "sse")
		7741	(set_attr "atom_sse_attr" "fence")
7723	(set_attr "memory" "unknown")])	7742	(set_attr "memory" "unknown")])
7724		7743
7725	(define_insn "sse2_clflush"	7744	(define_insn "sse2_clflush"
Lines 7728-7733 Link Here
7728	"TARGET_SSE2"	7747	"TARGET_SSE2"
7729	"clflush\t%a0"	7748	"clflush\t%a0"
7730	[(set_attr "type" "sse")	7749	[(set_attr "type" "sse")
		7750	(set_attr "atom_sse_attr" "fence")
7731	(set_attr "memory" "unknown")])	7751	(set_attr "memory" "unknown")])
7732		7752
7733	(define_expand "sse2_mfence"	7753	(define_expand "sse2_mfence"
Lines 7745-7750 Link Here
7745	"TARGET_64BIT \|\| TARGET_SSE2"	7765	"TARGET_64BIT \|\| TARGET_SSE2"
7746	"mfence"	7766	"mfence"
7747	[(set_attr "type" "sse")	7767	[(set_attr "type" "sse")
		7768	(set_attr "atom_sse_attr" "fence")
7748	(set_attr "memory" "unknown")])	7769	(set_attr "memory" "unknown")])
7749		7770
7750	(define_expand "sse2_lfence"	7771	(define_expand "sse2_lfence"
Lines 7762-7767 Link Here
7762	"TARGET_SSE2"	7783	"TARGET_SSE2"
7763	"lfence"	7784	"lfence"
7764	[(set_attr "type" "sse")	7785	[(set_attr "type" "sse")
		7786	(set_attr "atom_sse_attr" "lfence")
7765	(set_attr "memory" "unknown")])	7787	(set_attr "memory" "unknown")])
7766		7788
7767	(define_insn "sse3_mwait"	7789	(define_insn "sse3_mwait"
Lines 7885-7890 Link Here
7885	"TARGET_SSSE3"	7907	"TARGET_SSSE3"
7886	"phaddw\t{%2, %0\|%0, %2}"	7908	"phaddw\t{%2, %0\|%0, %2}"
7887	[(set_attr "type" "sseiadd")	7909	[(set_attr "type" "sseiadd")
		7910	(set_attr "atom_unit" "complex")
7888	(set_attr "prefix_data16" "1")	7911	(set_attr "prefix_data16" "1")
7889	(set_attr "prefix_extra" "1")	7912	(set_attr "prefix_extra" "1")
7890	(set_attr "mode" "TI")])	7913	(set_attr "mode" "TI")])
Lines 7913-7918 Link Here
7913	"TARGET_SSSE3"	7936	"TARGET_SSSE3"
7914	"phaddw\t{%2, %0\|%0, %2}"	7937	"phaddw\t{%2, %0\|%0, %2}"
7915	[(set_attr "type" "sseiadd")	7938	[(set_attr "type" "sseiadd")
		7939	(set_attr "atom_unit" "complex")
7916	(set_attr "prefix_extra" "1")	7940	(set_attr "prefix_extra" "1")
7917	(set_attr "mode" "DI")])	7941	(set_attr "mode" "DI")])
7918		7942
Lines 7967-7972 Link Here
7967	"TARGET_SSSE3"	7991	"TARGET_SSSE3"
7968	"phaddd\t{%2, %0\|%0, %2}"	7992	"phaddd\t{%2, %0\|%0, %2}"
7969	[(set_attr "type" "sseiadd")	7993	[(set_attr "type" "sseiadd")
		7994	(set_attr "atom_unit" "complex")
7970	(set_attr "prefix_data16" "1")	7995	(set_attr "prefix_data16" "1")
7971	(set_attr "prefix_extra" "1")	7996	(set_attr "prefix_extra" "1")
7972	(set_attr "mode" "TI")])	7997	(set_attr "mode" "TI")])
Lines 7987-7992 Link Here
7987	"TARGET_SSSE3"	8012	"TARGET_SSSE3"
7988	"phaddd\t{%2, %0\|%0, %2}"	8013	"phaddd\t{%2, %0\|%0, %2}"
7989	[(set_attr "type" "sseiadd")	8014	[(set_attr "type" "sseiadd")
		8015	(set_attr "atom_unit" "complex")
7990	(set_attr "prefix_extra" "1")	8016	(set_attr "prefix_extra" "1")
7991	(set_attr "mode" "DI")])	8017	(set_attr "mode" "DI")])
7992		8018
Lines 8073-8078 Link Here
8073	"TARGET_SSSE3"	8099	"TARGET_SSSE3"
8074	"phaddsw\t{%2, %0\|%0, %2}"	8100	"phaddsw\t{%2, %0\|%0, %2}"
8075	[(set_attr "type" "sseiadd")	8101	[(set_attr "type" "sseiadd")
		8102	(set_attr "atom_unit" "complex")
8076	(set_attr "prefix_data16" "1")	8103	(set_attr "prefix_data16" "1")
8077	(set_attr "prefix_extra" "1")	8104	(set_attr "prefix_extra" "1")
8078	(set_attr "mode" "TI")])	8105	(set_attr "mode" "TI")])
Lines 8101-8106 Link Here
8101	"TARGET_SSSE3"	8128	"TARGET_SSSE3"
8102	"phaddsw\t{%2, %0\|%0, %2}"	8129	"phaddsw\t{%2, %0\|%0, %2}"
8103	[(set_attr "type" "sseiadd")	8130	[(set_attr "type" "sseiadd")
		8131	(set_attr "atom_unit" "complex")
8104	(set_attr "prefix_extra" "1")	8132	(set_attr "prefix_extra" "1")
8105	(set_attr "mode" "DI")])	8133	(set_attr "mode" "DI")])
8106		8134
Lines 8187-8192 Link Here
8187	"TARGET_SSSE3"	8215	"TARGET_SSSE3"
8188	"phsubw\t{%2, %0\|%0, %2}"	8216	"phsubw\t{%2, %0\|%0, %2}"
8189	[(set_attr "type" "sseiadd")	8217	[(set_attr "type" "sseiadd")
		8218	(set_attr "atom_unit" "complex")
8190	(set_attr "prefix_data16" "1")	8219	(set_attr "prefix_data16" "1")
8191	(set_attr "prefix_extra" "1")	8220	(set_attr "prefix_extra" "1")
8192	(set_attr "mode" "TI")])	8221	(set_attr "mode" "TI")])
Lines 8215-8220 Link Here
8215	"TARGET_SSSE3"	8244	"TARGET_SSSE3"
8216	"phsubw\t{%2, %0\|%0, %2}"	8245	"phsubw\t{%2, %0\|%0, %2}"
8217	[(set_attr "type" "sseiadd")	8246	[(set_attr "type" "sseiadd")
		8247	(set_attr "atom_unit" "complex")
8218	(set_attr "prefix_extra" "1")	8248	(set_attr "prefix_extra" "1")
8219	(set_attr "mode" "DI")])	8249	(set_attr "mode" "DI")])
8220		8250
Lines 8269-8274 Link Here
8269	"TARGET_SSSE3"	8299	"TARGET_SSSE3"
8270	"phsubd\t{%2, %0\|%0, %2}"	8300	"phsubd\t{%2, %0\|%0, %2}"
8271	[(set_attr "type" "sseiadd")	8301	[(set_attr "type" "sseiadd")
		8302	(set_attr "atom_unit" "complex")
8272	(set_attr "prefix_data16" "1")	8303	(set_attr "prefix_data16" "1")
8273	(set_attr "prefix_extra" "1")	8304	(set_attr "prefix_extra" "1")
8274	(set_attr "mode" "TI")])	8305	(set_attr "mode" "TI")])
Lines 8289-8294 Link Here
8289	"TARGET_SSSE3"	8320	"TARGET_SSSE3"
8290	"phsubd\t{%2, %0\|%0, %2}"	8321	"phsubd\t{%2, %0\|%0, %2}"
8291	[(set_attr "type" "sseiadd")	8322	[(set_attr "type" "sseiadd")
		8323	(set_attr "atom_unit" "complex")
8292	(set_attr "prefix_extra" "1")	8324	(set_attr "prefix_extra" "1")
8293	(set_attr "mode" "DI")])	8325	(set_attr "mode" "DI")])
8294		8326
Lines 8375-8380 Link Here
8375	"TARGET_SSSE3"	8407	"TARGET_SSSE3"
8376	"phsubsw\t{%2, %0\|%0, %2}"	8408	"phsubsw\t{%2, %0\|%0, %2}"
8377	[(set_attr "type" "sseiadd")	8409	[(set_attr "type" "sseiadd")
		8410	(set_attr "atom_unit" "complex")
8378	(set_attr "prefix_data16" "1")	8411	(set_attr "prefix_data16" "1")
8379	(set_attr "prefix_extra" "1")	8412	(set_attr "prefix_extra" "1")
8380	(set_attr "mode" "TI")])	8413	(set_attr "mode" "TI")])
Lines 8403-8408 Link Here
8403	"TARGET_SSSE3"	8436	"TARGET_SSSE3"
8404	"phsubsw\t{%2, %0\|%0, %2}"	8437	"phsubsw\t{%2, %0\|%0, %2}"
8405	[(set_attr "type" "sseiadd")	8438	[(set_attr "type" "sseiadd")
		8439	(set_attr "atom_unit" "complex")
8406	(set_attr "prefix_extra" "1")	8440	(set_attr "prefix_extra" "1")
8407	(set_attr "mode" "DI")])	8441	(set_attr "mode" "DI")])
8408		8442
Lines 8509-8514 Link Here
8509	"TARGET_SSSE3"	8543	"TARGET_SSSE3"
8510	"pmaddubsw\t{%2, %0\|%0, %2}"	8544	"pmaddubsw\t{%2, %0\|%0, %2}"
8511	[(set_attr "type" "sseiadd")	8545	[(set_attr "type" "sseiadd")
		8546	(set_attr "atom_unit" "simul")
8512	(set_attr "prefix_data16" "1")	8547	(set_attr "prefix_data16" "1")
8513	(set_attr "prefix_extra" "1")	8548	(set_attr "prefix_extra" "1")
8514	(set_attr "mode" "TI")])	8549	(set_attr "mode" "TI")])
Lines 8547-8552 Link Here
8547	"TARGET_SSSE3"	8582	"TARGET_SSSE3"
8548	"pmaddubsw\t{%2, %0\|%0, %2}"	8583	"pmaddubsw\t{%2, %0\|%0, %2}"
8549	[(set_attr "type" "sseiadd")	8584	[(set_attr "type" "sseiadd")
		8585	(set_attr "atom_unit" "simul")
8550	(set_attr "prefix_extra" "1")	8586	(set_attr "prefix_extra" "1")
8551	(set_attr "mode" "DI")])	8587	(set_attr "mode" "DI")])
8552		8588
Lines 8754-8759 Link Here
8754	return "palignr\t{%3, %2, %0\|%0, %2, %3}";	8790	return "palignr\t{%3, %2, %0\|%0, %2, %3}";
8755	}	8791	}
8756	[(set_attr "type" "sseishft")	8792	[(set_attr "type" "sseishft")
		8793	(set_attr "atom_unit" "sishuf")
8757	(set_attr "prefix_data16" "1")	8794	(set_attr "prefix_data16" "1")
8758	(set_attr "prefix_extra" "1")	8795	(set_attr "prefix_extra" "1")
8759	(set_attr "mode" "TI")])	8796	(set_attr "mode" "TI")])
Lines 8770-8775 Link Here
8770	return "palignr\t{%3, %2, %0\|%0, %2, %3}";	8807	return "palignr\t{%3, %2, %0\|%0, %2, %3}";
8771	}	8808	}
8772	[(set_attr "type" "sseishft")	8809	[(set_attr "type" "sseishft")
		8810	(set_attr "atom_unit" "sishuf")
8773	(set_attr "prefix_extra" "1")	8811	(set_attr "prefix_extra" "1")
8774	(set_attr "mode" "DI")])	8812	(set_attr "mode" "DI")])
8775		8813
Lines 8956-8962 Link Here
8956	UNSPEC_MOVNTDQA))]	8994	UNSPEC_MOVNTDQA))]
8957	"TARGET_SSE4_1"	8995	"TARGET_SSE4_1"
8958	"%vmovntdqa\t{%1, %0\|%0, %1}"	8996	"%vmovntdqa\t{%1, %0\|%0, %1}"
8959	[(set_attr "type" "ssecvt")	8997	[(set_attr "type" "ssemov")
8960	(set_attr "prefix_extra" "1")	8998	(set_attr "prefix_extra" "1")
8961	(set_attr "prefix" "maybe_vex")	8999	(set_attr "prefix" "maybe_vex")
8962	(set_attr "mode" "TI")])	9000	(set_attr "mode" "TI")])