Attachment #185113 for bug #262603

Lines 7505-7510 Link Here

(-)gcc/doc/md.texi (+5 lines)
7505	recognize complicated bypasses, e.g.@: when the consumer is only an address	7505	recognize complicated bypasses, e.g.@: when the consumer is only an address
7506	of insn @samp{store} (not a stored value).	7506	of insn @samp{store} (not a stored value).
7507		7507
		7508	If there are more one bypass with the same output and input insns, the
		7509	chosen bypass is the first bypass with a guard in description whose
		7510	guard function returns nonzero. If there is no such bypass, then
		7511	bypass without the guard function is chosen.
		7512
7508	@findex exclusion_set	7513	@findex exclusion_set
7509	@findex presence_set	7514	@findex presence_set
7510	@findex final_presence_set	7515	@findex final_presence_set




    }
  return 0;
}

static int
reg_mentioned_by_mem_p_1 (const_rtx reg, const_rtx in,
			  bool *mem_p)
{
  const char *fmt;
  int i;
  enum rtx_code code;

  if (in == 0)
    return 0;

  if (reg == in)
    return 1;

  if (GET_CODE (in) == LABEL_REF)
    return reg == XEXP (in, 0);

  code = GET_CODE (in);

  switch (code)
    {
      /* Compare registers by number.  */
    case REG:
      return REG_P (reg) && REGNO (in) == REGNO (reg);

      /* These codes have no constituent expressions
	 and are unique.  */
    case SCRATCH:
    case CC0:
    case PC:
      return 0;

    case CONST_INT:
    case CONST_VECTOR:
    case CONST_DOUBLE:
    case CONST_FIXED:
      /* These are kept unique for a given value.  */
      return 0;

    default:
      break;
    }

  if (GET_CODE (reg) == code && rtx_equal_p (reg, in))
    return 1;

  fmt = GET_RTX_FORMAT (code);

  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
    {
      if (fmt[i] == 'E')
	{
	  int j;
	  for (j = XVECLEN (in, i) - 1; j >= 0; j--)
	    if (reg_mentioned_by_mem_p_1 (reg, XVECEXP (in, i, j), mem_p))
              {
                if (code == MEM)
                  *mem_p = true;

	        return 1;
              }
	}
      else if (fmt[i] == 'e'
	       && reg_mentioned_by_mem_p_1 (reg, XEXP (in, i), mem_p))
	{
	  if (code == MEM)
	    *mem_p = true;

	  return 1;
	}
    }
  return 0;
}

/* Similar to the function reg_mentioned_p, return true only when
   register REG appears in a MEM container of RTX IN.  */

bool
reg_mentioned_by_mem_p (const_rtx reg, const_rtx in)
{
  bool mem = false;

  reg_mentioned_by_mem_p_1 (reg, in, &mem);
  return mem;
}

/* Return true if dest regsiter in set_insn is used in use_insn as 
   address calculation.
   For example, returns true if 
     set_insn: reg_a = reg_b
     use_insn: reg_c = (reg_a) # reg_a used in addr calculation
   False if
     set_insn: reg_a = reg_b
     use_insn: (reg_c) = reg_a # reg_a is used, by not as addr.  */

bool
reg_dep_by_addr_p (const_rtx set_insn, const_rtx use_insn)
{
  rtx pattern = PATTERN (set_insn);
  rtx set_dest = NULL;

  switch (GET_CODE (pattern))
    {
      case SET:
        set_dest = SET_DEST (pattern);
        break;
      case PARALLEL:
        {
          rtx pattern2 = XVECEXP (PATTERN (set_insn), 0,0);
  	  if (GET_CODE (pattern2) == SET)
  	    set_dest = SET_DEST (pattern2);
          break;
        }
      default:
        set_dest = NULL;
    }

  /* True if destination of set is reg and used as address.  */
  return set_dest && REG_P (set_dest) 
         && reg_mentioned_by_mem_p (set_dest, use_insn);
}


/* Return 1 if in between BEG and END, exclusive of BEG and END, there is
   no CODE_LABEL insn.  */




/* Pipeline hazard description translator.
   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
   Free Software Foundation, Inc.

   Written by Vladimir Makarov <vmakarov@redhat.com>


/* References:

   1. The finite state automaton based pipeline hazard recognizer and
      instruction scheduler in GCC.  V. Makarov.  Proceedings of GCC
      summit, 2003.

   2. Detecting pipeline structural hazards quickly. T. Proebsting,
      C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on
      Principles of Programming Languages, pages 280--286, 1994.

      This article is a good start point to understand usage of finite
      state automata for pipeline hazard recognizers.  But I'd
      recommend the 1st and 3rd article for more deep understanding.

   3. Efficient Instruction Scheduling Using Finite State Automata:
      V. Bala and N. Rubin, Proceedings of MICRO-28.  This is the best
      article about usage of finite state automata for pipeline hazard
      recognizers.

   The current implementation is described in the 1st article and it
   is different from the 3rd article in the following:

   1. New operator `|' (alternative) is permitted in functional unit
      reservation which can be treated deterministically and

     insn.  */
  int insn_num;
  /* The following field value is list of bypasses in which given insn
     is output insn.  Bypasses with the same input insn stay one after
     another in the list in the same order as their occurrences in the
     description but the bypass without a guard stays always the last
     in a row of bypasses with the same input insn.  */
  struct bypass_decl *bypass_list;

  /* The following fields are defined by automaton generator.  */

}


/* The function inserts BYPASS in the list of bypasses of the
   corresponding output insn.  The order of bypasses in the list is
   decribed in a comment for member `bypass_list' (see above).  If
   there is already the same bypass in the list the function reports
   this and does nothing.  */
static void
insert_bypass (struct bypass_decl *bypass)
{
  struct bypass_decl *curr, *last;
  struct insn_reserv_decl *out_insn_reserv = bypass->out_insn_reserv;
  struct insn_reserv_decl *in_insn_reserv = bypass->in_insn_reserv;
  
  for (curr = out_insn_reserv->bypass_list, last = NULL;
       curr != NULL;
       last = curr, curr = curr->next)
    if (curr->in_insn_reserv == in_insn_reserv)
      {
	if ((bypass->bypass_guard_name != NULL
	     && curr->bypass_guard_name != NULL
	     && ! strcmp (bypass->bypass_guard_name, curr->bypass_guard_name))
	    || bypass->bypass_guard_name == curr->bypass_guard_name)
	  {
	    if (bypass->bypass_guard_name == NULL)
	      {
		if (!w_flag)
		  error ("the same bypass `%s - %s' is already defined",
			 bypass->out_insn_name, bypass->in_insn_name);
		else
		  warning (0, "the same bypass `%s - %s' is already defined",
			   bypass->out_insn_name, bypass->in_insn_name);
	      }
	    else if (!w_flag)
	      error ("the same bypass `%s - %s' (guard %s) is already defined",
		     bypass->out_insn_name, bypass->in_insn_name,
		     bypass->bypass_guard_name);
	    else
	      warning
		(0, "the same bypass `%s - %s' (guard %s) is already defined",
		 bypass->out_insn_name, bypass->in_insn_name,
		 bypass->bypass_guard_name);
	    return;
	  }
	if (curr->bypass_guard_name == NULL)
	  break;
	if (curr->next == NULL || curr->next->in_insn_reserv != in_insn_reserv)
	  {
	    last = curr;
	    break;
	  }
	  
      }
  if (last == NULL)
    {
      bypass->next = out_insn_reserv->bypass_list;
      out_insn_reserv->bypass_list = bypass;
    }
  else
    {
      bypass->next = last->next;
      last->next = bypass;
    }
}

/* The function processes pipeline description declarations, checks

  decl_t decl_in_table;
  decl_t out_insn_reserv;
  decl_t in_insn_reserv;
  struct bypass_decl *bypass;
  int automaton_presence;
  int i;


		= DECL_INSN_RESERV (out_insn_reserv);
	      DECL_BYPASS (decl)->in_insn_reserv
		= DECL_INSN_RESERV (in_insn_reserv);
	      insert_bypass (DECL_BYPASS (decl));
		= find_bypass (DECL_INSN_RESERV (out_insn_reserv)->bypass_list,
			       DECL_BYPASS (decl)->in_insn_reserv);
	      if (bypass != NULL)
		{
		  if (DECL_BYPASS (decl)->latency == bypass->latency)
		    {
		      if (!w_flag)
			error
			  ("the same bypass `%s - %s' is already defined",
			   DECL_BYPASS (decl)->out_insn_name,
			   DECL_BYPASS (decl)->in_insn_name);
		      else
			warning
			  (0, "the same bypass `%s - %s' is already defined",
			   DECL_BYPASS (decl)->out_insn_name,
			   DECL_BYPASS (decl)->in_insn_name);
		    }
		  else
		    error ("bypass `%s - %s' is already defined",
			   DECL_BYPASS (decl)->out_insn_name,
			   DECL_BYPASS (decl)->in_insn_name);
		}
	      else
		{
		  DECL_BYPASS (decl)->next
		    = DECL_INSN_RESERV (out_insn_reserv)->bypass_list;
		  DECL_INSN_RESERV (out_insn_reserv)->bypass_list
		    = DECL_BYPASS (decl);
		}
	    }
	}
    }

			    (advance_cycle_insn_decl)->insn_num));
	    fprintf (output_file, "        case %d:\n",
		     bypass->in_insn_reserv->insn_num);
	    for (;;)
	      fprintf (output_file, "          return %d;\n",
		       bypass->latency);
	    else
	      {
		if (bypass->bypass_guard_name == NULL)
		  {
		    gcc_assert (bypass->next == NULL
				|| (bypass->in_insn_reserv
				    != bypass->next->in_insn_reserv));
		    fprintf (output_file, "          return %d;\n",
			     bypass->latency);
		  }
		else
		  {
		    fprintf (output_file,
			     "          if (%s (%s, %s))\n",
			     bypass->bypass_guard_name, INSN_PARAMETER_NAME,
			     INSN2_PARAMETER_NAME);
		    fprintf (output_file, "            return %d;\n",
			     bypass->latency);
		  }
		if (bypass->next == NULL
		    || bypass->in_insn_reserv != bypass->next->in_insn_reserv)
		  break;
		bypass = bypass->next;
	      }
	    if (bypass->bypass_guard_name != NULL)
	      fprintf (output_file, "          break;\n");
	  }
	fputs ("        }\n      break;\n", output_file);
      }

Lines 1088-1094 Link Here

(-)gcc/rtl.def (-1 / +5 lines)
1088	guard for the bypass. The function will get the two insns as	1088	guard for the bypass. The function will get the two insns as
1089	parameters. If the function returns zero the bypass will be	1089	parameters. If the function returns zero the bypass will be
1090	ignored for this case. Additional guard is necessary to recognize	1090	ignored for this case. Additional guard is necessary to recognize
1091	complicated bypasses, e.g. when consumer is load address. */	1091	complicated bypasses, e.g. when consumer is load address. If there
		1092	are more one bypass with the same output and input insns, the
		1093	chosen bypass is the first bypass with a guard in description whose
		1094	guard function returns nonzero. If there is no such bypass, then
		1095	bypass without the guard function is chosen. */
1092	DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)	1096	DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1093		1097
1094	/* (define_automaton string) describes names of automata generated and	1098	/* (define_automaton string) describes names of automata generated and




2009-02-05  Joey Ye  <joey.ye@intel.com>
	    Xuepeng Guo <xuepeng.guo@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	Atom pipeline model, tuning and insn selection.
	* rtlanal.c (reg_mentioned_by_mem_p_1): New function.
	(reg_mentioned_by_mem_p): New function.
	(reg_dep_by_addr_p): New function.

	* rtl.h (reg_mentioned_by_mem_p): Declare new function.
	(reg_dep_by_addr_p): Likewise.

	* config.gcc (atom): Add atom config options and target.

	* config/i386/i386.h (TARGET_ATOM): New target macro.
	(X86_TUNE_OPT_AGU): New tuning flag.
	(TARGET_OPT_AGU): New target option.
	(TARGET_CPU_DEFAULT_atom): New CPU default.
	(PROCESSOR_ATOM): New processor.

	* config/i386/i386-c.c (ix86_target_macros_internal): New case
	PROCESSOR_ATOM.
	(ix86_target_macros_internal): Likewise.

	* config/i386/i386-protos.h (ix86_lea_for_add_ok): Declare new
	function.
	(ix86_dep_by_shift_count): Likewise.
	(ix86_agi_dependent): Likewise.

	* config/i386/i386.c (atom_cost): New cost.
	(m_ATOM): New macro flag.
	(initial_ix86_tune_fe): Set m_ATOM.
	(x86_accumulate_outgoing_args): Likewise.
	(x86_arch_always_fancy_math_387): Likewise.
	(processor_target): Add Atom cost.
	(cpu_names): Add Atom cpu name.
	(override_options): Set Atom ISA.
	(LEA_SEARCH_THRESHOLD): New macro.
	(distance_non_agu_define): New function.
	(distance_agu_use): Likewise.
	(ix86_lea_for_add_ok): Likewise.
	(ix86_dep_by_shift_count): Likewise.
	(ix86_agi_dependent): Make it global.
	(ix86_issue_rate): New case PROCESSOR_ATOM.
	(ix86_adjust_cost): Likewise.

	* config/i386/i386.md (cpu): Add new value "atom".
	(atom.md): Include atom.md.
	(use_carry, movu): New attr.
	(adddi3_carry_rex64): Set attr "use_carry".
	(addqi3_carry): Likewise.
	(addhi3_carry): Likewise.
	(addsi3_carry): Likewise.
	(*addsi3_carry_zext): Likewise.
	(subdi3_carry_rex64): Likewise.
	(subqi3_carry): Likewise.
	(subhi3_carry): Likewise.
	(subsi3_carry): Likewise.
	(x86_movdicc_0_m1_rex64): Likewise.
	(*x86_movdicc_0_m1_se): Likewise.
	(x86_movsicc_0_m1): Likewise.
	(*x86_movsicc_0_m1_se): Likewise.
	(*adddi_1_rex64): Emit add insn as much as possible.
	(*addsi_1): Likewise.
	(return_internal): Set atom_unit.
	(return_internal_long): Likewise.
	(return_pop_internal): Likewise.
	(*rcpsf2_sse): Set atom_sse_attr attr.
	(*qrt<mode>2_sse): Likewise.
	(*prefetch_sse): Likewise.

	* config/i386/sse.md (cpu): Set attr "atom_sse_attr".
	(*prefetch_sse_rex): Likewise.
	(sse_rcpv4sf2): Likewise.
	(sse_vmrcpv4sf2): Likewise.
	(sse_sqrtv4sf2): Likewise.
	(<sse>_vmsqrt<mode>2): Likewise.
	(sse_ldmxcsr): Likewise.
	(sse_stmxcsr): Likewise.
	(*sse_sfence): Likewise.
	(sse2_clflush): Likewise.
	(*sse2_mfence): Likewise.
	(*sse2_lfence): Likewise.
	(avx_movup<avxmodesuffixf2c><avxmodesuffix>): Set attr "movu".
	(<sse>_movup<ssemodesuffixf2c>): Likewise.
	(avx_movdqu<avxmodesuffix>): Likewise.
	(avx_lddqu<avxmodesuffix>): Likewise.
	(sse2_movntv2di): Change attr "type" to "ssemov".
	(sse2_movntsi): Likewise.
	(rsqrtv8sf2): Change attr "type" to "sseadd".
	(sse3_addsubv2df3): Set attr "atom_unit".
	(sse3_h<plusminus_insn>v4sf3): Likewise.
	(*sse2_pmaddwd): Likewise.
	(*vec_extractv2di_1_rex64): Likewise.
	(*vec_extractv2di_1_avx): Likewise.
	(sse2_psadbw): Likewise.
	(ssse3_phaddwv8hi3): Likewise.
	(ssse3_phaddwv4hi3): Likewise.
	(ssse3_phadddv4si3): Likewise.
	(ssse3_phadddv2si3): Likewise.
	(ssse3_phaddswv8hi3): Likewise.
	(ssse3_phaddswv4hi3): Likewise.
	(ssse3_phsubwv8hi3): Likewise.
	(ssse3_phsubwv4hi3): Likewise.
	(ssse3_phsubdv4si3): Likewise.
	(ssse3_phsubdv2si3): Likewise.
	(ssse3_phsubswv8hi3): Likewise.
	(ssse3_phsubswv4hi3): Likewise.
	(ssse3_pmaddubsw128): Likewise.
	(sse3_pmaddubsw: Likewise.
	(ssse3_palignrti): Likewise.
	(ssse3_palignrdi): Likewise.

	* config/i386/atom.md: New.

2009-02-05  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (ix86_agi_dependent): Remove the third
	argument.  Swap the first 2 arguments.
	(ix86_adjust_cost): Updated.

2009-01-30  Vladimir Makarov  <vmakarov@redhat.com>

	* genautomata.c: Add a new year to the copyright.  Add a new
	reference.
	(struct insn_reserv_decl): Add comments for member bypass_list.
	(find_bypass): Remove.
	(insert_bypass): New.
	(process_decls): Use insert_bypass.
	(output_internal_insn_latency_func): Output all bypasses with the
	same input insn in one switch case.

	* rtl.def (define_bypass): Describe bypass choice.
	* doc/md.texi (define_bypass): Ditto.

Lines 1731-1736 Link Here

(-)gcc/rtl.h (+2 lines)
1731	extern bool offset_within_block_p (const_rtx, HOST_WIDE_INT);	1731	extern bool offset_within_block_p (const_rtx, HOST_WIDE_INT);
1732	extern void split_const (rtx, rtx , rtx );	1732	extern void split_const (rtx, rtx , rtx );
1733	extern int reg_mentioned_p (const_rtx, const_rtx);	1733	extern int reg_mentioned_p (const_rtx, const_rtx);
		1734	extern bool reg_mentioned_by_mem_p (const_rtx, const_rtx);
		1735	extern bool reg_dep_by_addr_p (const_rtx, const_rtx);
1734	extern int count_occurrences (const_rtx, const_rtx, int);	1736	extern int count_occurrences (const_rtx, const_rtx, int);
1735	extern int reg_referenced_p (const_rtx, const_rtx);	1737	extern int reg_referenced_p (const_rtx, const_rtx);
1736	extern int reg_used_between_p (const_rtx, const_rtx, const_rtx);	1738	extern int reg_used_between_p (const_rtx, const_rtx, const_rtx);




			tmake_file="${tmake_file} i386/t-linux64"
			need_64bit_hwint=yes
			case X"${with_cpu}" in
			Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
				;;
			X)
				if test x$with_cpu_64 = x; then

				;;
			*)
				echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
				echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
				exit 1
				;;
			esac

		# libgcc/configure.ac instead.
		need_64bit_hwint=yes
		case X"${with_cpu}" in
		Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
			;;
		X)
			if test x$with_cpu_64 = x; then

			;;
		*)
			echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
			echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
			exit 1
			;;
		esac

				esac
				# OK
				;;
			"" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | atom | generic)
				# OK
				;;
			*)




#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)

/* Feature tests against the various tunings.  */
enum ix86_tune_indices {

  X86_TUNE_USE_VECTOR_FP_CONVERTS,
  X86_TUNE_USE_VECTOR_CONVERTS,
  X86_TUNE_FUSE_CMP_AND_BRANCH,
  X86_TUNE_OPT_AGU,

  X86_TUNE_LAST
};

	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
#define TARGET_FUSE_CMP_AND_BRANCH \
	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]

/* Feature tests against the various architecture variations.  */
enum ix86_arch_indices {

  TARGET_CPU_DEFAULT_prescott,
  TARGET_CPU_DEFAULT_nocona,
  TARGET_CPU_DEFAULT_core2,
  TARGET_CPU_DEFAULT_atom,

  TARGET_CPU_DEFAULT_geode,
  TARGET_CPU_DEFAULT_k6,

  PROCESSOR_GENERIC32,
  PROCESSOR_GENERIC64,
  PROCESSOR_AMDFAM10,
  PROCESSOR_ATOM,
  PROCESSOR_max
};


Lines 297-303 Link Here

(-)gcc/config/i386/i386.md (-15 / +58 lines)
297		297
298		298
299	;; Processor type.	299	;; Processor type.
300	(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,	300	(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
301	generic64,amdfam10"	301	generic64,amdfam10"
302	(const (symbol_ref "ix86_schedule")))	302	(const (symbol_ref "ix86_schedule")))
303		303
Lines 593-598 Link Here
593	(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"	593	(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
594	(const_string "any"))	594	(const_string "any"))
595		595
		596	;; Define attribute to classify add/sub insns that consumes carry flag (CF)
		597	(define_attr "use_carry" "0,1" (const_string "0"))
		598
		599	;; Define attribute to indicate unaligned ssemov insns
		600	(define_attr "movu" "0,1" (const_string "0"))
		601
596	;; Describe a user's asm statement.	602	;; Describe a user's asm statement.
597	(define_asm_attributes	603	(define_asm_attributes
598	[(set_attr "length" "128")	604	[(set_attr "length" "128")
Lines 708-713 Link Here
708	(include "k6.md")	714	(include "k6.md")
709	(include "athlon.md")	715	(include "athlon.md")
710	(include "geode.md")	716	(include "geode.md")
		717	(include "atom.md")
711		718
712		719
713	;; Operand and operator predicates and constraints	720	;; Operand and operator predicates and constraints
Lines 5775-5780 Link Here
5775	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"	5782	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5776	"adc{q}\t{%2, %0\|%0, %2}"	5783	"adc{q}\t{%2, %0\|%0, %2}"
5777	[(set_attr "type" "alu")	5784	[(set_attr "type" "alu")
		5785	(set_attr "use_carry" "1")
5778	(set_attr "pent_pair" "pu")	5786	(set_attr "pent_pair" "pu")
5779	(set_attr "mode" "DI")])	5787	(set_attr "mode" "DI")])
5780		5788
Lines 5849-5854 Link Here
5849	"ix86_binary_operator_ok (PLUS, QImode, operands)"	5857	"ix86_binary_operator_ok (PLUS, QImode, operands)"
5850	"adc{b}\t{%2, %0\|%0, %2}"	5858	"adc{b}\t{%2, %0\|%0, %2}"
5851	[(set_attr "type" "alu")	5859	[(set_attr "type" "alu")
		5860	(set_attr "use_carry" "1")
5852	(set_attr "pent_pair" "pu")	5861	(set_attr "pent_pair" "pu")
5853	(set_attr "mode" "QI")])	5862	(set_attr "mode" "QI")])
5854		5863
Lines 5861-5866 Link Here
5861	"ix86_binary_operator_ok (PLUS, HImode, operands)"	5870	"ix86_binary_operator_ok (PLUS, HImode, operands)"
5862	"adc{w}\t{%2, %0\|%0, %2}"	5871	"adc{w}\t{%2, %0\|%0, %2}"
5863	[(set_attr "type" "alu")	5872	[(set_attr "type" "alu")
		5873	(set_attr "use_carry" "1")
5864	(set_attr "pent_pair" "pu")	5874	(set_attr "pent_pair" "pu")
5865	(set_attr "mode" "HI")])	5875	(set_attr "mode" "HI")])
5866		5876
Lines 5873-5878 Link Here
5873	"ix86_binary_operator_ok (PLUS, SImode, operands)"	5883	"ix86_binary_operator_ok (PLUS, SImode, operands)"
5874	"adc{l}\t{%2, %0\|%0, %2}"	5884	"adc{l}\t{%2, %0\|%0, %2}"
5875	[(set_attr "type" "alu")	5885	[(set_attr "type" "alu")
		5886	(set_attr "use_carry" "1")
5876	(set_attr "pent_pair" "pu")	5887	(set_attr "pent_pair" "pu")
5877	(set_attr "mode" "SI")])	5888	(set_attr "mode" "SI")])
5878		5889
Lines 5886-5891 Link Here
5886	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"	5897	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5887	"adc{l}\t{%2, %k0\|%k0, %2}"	5898	"adc{l}\t{%2, %k0\|%k0, %2}"
5888	[(set_attr "type" "alu")	5899	[(set_attr "type" "alu")
		5900	(set_attr "use_carry" "1")
5889	(set_attr "pent_pair" "pu")	5901	(set_attr "pent_pair" "pu")
5890	(set_attr "mode" "SI")])	5902	(set_attr "mode" "SI")])
5891		5903
Lines 6115-6123 Link Here
6115	(set_attr "mode" "SI")])	6127	(set_attr "mode" "SI")])
6116		6128
6117	(define_insn "*adddi_1_rex64"	6129	(define_insn "*adddi_1_rex64"
6118	[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")	6130	[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
6119	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")	6131	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r")
6120	(match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))	6132	(match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le")))
6121	(clobber (reg:CC FLAGS_REG))]	6133	(clobber (reg:CC FLAGS_REG))]
6122	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"	6134	"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
6123	{	6135	{
Lines 6138-6143 Link Here
6138	}	6150	}
6139		6151
6140	default:	6152	default:
		6153	/* Use add as much as possible to replace lea for AGU optimization. */
		6154	if (which_alternative == 2 && TARGET_OPT_AGU)
		6155	return "add{q}\t{%1, %0\|%0, %1}";
		6156
6141	gcc_assert (rtx_equal_p (operands[0], operands[1]));	6157	gcc_assert (rtx_equal_p (operands[0], operands[1]));
6142		6158
6143	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.	6159	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Lines 6156-6163 Link Here
6156	}	6172	}
6157	}	6173	}
6158	[(set (attr "type")	6174	[(set (attr "type")
6159	(cond [(eq_attr "alternative" "2")	6175	(cond [(and (eq_attr "alternative" "2")
		6176	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
6160	(const_string "lea")	6177	(const_string "lea")
		6178	(eq_attr "alternative" "3")
		6179	(const_string "lea")
6161	; Current assemblers are broken and do not allow @GOTOFF in	6180	; Current assemblers are broken and do not allow @GOTOFF in
6162	; ought but a memory context.	6181	; ought but a memory context.
6163	(match_operand:DI 2 "pic_symbolic_operand" "")	6182	(match_operand:DI 2 "pic_symbolic_operand" "")
Lines 6174-6181 Link Here
6174	(plus:DI (match_operand:DI 1 "register_operand" "")	6193	(plus:DI (match_operand:DI 1 "register_operand" "")
6175	(match_operand:DI 2 "x86_64_nonmemory_operand" "")))	6194	(match_operand:DI 2 "x86_64_nonmemory_operand" "")))
6176	(clobber (reg:CC FLAGS_REG))]	6195	(clobber (reg:CC FLAGS_REG))]
6177	"TARGET_64BIT && reload_completed	6196	"TARGET_64BIT && reload_completed
6178	&& true_regnum (operands[0]) != true_regnum (operands[1])"	6197	&& ix86_lea_for_add_ok (PLUS, insn, operands)"
6179	[(set (match_dup 0)	6198	[(set (match_dup 0)
6180	(plus:DI (match_dup 1)	6199	(plus:DI (match_dup 1)
6181	(match_dup 2)))]	6200	(match_dup 2)))]
Lines 6379-6387 Link Here
6379		6398
6380		6399
6381	(define_insn "*addsi_1"	6400	(define_insn "*addsi_1"
6382	[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")	6401	[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r")
6383	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")	6402	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r")
6384	(match_operand:SI 2 "general_operand" "g,ri,li")))	6403	(match_operand:SI 2 "general_operand" "g,ri,0,li")))
6385	(clobber (reg:CC FLAGS_REG))]	6404	(clobber (reg:CC FLAGS_REG))]
6386	"ix86_binary_operator_ok (PLUS, SImode, operands)"	6405	"ix86_binary_operator_ok (PLUS, SImode, operands)"
6387	{	6406	{
Lines 6402-6407 Link Here
6402	}	6421	}
6403		6422
6404	default:	6423	default:
		6424	/* Use add as much as possible to replace lea for AGU optimization. */
		6425	if (which_alternative == 2 && TARGET_OPT_AGU)
		6426	return "add{l}\t{%1, %0\|%0, %1}";
		6427
6405	gcc_assert (rtx_equal_p (operands[0], operands[1]));	6428	gcc_assert (rtx_equal_p (operands[0], operands[1]));
6406		6429
6407	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.	6430	/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Lines 6418-6424 Link Here
6418	}	6441	}
6419	}	6442	}
6420	[(set (attr "type")	6443	[(set (attr "type")
6421	(cond [(eq_attr "alternative" "2")	6444	(cond [(and (eq_attr "alternative" "2")
		6445	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
		6446	(const_string "lea")
		6447	(eq_attr "alternative" "3")
6422	(const_string "lea")	6448	(const_string "lea")
6423	; Current assemblers are broken and do not allow @GOTOFF in	6449	; Current assemblers are broken and do not allow @GOTOFF in
6424	; ought but a memory context.	6450	; ought but a memory context.
Lines 6436-6443 Link Here
6436	(plus (match_operand 1 "register_operand" "")	6462	(plus (match_operand 1 "register_operand" "")
6437	(match_operand 2 "nonmemory_operand" "")))	6463	(match_operand 2 "nonmemory_operand" "")))
6438	(clobber (reg:CC FLAGS_REG))]	6464	(clobber (reg:CC FLAGS_REG))]
6439	"reload_completed	6465	"reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
6440	&& true_regnum (operands[0]) != true_regnum (operands[1])"
6441	[(const_int 0)]	6466	[(const_int 0)]
6442	{	6467	{
6443	rtx pat;	6468	rtx pat;
Lines 7538-7543 Link Here
7538	"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"	7563	"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
7539	"sbb{q}\t{%2, %0\|%0, %2}"	7564	"sbb{q}\t{%2, %0\|%0, %2}"
7540	[(set_attr "type" "alu")	7565	[(set_attr "type" "alu")
		7566	(set_attr "use_carry" "1")
7541	(set_attr "pent_pair" "pu")	7567	(set_attr "pent_pair" "pu")
7542	(set_attr "mode" "DI")])	7568	(set_attr "mode" "DI")])
7543		7569
Lines 7586-7591 Link Here
7586	"ix86_binary_operator_ok (MINUS, QImode, operands)"	7612	"ix86_binary_operator_ok (MINUS, QImode, operands)"
7587	"sbb{b}\t{%2, %0\|%0, %2}"	7613	"sbb{b}\t{%2, %0\|%0, %2}"
7588	[(set_attr "type" "alu")	7614	[(set_attr "type" "alu")
		7615	(set_attr "use_carry" "1")
7589	(set_attr "pent_pair" "pu")	7616	(set_attr "pent_pair" "pu")
7590	(set_attr "mode" "QI")])	7617	(set_attr "mode" "QI")])
7591		7618
Lines 7598-7603 Link Here
7598	"ix86_binary_operator_ok (MINUS, HImode, operands)"	7625	"ix86_binary_operator_ok (MINUS, HImode, operands)"
7599	"sbb{w}\t{%2, %0\|%0, %2}"	7626	"sbb{w}\t{%2, %0\|%0, %2}"
7600	[(set_attr "type" "alu")	7627	[(set_attr "type" "alu")
		7628	(set_attr "use_carry" "1")
7601	(set_attr "pent_pair" "pu")	7629	(set_attr "pent_pair" "pu")
7602	(set_attr "mode" "HI")])	7630	(set_attr "mode" "HI")])
7603		7631
Lines 7610-7615 Link Here
7610	"ix86_binary_operator_ok (MINUS, SImode, operands)"	7638	"ix86_binary_operator_ok (MINUS, SImode, operands)"
7611	"sbb{l}\t{%2, %0\|%0, %2}"	7639	"sbb{l}\t{%2, %0\|%0, %2}"
7612	[(set_attr "type" "alu")	7640	[(set_attr "type" "alu")
		7641	(set_attr "use_carry" "1")
7613	(set_attr "pent_pair" "pu")	7642	(set_attr "pent_pair" "pu")
7614	(set_attr "mode" "SI")])	7643	(set_attr "mode" "SI")])
7615		7644
Lines 15223-15228 Link Here
15223	"reload_completed"	15252	"reload_completed"
15224	"ret"	15253	"ret"
15225	[(set_attr "length" "1")	15254	[(set_attr "length" "1")
		15255	(set_attr "atom_unit" "jeu")
15226	(set_attr "length_immediate" "0")	15256	(set_attr "length_immediate" "0")
15227	(set_attr "modrm" "0")])	15257	(set_attr "modrm" "0")])
15228		15258
Lines 15235-15240 Link Here
15235	"reload_completed"	15265	"reload_completed"
15236	"rep\;ret"	15266	"rep\;ret"
15237	[(set_attr "length" "1")	15267	[(set_attr "length" "1")
		15268	(set_attr "atom_unit" "jeu")
15238	(set_attr "length_immediate" "0")	15269	(set_attr "length_immediate" "0")
15239	(set_attr "prefix_rep" "1")	15270	(set_attr "prefix_rep" "1")
15240	(set_attr "modrm" "0")])	15271	(set_attr "modrm" "0")])
Lines 15245-15250 Link Here
15245	"reload_completed"	15276	"reload_completed"
15246	"ret\t%0"	15277	"ret\t%0"
15247	[(set_attr "length" "3")	15278	[(set_attr "length" "3")
		15279	(set_attr "atom_unit" "jeu")
15248	(set_attr "length_immediate" "2")	15280	(set_attr "length_immediate" "2")
15249	(set_attr "modrm" "0")])	15281	(set_attr "modrm" "0")])
15250		15282
Lines 16366-16371 Link Here
16366	"TARGET_SSE_MATH"	16398	"TARGET_SSE_MATH"
16367	"%vrcpss\t{%1, %d0\|%d0, %1}"	16399	"%vrcpss\t{%1, %d0\|%d0, %1}"
16368	[(set_attr "type" "sse")	16400	[(set_attr "type" "sse")
		16401	(set_attr "atom_sse_attr" "rcp")
16369	(set_attr "prefix" "maybe_vex")	16402	(set_attr "prefix" "maybe_vex")
16370	(set_attr "mode" "SF")])	16403	(set_attr "mode" "SF")])
16371		16404
Lines 16717-16722 Link Here
16717	"TARGET_SSE_MATH"	16750	"TARGET_SSE_MATH"
16718	"%vrsqrtss\t{%1, %d0\|%d0, %1}"	16751	"%vrsqrtss\t{%1, %d0\|%d0, %1}"
16719	[(set_attr "type" "sse")	16752	[(set_attr "type" "sse")
		16753	(set_attr "atom_sse_attr" "rcp")
16720	(set_attr "prefix" "maybe_vex")	16754	(set_attr "prefix" "maybe_vex")
16721	(set_attr "mode" "SF")])	16755	(set_attr "mode" "SF")])
16722		16756
Lines 16737-16742 Link Here
16737	"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"	16771	"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16738	"%vsqrts<ssemodefsuffix>\t{%1, %d0\|%d0, %1}"	16772	"%vsqrts<ssemodefsuffix>\t{%1, %d0\|%d0, %1}"
16739	[(set_attr "type" "sse")	16773	[(set_attr "type" "sse")
		16774	(set_attr "atom_sse_attr" "sqrt")
16740	(set_attr "prefix" "maybe_vex")	16775	(set_attr "prefix" "maybe_vex")
16741	(set_attr "mode" "<MODE>")	16776	(set_attr "mode" "<MODE>")
16742	(set_attr "athlon_decode" "*")	16777	(set_attr "athlon_decode" "*")
Lines 19732-19737 Link Here
19732	; Since we don't have the proper number of operands for an alu insn,	19767	; Since we don't have the proper number of operands for an alu insn,
19733	; fill in all the blanks.	19768	; fill in all the blanks.
19734	[(set_attr "type" "alu")	19769	[(set_attr "type" "alu")
		19770	(set_attr "use_carry" "1")
19735	(set_attr "pent_pair" "pu")	19771	(set_attr "pent_pair" "pu")
19736	(set_attr "memory" "none")	19772	(set_attr "memory" "none")
19737	(set_attr "imm_disp" "false")	19773	(set_attr "imm_disp" "false")
Lines 19747-19752 Link Here
19747	""	19783	""
19748	"sbb{q}\t%0, %0"	19784	"sbb{q}\t%0, %0"
19749	[(set_attr "type" "alu")	19785	[(set_attr "type" "alu")
		19786	(set_attr "use_carry" "1")
19750	(set_attr "pent_pair" "pu")	19787	(set_attr "pent_pair" "pu")
19751	(set_attr "memory" "none")	19788	(set_attr "memory" "none")
19752	(set_attr "imm_disp" "false")	19789	(set_attr "imm_disp" "false")
Lines 19790-19795 Link Here
19790	; Since we don't have the proper number of operands for an alu insn,	19827	; Since we don't have the proper number of operands for an alu insn,
19791	; fill in all the blanks.	19828	; fill in all the blanks.
19792	[(set_attr "type" "alu")	19829	[(set_attr "type" "alu")
		19830	(set_attr "use_carry" "1")
19793	(set_attr "pent_pair" "pu")	19831	(set_attr "pent_pair" "pu")
19794	(set_attr "memory" "none")	19832	(set_attr "memory" "none")
19795	(set_attr "imm_disp" "false")	19833	(set_attr "imm_disp" "false")
Lines 19805-19810 Link Here
19805	""	19843	""
19806	"sbb{l}\t%0, %0"	19844	"sbb{l}\t%0, %0"
19807	[(set_attr "type" "alu")	19845	[(set_attr "type" "alu")
		19846	(set_attr "use_carry" "1")
19808	(set_attr "pent_pair" "pu")	19847	(set_attr "pent_pair" "pu")
19809	(set_attr "memory" "none")	19848	(set_attr "memory" "none")
19810	(set_attr "imm_disp" "false")	19849	(set_attr "imm_disp" "false")
Lines 20137-20143 Link Here
20137	}	20176	}
20138	}	20177	}
20139	[(set (attr "type")	20178	[(set (attr "type")
20140	(cond [(eq_attr "alternative" "0")	20179	(cond [(and (eq_attr "alternative" "0")
		20180	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
20141	(const_string "alu")	20181	(const_string "alu")
20142	(match_operand:SI 2 "const0_operand" "")	20182	(match_operand:SI 2 "const0_operand" "")
20143	(const_string "imov")	20183	(const_string "imov")
Lines 20180-20186 Link Here
20180	}	20220	}
20181	}	20221	}
20182	[(set (attr "type")	20222	[(set (attr "type")
20183	(cond [(eq_attr "alternative" "0")	20223	(cond [(and (eq_attr "alternative" "0")
		20224	(eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
20184	(const_string "alu")	20225	(const_string "alu")
20185	(match_operand:DI 2 "const0_operand" "")	20226	(match_operand:DI 2 "const0_operand" "")
20186	(const_string "imov")	20227	(const_string "imov")
Lines 21672-21677 Link Here
21672	return patterns[locality];	21713	return patterns[locality];
21673	}	21714	}
21674	[(set_attr "type" "sse")	21715	[(set_attr "type" "sse")
		21716	(set_attr "atom_sse_attr" "prefetch")
21675	(set_attr "memory" "none")])	21717	(set_attr "memory" "none")])
21676		21718
21677	(define_insn "*prefetch_sse_rex"	21719	(define_insn "*prefetch_sse_rex"
Lines 21690-21695 Link Here
21690	return patterns[locality];	21732	return patterns[locality];
21691	}	21733	}
21692	[(set_attr "type" "sse")	21734	[(set_attr "type" "sse")
		21735	(set_attr "atom_sse_attr" "prefetch")
21693	(set_attr "memory" "none")])	21736	(set_attr "memory" "none")])
21694		21737
21695	(define_insn "*prefetch_3dnow"	21738	(define_insn "*prefetch_3dnow"




;; Atom Scheduling
;; Copyright (C) 2009 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
;; Boston, MA 02110-1301, USA.  */
;;
;; Atom is an in-order core with two integer pipelines.


(define_attr "atom_unit" "sishuf,simul,jeu,complex,other" 
  (const_string "other"))

(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other"
  (const_string "other"))

(define_automaton "atom")

;;  Atom has two ports: port 0 and port 1 connecting to all execution units
(define_cpu_unit "atom-port-0,atom-port-1" "atom")

;;  EU: Execution Unit
;;  Atom EUs are connected by port 0 or port 1. 

(define_cpu_unit "atom-eu-0, atom-eu-1,
                  atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4"
                  "atom")

;; Some EUs have duplicated copied and can be accessed via either
;; port 0 or port 1
;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)")

;;; Some instructions is dual-pipe execution, need both ports
;;; Complex multi-op macro-instructoins need both ports and all EUs
(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)")
(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 + 
                                    atom-imul-1 + atom-imul-2 + atom-imul-3 +
                                    atom-imul-4)")

;;; Most of simple instructions have 1 cycle latency. Some of them
;;; issue in port 0, some in port 0 and some in either port.
(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)")
(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)")
(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)")

;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)")

;;; fmul insn can have 4 or 5 cycles latency
(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4")
(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3")

;;; fadd can has 5 cycles latency depends on instruction forms
(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5")

;;; imul insn has 5 cycles latency
(define_reservation "atom-imul-32" 
                    "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4, 
                     atom-port-0")
;;; imul instruction excludes other non-FP instructions.
(exclusion_set "atom-eu-0, atom-eu-1" 
               "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")

;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on 
;;; instruction forms
(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)")
(define_reservation "atom-dual-2c"
                    "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)")
(define_reservation "atom-dual-5c"
                    "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)")

;;; Complex macro-instruction has variants of latency, and uses both ports.
(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)")

(define_insn_reservation  "atom_other" 9
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "other")
            (eq_attr "atom_unit" "!jeu")))
  "atom-complex, atom-all-eu*8")

;; return has type "other" with atom_unit "jeu"
(define_insn_reservation  "atom_other_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "other")
            (eq_attr "atom_unit" "jeu")))
  "atom-dual-1c")

(define_insn_reservation  "atom_multi" 9
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "multi"))
  "atom-complex, atom-all-eu*8")

;; Normal alu insns without carry
(define_insn_reservation  "atom_alu" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "none")
                 (eq_attr "use_carry" "0"))))
  "atom-simple-either")

;; Normal alu insns without carry
(define_insn_reservation  "atom_alu_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "!none")
                 (eq_attr "use_carry" "0"))))
  "atom-simple-either")

;; Alu insn consuming CF, such as add/sbb
(define_insn_reservation  "atom_alu_carry" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "none")
                 (eq_attr "use_carry" "1"))))
  "atom-simple-either")

;; Alu insn consuming CF, such as add/sbb
(define_insn_reservation  "atom_alu_carry_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu")
            (and (eq_attr "memory" "!none")
                (eq_attr "use_carry" "1"))))
  "atom-simple-either")

(define_insn_reservation  "atom_alu1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu1")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_alu1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "alu1")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_negnot" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "negnot")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_negnot_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "negnot")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_imov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_imov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; 16<-16, 32<-32
(define_insn_reservation  "atom_imovx" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "none")
                 (ior (and (match_operand:HI 0 "register_operand")
                           (match_operand:HI 1 "general_operand"))
                      (and (match_operand:SI 0 "register_operand")
                           (match_operand:SI 1 "general_operand"))))))
  "atom-simple-either")

;; 16<-16, 32<-32, mem
(define_insn_reservation  "atom_imovx_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "!none")
                 (ior (and (match_operand:HI 0 "register_operand")
                           (match_operand:HI 1 "general_operand"))
                      (and (match_operand:SI 0 "register_operand")
                           (match_operand:SI 1 "general_operand"))))))
  "atom-simple-either")

;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
(define_insn_reservation  "atom_imovx_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "none")
                 (ior (match_operand:QI 0 "register_operand")
                      (ior (and (match_operand:SI 0 "register_operand")
                                (not (match_operand:SI 1 "general_operand")))
                           (match_operand:DI 0 "register_operand"))))))
  "atom-simple-0")

;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
(define_insn_reservation  "atom_imovx_2_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (eq_attr "memory" "!none")
                 (ior (match_operand:QI 0 "register_operand")
                      (ior (and (match_operand:SI 0 "register_operand")
                                (not (match_operand:SI 1 "general_operand")))
                           (match_operand:DI 0 "register_operand"))))))
  "atom-simple-0")

;; 16<-8
(define_insn_reservation  "atom_imovx_3" 3
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imovx")
            (and (match_operand:HI 0 "register_operand")
                 (match_operand:QI 1 "general_operand"))))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_lea" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "lea")
            (eq_attr "mode" "!HI")))
  "atom-simple-either")

;; lea 16bit address is complex insn
(define_insn_reservation  "atom_lea_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "lea")
            (eq_attr "mode" "HI")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_incdec" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "incdec")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_incdec_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "incdec")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; simple shift instruction use SHIFT eu, none memory
(define_insn_reservation  "atom_ishift" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
  "atom-simple-0")

;; simple shift instruction use SHIFT eu, memory
(define_insn_reservation  "atom_ishift_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
  "atom-simple-0")

;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles
(define_insn_reservation  "atom_ishift_3" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift")
            (eq_attr "prefix_0f" "1")))
  "atom-complex, atom-all-eu*6")

(define_insn_reservation  "atom_ishift1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_ishift1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ishift1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_rotate1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "rotate1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

(define_insn_reservation  "atom_imul" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
  "atom-imul-32")

(define_insn_reservation  "atom_imul_mem" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
  "atom-imul-32")

;; latency set to 10 as common 64x64 imul
(define_insn_reservation  "atom_imul_3" 10
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "imul")
            (eq_attr "mode" "!SI")))
  "atom-complex, atom-all-eu*9")

(define_insn_reservation  "atom_idiv" 65
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "idiv"))
  "atom-complex, atom-all-eu*32, nothing*32")

(define_insn_reservation  "atom_icmp" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmp")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_icmp_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmp")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_test" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "test")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_test_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "test")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_ibr" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ibr")
            (eq_attr "memory" "!load")))
  "atom-simple-1")

;; complex if jump target is from address
(define_insn_reservation  "atom_ibr_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ibr")
            (eq_attr "memory" "load")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_setcc" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "setcc")
            (eq_attr "memory" "!store")))
  "atom-simple-either")

;; 2 cycles complex if target is in memory
(define_insn_reservation  "atom_setcc_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "setcc")
            (eq_attr "memory" "store")))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_icmov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_icmov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "icmov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; UCODE if segreg, ignored
(define_insn_reservation  "atom_push" 2
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "push"))
  "atom-dual-2c")

;; pop r64 is 1 cycle. UCODE if segreg, ignored
(define_insn_reservation  "atom_pop" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "pop")
            (eq_attr "mode" "DI")))
  "atom-dual-1c")

;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
(define_insn_reservation  "atom_pop_2" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "pop")
            (eq_attr "mode" "!DI")))
  "atom-dual-2c")

;; UCODE if segreg, ignored
(define_insn_reservation  "atom_call" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "call"))
  "atom-dual-1c")

(define_insn_reservation  "atom_callv" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "callv"))
  "atom-dual-1c")

(define_insn_reservation  "atom_leave" 3
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "leave"))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_str" 3
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "str"))
  "atom-complex, atom-all-eu*2")

(define_insn_reservation  "atom_sselog" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog")
            (eq_attr "memory" "none")))
  "atom-simple-either")

(define_insn_reservation  "atom_sselog_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

(define_insn_reservation  "atom_sselog1" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog1")
            (eq_attr "memory" "none")))
  "atom-simple-0")

(define_insn_reservation  "atom_sselog1_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sselog1")
            (eq_attr "memory" "!none")))
  "atom-simple-0")

;; not pmad, not psad
(define_insn_reservation  "atom_sseiadd" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "!simul")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-simple-either")

;; pmad, psad and 64
(define_insn_reservation  "atom_sseiadd_2" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "simul" )
                      (eq_attr "mode" "DI")))))
  "atom-fmul-4c")

;; pmad, psad and 128
(define_insn_reservation  "atom_sseiadd_3" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (and (not (match_operand:V2DI 0 "register_operand"))
                 (and (eq_attr "atom_unit" "simul" )
                      (eq_attr "mode" "TI")))))
  "atom-fmul-5c")

;; if paddq(64 bit op), phadd/phsub
(define_insn_reservation  "atom_sseiadd_4" 6
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseiadd")
            (ior (match_operand:V2DI 0 "register_operand")
                 (eq_attr "atom_unit" "complex"))))
  "atom-complex, atom-all-eu*5")

;; if immediate op. 
(define_insn_reservation  "atom_sseishft" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (and (eq_attr "atom_unit" "!sishuf")
                 (match_operand 2 "immediate_operand"))))
  "atom-simple-either")

;; if palignr or psrldq
(define_insn_reservation  "atom_sseishft_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (and (eq_attr "atom_unit" "sishuf")
                 (match_operand 2 "immediate_operand"))))
  "atom-simple-0")

;; if reg/mem op
(define_insn_reservation  "atom_sseishft_3" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseishft")
            (not (match_operand 2 "immediate_operand"))))
  "atom-complex, atom-all-eu")

(define_insn_reservation  "atom_sseimul" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "sseimul"))
  "atom-simple-0")

;; rcpss or rsqrtss
(define_insn_reservation  "atom_sse" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
  "atom-fmul-4c")

;; movshdup, movsldup. Suggest to type sseishft
(define_insn_reservation  "atom_sse_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (eq_attr "atom_sse_attr" "movdup")))
  "atom-simple-0")

;; lfence
(define_insn_reservation  "atom_sse_3" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (eq_attr "atom_sse_attr" "lfence")))
  "atom-simple-either")

;; sfence,clflush,mfence, prefetch
(define_insn_reservation  "atom_sse_4" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (ior (eq_attr "atom_sse_attr" "fence")
                 (eq_attr "atom_sse_attr" "prefetch"))))
  "atom-simple-0")

;; rcpps, rsqrtss, sqrt, ldmxcsr
(define_insn_reservation  "atom_sse_5" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sse")
            (ior (ior (eq_attr "atom_sse_attr" "sqrt")
                      (eq_attr "atom_sse_attr" "mxcsr"))
                 (and (eq_attr "atom_sse_attr" "rcp")
                      (eq_attr "mode" "V4SF")))))
  "atom-complex, atom-all-eu*6")

;; xmm->xmm
(define_insn_reservation  "atom_ssemov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy"))))
  "atom-simple-either")

;; reg->xmm
(define_insn_reservation  "atom_ssemov_2" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r"))))
  "atom-simple-0")

;; xmm->reg
(define_insn_reservation  "atom_ssemov_3" 3
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy"))))
  "atom-eu-0-3-1")

;; mov mem
(define_insn_reservation  "atom_ssemov_4" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
  "atom-simple-0")

;; movu mem
(define_insn_reservation  "atom_ssemov_5" 2
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemov")
            (ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
  "atom-complex, atom-all-eu")

;; no memory simple
(define_insn_reservation  "atom_sseadd" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (and (eq_attr "memory" "none")
                 (and (eq_attr "mode" "!V2DF")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-fadd-5c")

;; memory simple
(define_insn_reservation  "atom_sseadd_mem" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (and (eq_attr "memory" "!none")
                 (and (eq_attr "mode" "!V2DF")
                      (eq_attr "atom_unit" "!complex")))))
  "atom-dual-5c")

;; maxps, minps, *pd, hadd, hsub
(define_insn_reservation  "atom_sseadd_3" 8
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseadd")
            (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
  "atom-complex, atom-all-eu*7")

;; Except dppd/dpps
(define_insn_reservation  "atom_ssemul" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemul")
            (eq_attr "mode" "!SF")))
  "atom-fmul-5c")

;; Except dppd/dpps, 4 cycle if mulss
(define_insn_reservation  "atom_ssemul_2" 4
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssemul")
            (eq_attr "mode" "SF")))
  "atom-fmul-4c")

(define_insn_reservation  "atom_ssecmp" 1
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssecmp"))
  "atom-simple-either")

(define_insn_reservation  "atom_ssecomi" 10
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssecomi"))
  "atom-complex, atom-all-eu*9")

;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
(define_insn_reservation  "atom_ssecvt" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (ior (and (match_operand:V2SI 0 "register_operand")
                      (match_operand:V4SF 1 "register_operand"))
                 (and (match_operand:V4SF 0 "register_operand")
                      (match_operand:V2SI 1 "register_operand")))))
  "atom-fadd-5c")

;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
(define_insn_reservation  "atom_ssecvt_2" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (ior (and (match_operand:V2SI 0 "register_operand")
                      (match_operand:V4SF 1 "memory_operand"))
                 (and (match_operand:V4SF 0 "register_operand")
                      (match_operand:V2SI 1 "memory_operand")))))
  "atom-dual-5c")

;; otherwise. 7 cycles average for cvtss2sd
(define_insn_reservation  "atom_ssecvt_3" 7
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "ssecvt")
            (not (ior (and (match_operand:V2SI 0 "register_operand")
                           (match_operand:V4SF 1 "nonimmediate_operand"))
                      (and (match_operand:V4SF 0 "register_operand")
                           (match_operand:V2SI 1 "nonimmediate_operand"))))))
  "atom-complex, atom-all-eu*6")

;; memory and cvtsi2sd
(define_insn_reservation  "atom_sseicvt" 5
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseicvt")
            (and (match_operand:V2DF 0 "register_operand")
                 (match_operand:SI 1 "memory_operand"))))
  "atom-dual-5c")

;; otherwise. 8 cycles average for cvtsd2si
(define_insn_reservation  "atom_sseicvt_2" 8
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "sseicvt")
            (not (and (match_operand:V2DF 0 "register_operand")
                      (match_operand:SI 1 "memory_operand")))))
  "atom-complex, atom-all-eu*7")

(define_insn_reservation  "atom_ssediv" 62
  (and (eq_attr "cpu" "atom")
       (eq_attr "type" "ssediv"))
  "atom-complex, atom-all-eu*12, nothing*49")

;; simple for fmov
(define_insn_reservation  "atom_fmov" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "fmov")
            (eq_attr "memory" "none")))
  "atom-simple-either")

;; simple for fmov
(define_insn_reservation  "atom_fmov_mem" 1
  (and (eq_attr "cpu" "atom")
       (and (eq_attr "type" "fmov")
            (eq_attr "memory" "!none")))
  "atom-simple-either")

;; Define bypass here

;; There will be no stall from lea to non-mem EX insns
(define_bypass 0 "atom_lea"
                 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec, atom_setcc, atom_icmov, atom_pop")

(define_bypass 0 "atom_lea"
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "!ix86_agi_dependent")

;; There will be 3 cycles stall from EX insns to AGAN insns LEA
(define_bypass 4 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
                  atom_rotate1, atom_setcc, atom_icmov, atom_pop,
                  atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "atom_lea")

;; There will be 3 cycles stall from EX insns to insns need addr calculation
(define_bypass 4 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
                  atom_rotate1, atom_setcc, atom_icmov, atom_pop,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imul_mem, atom_icmp_mem,
                  atom_test_mem, atom_icmov_mem, atom_sselog_mem,
                  atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem,
                  atom_ishift_mem, atom_ishift1_mem, 
                  atom_rotate_mem, atom_rotate1_mem"
                  "ix86_agi_dependent")

;; Stall from imul to lea is 8 cycles.
(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea")

;; Stall from imul to memory address is 8 cycles.
(define_bypass 9 "atom_imul, atom_imul_mem" 
                 "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
                  atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem,
                  atom_rotate1_mem, atom_imul_mem, atom_icmp_mem,
                  atom_test_mem, atom_icmov_mem, atom_sselog_mem,
                  atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem"
                  "ix86_agi_dependent")

;; There will be 0 cycle stall from cmp/test to jcc

;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry,
                  atom_alu1, atom_negnot, atom_incdec, atom_ishift,
                  atom_ishift1, atom_rotate, atom_rotate1"
                 "atom_icmov, atom_alu_carry")

;; lea to shift count stall is 2 cycles
(define_bypass 3 "atom_lea"
                 "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
                  atom_ishift_mem, atom_ishift1_mem, 
                  atom_rotate_mem, atom_rotate1_mem"
                 "ix86_dep_by_shift_count")

;; lea to shift source stall is 1 cycle
(define_bypass 2 "atom_lea"
                 "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1"
                 "!ix86_dep_by_shift_count")

;; non-lea to shift count stall is 1 cycle
(define_bypass 2 "atom_alu_carry,
                  atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
                  atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
                  atom_rotate1, atom_setcc, atom_icmov, atom_pop,
                  atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
                  atom_imovx_mem, atom_imovx_2_mem,
                  atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
                 "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
                  atom_ishift_mem, atom_ishift1_mem, 
                  atom_rotate_mem, atom_rotate1_mem"
                 "ix86_dep_by_shift_count")




   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<MODE>")])


   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "mode" "<MODE>")])

(define_insn "avx_movdqu<avxmodesuffix>"

  "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "vmovdqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<avxvecmode>")])


  "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "movdqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


		     UNSPEC_MOVNT))]
  "TARGET_SSE2"
  "movntdq\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


		   UNSPEC_MOVNT))]
  "TARGET_SSE2"
  "movnti\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "mode" "V2DF")])

(define_insn "avx_lddqu<avxmodesuffix>"

  "TARGET_AVX"
  "vlddqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssecvt")
   (set_attr "movu" "1")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<avxvecmode>")])


		      UNSPEC_LDDQU))]
  "TARGET_SSE3"
  "lddqu\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "movu" "1")
   (set_attr "prefix_rep" "1")
   (set_attr "mode" "TI")])


  "TARGET_SSE"
  "%vrcpps\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "rcp")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "V4SF")])


  "TARGET_SSE"
  "rcpss\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "rcp")
   (set_attr "mode" "SF")])

(define_expand "sqrtv8sf2"

  "TARGET_SSE"
  "%vsqrtps\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "sqrt")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "V4SF")])


  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "sqrt")
   (set_attr "mode" "<ssescalarmode>")])

(define_expand "rsqrtv8sf2"

	 (const_int 1)))]
  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "mode" "<ssescalarmode>")])

;; These versions of the min/max patterns implement exactly the operations

  "TARGET_SSE3"
  "addsubpd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "atom_unit" "complex")
   (set_attr "mode" "V2DF")])

(define_insn "avx_h<plusminus_insn>v4df3"

  "TARGET_SSE3"
  "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_rep" "1")
   (set_attr "mode" "V4SF")])


  "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
  "pmaddwd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


   movq\t{%H1, %0|%0, %H1}
   mov{q}\t{%H1, %0|%0, %H1}"
  [(set_attr "type" "ssemov,sseishft,ssemov,imov")
   (set_attr "atom_unit" "*,sishuf,*,*")
   (set_attr "memory" "*,none,*,*")
   (set_attr "mode" "V2SF,TI,TI,DI")])


   psrldq\t{$8, %0|%0, 8}
   movq\t{%H1, %0|%0, %H1}"
  [(set_attr "type" "ssemov,sseishft,ssemov")
   (set_attr "atom_unit" "*,sishuf,*")
   (set_attr "memory" "*,none,*")
   (set_attr "mode" "V2SF,TI,TI")])


  "TARGET_SSE2"
  "psadbw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "mode" "TI")])


	  UNSPEC_MOVMSK))]
  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
  "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "<MODE>")])


		   UNSPEC_MOVMSK))]
  "TARGET_SSE2"
  "%vpmovmskb\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "SI")])

  "TARGET_SSE2 && !TARGET_64BIT"
  ;; @@@ check ordering of operands in intel/nonintel syntax
  "%vmaskmovdqu\t{%2, %1|%1, %2}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

  "TARGET_SSE2 && TARGET_64BIT"
  ;; @@@ check ordering of operands in intel/nonintel syntax
  "%vmaskmovdqu\t{%2, %1|%1, %2}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

  "TARGET_SSE"
  "%vldmxcsr\t%0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "mxcsr")
   (set_attr "prefix" "maybe_vex")
   (set_attr "memory" "load")])


  "TARGET_SSE"
  "%vstmxcsr\t%0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "mxcsr")
   (set_attr "prefix" "maybe_vex")
   (set_attr "memory" "store")])


  "TARGET_SSE || TARGET_3DNOW_A"
  "sfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_insn "sse2_clflush"

  "TARGET_SSE2"
  "clflush\t%a0"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_expand "sse2_mfence"

  "TARGET_64BIT || TARGET_SSE2"
  "mfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "fence")
   (set_attr "memory" "unknown")])

(define_expand "sse2_lfence"

  "TARGET_SSE2"
  "lfence"
  [(set_attr "type" "sse")
   (set_attr "atom_sse_attr" "lfence")
   (set_attr "memory" "unknown")])

(define_insn "sse3_mwait"

  "TARGET_SSSE3"
  "phaddw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phaddd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phaddsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phaddsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubd\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "phsubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "phsubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  "TARGET_SSSE3"
  "pmaddubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  "TARGET_SSSE3"
  "pmaddubsw\t{%2, %0|%0, %2}"
  [(set_attr "type" "sseiadd")
   (set_attr "atom_unit" "simul")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


  return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
  [(set_attr "type" "sseishft")
   (set_attr "atom_unit" "sishuf")
   (set_attr "prefix_data16" "1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

  return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
  [(set_attr "type" "sseishft")
   (set_attr "atom_unit" "sishuf")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "DI")])


		     UNSPEC_MOVNTDQA))]
  "TARGET_SSE4_1"
  "%vmovntdqa\t{%1, %0|%0, %1}"
  [(set_attr "type" "ssemov")
   (set_attr "prefix_extra" "1")
   (set_attr "prefix" "maybe_vex")
   (set_attr "mode" "TI")])

Lines 119-124 Link Here

(-)gcc/config/i386/i386-c.c (+7 lines)
119	def_or_undef (parse_in, "__core2");	119	def_or_undef (parse_in, "__core2");
120	def_or_undef (parse_in, "__core2__");	120	def_or_undef (parse_in, "__core2__");
121	break;	121	break;
		122	case PROCESSOR_ATOM:
		123	def_or_undef (parse_in, "__atom");
		124	def_or_undef (parse_in, "__atom__");
		125	break;
122	/* use PROCESSOR_max to not set/unset the arch macro. */	126	/* use PROCESSOR_max to not set/unset the arch macro. */
123	case PROCESSOR_max:	127	case PROCESSOR_max:
124	break;	128	break;
Lines 187-192 Link Here
187	case PROCESSOR_CORE2:	191	case PROCESSOR_CORE2:
188	def_or_undef (parse_in, "__tune_core2__");	192	def_or_undef (parse_in, "__tune_core2__");
189	break;	193	break;
		194	case PROCESSOR_ATOM:
		195	def_or_undef (parse_in, "__tune_atom__");
		196	break;
190	case PROCESSOR_GENERIC32:	197	case PROCESSOR_GENERIC32:
191	case PROCESSOR_GENERIC64:	198	case PROCESSOR_GENERIC64:
192	break;	199	break;

Lines 85-90 Link Here

(-)gcc/config/i386/i386-protos.h (+3 lines)
85	extern void ix86_expand_binary_operator (enum rtx_code,	85	extern void ix86_expand_binary_operator (enum rtx_code,
86	enum machine_mode, rtx[]);	86	enum machine_mode, rtx[]);
87	extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);	87	extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
		88	extern bool ix86_lea_for_add_ok (enum rtx_code, rtx, rtx[]);
		89	extern bool ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn);
		90	extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn);
88	extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,	91	extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,
89	rtx[]);	92	rtx[]);
90	extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx);	93	extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx);




  1,                                    /* cond_not_taken_branch_cost.  */
};

static const
struct processor_costs atom_cost = {
  COSTS_N_INSNS (1),			/* cost of an add instruction */
  COSTS_N_INSNS (1) + 1,		/* cost of a lea instruction */
  COSTS_N_INSNS (1),			/* variable shift costs */
  COSTS_N_INSNS (1),			/* constant shift costs */
  {COSTS_N_INSNS (3),			/* cost of starting multiply for QI */
   COSTS_N_INSNS (4),			/*                               HI */
   COSTS_N_INSNS (3),			/*                               SI */
   COSTS_N_INSNS (4),			/*                               DI */
   COSTS_N_INSNS (2)},			/*                               other */
  0,					/* cost of multiply per each bit set */
  {COSTS_N_INSNS (18),			/* cost of a divide/mod for QI */
   COSTS_N_INSNS (26),			/*                          HI */
   COSTS_N_INSNS (42),			/*                          SI */
   COSTS_N_INSNS (74),			/*                          DI */
   COSTS_N_INSNS (74)},			/*                          other */
  COSTS_N_INSNS (1),			/* cost of movsx */
  COSTS_N_INSNS (1),			/* cost of movzx */
  8,					/* "large" insn */
  17,					/* MOVE_RATIO */
  2,					/* cost for loading QImode using movzbl */
  {4, 4, 4},				/* cost of loading integer registers
					   in QImode, HImode and SImode.
					   Relative to reg-reg move (2).  */
  {4, 4, 4},				/* cost of storing integer registers */
  4,					/* cost of reg,reg fld/fst */
  {12, 12, 12},				/* cost of loading fp registers
					   in SFmode, DFmode and XFmode */
  {6, 6, 8},				/* cost of storing fp registers
					   in SFmode, DFmode and XFmode */
  2,					/* cost of moving MMX register */
  {8, 8},				/* cost of loading MMX registers
					   in SImode and DImode */
  {8, 8},				/* cost of storing MMX registers
					   in SImode and DImode */
  2,					/* cost of moving SSE register */
  {8, 8, 8},				/* cost of loading SSE registers
					   in SImode, DImode and TImode */
  {8, 8, 8},				/* cost of storing SSE registers
					   in SImode, DImode and TImode */
  5,					/* MMX or SSE register to integer */
  32,					/* size of l1 cache.  */
  256,					/* size of l2 cache.  */
  64,					/* size of prefetch block */
  6,					/* number of parallel prefetches */
  3,					/* Branch cost */
  COSTS_N_INSNS (8),			/* cost of FADD and FSUB insns.  */
  COSTS_N_INSNS (8),			/* cost of FMUL instruction.  */
  COSTS_N_INSNS (20),			/* cost of FDIV instruction.  */
  COSTS_N_INSNS (8),			/* cost of FABS instruction.  */
  COSTS_N_INSNS (8),			/* cost of FCHS instruction.  */
  COSTS_N_INSNS (40),			/* cost of FSQRT instruction.  */
  {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
   {libcall, {{32, loop}, {64, rep_prefix_4_byte},
          {8192, rep_prefix_8_byte}, {-1, libcall}}}},
  {{libcall, {{8, loop}, {15, unrolled_loop},
          {2048, rep_prefix_4_byte}, {-1, libcall}}},
   {libcall, {{24, loop}, {32, unrolled_loop},
          {8192, rep_prefix_8_byte}, {-1, libcall}}}},
  1,                                    /* scalar_stmt_cost.  */
  1,                                    /* scalar load_cost.  */
  1,                                    /* scalar_store_cost.  */
  1,                                    /* vec_stmt_cost.  */
  1,                                    /* vec_to_scalar_cost.  */
  1,                                    /* scalar_to_vec_cost.  */
  1,                                    /* vec_align_load_cost.  */
  2,                                    /* vec_unalign_load_cost.  */
  1,                                    /* vec_store_cost.  */
  3,                                    /* cond_taken_branch_cost.  */
  1,                                    /* cond_not_taken_branch_cost.  */
};

/* Generic64 should produce code tuned for Nocona and K8.  */
static const
struct processor_costs generic64_cost = {

#define m_PENT4  (1<<PROCESSOR_PENTIUM4)
#define m_NOCONA  (1<<PROCESSOR_NOCONA)
#define m_CORE2  (1<<PROCESSOR_CORE2)
#define m_ATOM  (1<<PROCESSOR_ATOM)

#define m_GEODE  (1<<PROCESSOR_GEODE)
#define m_K6  (1<<PROCESSOR_K6)

  m_486 | m_PENT,

  /* X86_TUNE_UNROLL_STRLEN */
  m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_DEEP_BRANCH_PREDICTION */
  m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,

  /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
     on simulation result. But after P4 was made, no performance benefit

  ~m_386,

  /* X86_TUNE_USE_SAHF */
  m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
  | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
     partial dependencies.  */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
  | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,

  /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial

  m_386 | m_486 | m_K6_GEODE,

  /* X86_TUNE_USE_SIMODE_FIOP */
  ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),

  /* X86_TUNE_USE_MOV0 */
  m_K6,

  /* X86_TUNE_USE_CLTD */
  ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),

  /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx.  */
  m_PENT4,

  ~(m_PENT | m_PPRO),

  /* X86_TUNE_PROMOTE_QIMODE */
  m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
  | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,

  /* X86_TUNE_FAST_PREFIX */
  ~(m_PENT | m_486 | m_386),

  m_PPRO,

  /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop.  */
  m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_ADD_ESP_8 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
  | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SUB_ESP_4 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_SUB_ESP_8 */
  m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
  | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
     for DFmode copies */
  ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
    | m_GENERIC | m_GEODE),

  /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
  m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
     conflict here in between PPro/Pentium4 based chips that thread 128bit

     shows that disabling this option on P4 brings over 20% SPECfp regression,
     while enabling it on K8 brings roughly 2.4% regression that can be partly
     masked by careful scheduling of moves.  */
  m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
  | m_AMDFAM10,

  /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
  m_AMDFAM10,

  m_PPRO | m_PENT4 | m_NOCONA,

  /* X86_TUNE_MEMORY_MISMATCH_STALL */
  m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,

  /* X86_TUNE_PROLOGUE_USING_MOVE */
  m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,

  /* X86_TUNE_EPILOGUE_USING_MOVE */
  m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SHIFT1 */
  ~m_486,

  m_AMD_MULTIPLE,

  /* X86_TUNE_INTER_UNIT_MOVES */
  ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),

  /* X86_TUNE_INTER_UNIT_CONVERSIONS */
  ~(m_AMDFAM10),

  /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
     than 4 branch instructions in the 16 byte window.  */
  m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_SCHEDULE */
  m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
  | m_GENERIC,

  /* X86_TUNE_USE_BT */
  m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,

  /* X86_TUNE_USE_INCDEC */
  ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),

  /* X86_TUNE_PAD_RETURNS */
  m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,

  /* X86_TUNE_EXT_80387_CONSTANTS */
  m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
  | m_CORE2 | m_GENERIC,

  /* X86_TUNE_SHORTEN_X87_SSE */
  ~m_K8,

     with a subsequent conditional jump instruction into a single
     compare-and-branch uop.  */
  m_CORE2,

  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
  m_ATOM,
};

/* Feature tests against the various architecture variations.  */

};

static const unsigned int x86_accumulate_outgoing_args
  = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
    | m_GENERIC;

static const unsigned int x86_arch_always_fancy_math_387
  = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
    | m_NOCONA | m_CORE2 | m_GENERIC;

static enum stringop_alg stringop_alg = no_stringop;

  {&core2_cost, 16, 10, 16, 10, 16},
  {&generic32_cost, 16, 7, 16, 7, 16},
  {&generic64_cost, 16, 10, 16, 10, 16},
  {&amdfam10_cost, 32, 24, 32, 7, 32},
  {&atom_cost, 16, 7, 16, 7, 16}
};

static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =

  "prescott",
  "nocona",
  "core2",
  "atom",
  "geode",
  "k6",
  "k6-2",

      {"core2", PROCESSOR_CORE2, CPU_CORE2,
	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
	| PTA_SSSE3 | PTA_CX16},
      {"atom", PROCESSOR_ATOM, CPU_ATOM,
	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
	| PTA_SSSE3 | PTA_CX16},
      {"geode", PROCESSOR_GEODE, CPU_GEODE,
	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},

    emit_move_insn (operands[0], dst);
}

#define LEA_SEARCH_THRESHOLD 12

/* Reach non-agu definition of op1 and op2 in insn's basic block. 
   Search backward until 1. passed LEA_SEARCH_THRESHOLD instructions, 
   or 2. reach BB boundary, or reach agu definition. 
   Returns the distance between the non-agu definition point and insn.
   If no definition point, returns -1 
   TODO: Currently we have no way to distinguish if definition insn is a LEA. 
   We just assume all definitions are non-lea. */
static int
distance_non_agu_define (rtx op1, rtx op2, rtx insn)
{
  rtx reg_op1 = REG_P (op1) ? op1 : NULL;
  rtx reg_op2 = REG_P (op2) ? op2 : NULL;
  basic_block bb = BLOCK_FOR_INSN (insn);
  int distance = 0;

  if (insn != BB_HEAD (bb))
    {

      rtx prev = PREV_INSN (insn);
      while (prev && distance < LEA_SEARCH_THRESHOLD)
	{
	  if (INSN_P (prev))
	    {
	      distance++;
	      if ((reg_op1 && reg_set_p (reg_op1, prev))
		  || (reg_op2 && reg_set_p (reg_op2, prev)))
		return distance ;
	    }
	  if (prev == BB_HEAD (bb))
	    break;
	  prev = PREV_INSN (prev);
	}
    }
  
  if (distance < LEA_SEARCH_THRESHOLD)
    {
      edge e;
      edge_iterator ei;
      bool simple_loop = false;
  
      FOR_EACH_EDGE (e, ei, bb->preds)
	if (e->src == bb)
	  {
	    simple_loop = true;
	    break;
	  }
  
      if (simple_loop)
	{
	  rtx prev = BB_END (bb);
	  while (prev
		 && prev != insn
		 && distance < LEA_SEARCH_THRESHOLD)
	    {
	      if (INSN_P (prev))
		{
		  distance++;
		  if ((reg_op1 && reg_set_p (reg_op1, prev))
		      || (reg_op2 && reg_set_p (reg_op2, prev)))
		    return distance;
		}
	      prev = PREV_INSN (prev);
	    }
	}
    }

  return -1;
}

/* Return the distance between this insn and the next insn that uses 
   result of this insn as memory address. 
   Return -1 if not found such a use within LEA_SEARCH_THRESHOLD. */
static int
distance_agu_use (rtx op0, rtx insn)
{
  basic_block bb = BLOCK_FOR_INSN (insn);
  int distance = 0;

  if (insn != BB_END(bb))
    {
      rtx next = NEXT_INSN (insn);

      while (next && distance < LEA_SEARCH_THRESHOLD)
	{
	  if (INSN_P (next))
	    {
	      distance++;
	      if (reg_mentioned_by_mem_p (op0, next))
		return distance;
	      if (reg_set_p (op0, next))
		return -1;
	    }
	  if (next == BB_END (bb))
	    break;
	  next = NEXT_INSN (next);
	}
    }

  if (distance < LEA_SEARCH_THRESHOLD)
    {
      edge e;
      edge_iterator ei;
      bool simple_loop = false;
  
      FOR_EACH_EDGE (e, ei, bb->succs)
        if (e->dest == bb)
	  {
	    simple_loop = true;
	    break;
	  }
  
      if (simple_loop)
	{
	  rtx next = BB_HEAD (bb);
	  while (next && distance < LEA_SEARCH_THRESHOLD)
	    {
	      if (next == insn)
		break;
	      if (INSN_P (next))
		{
		  distance++;
		  if (reg_mentioned_by_mem_p (op0, next))
		    return distance;
		  if (reg_set_p (op0, next))
		    return -1;
		}
	      next = NEXT_INSN (next);
	    }
	}
    }  

  return -1;
}

/* Define this macro to tune LEA priority vs ADD, it take effect when
   there is a dilemma of choicing LEA or ADD
   Negative value: ADD is more preferred than LEA
   Zero: Netrual
   Positive value: LEA is more preferred than ADD*/
#define IX86_LEA_PRIORITY 2

/* Return true if it is ok to optimize an ADD operation to LEA
   operation to avoid flag register consumation.  For the processors
   like ATOM, if the destination register of LEA holds an actual
   address which will be used soon, LEA is better and otherwise ADD
   is better.  */

bool
ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
                     rtx insn,
                     rtx operands[])
{
  gcc_assert (REG_P (operands[0]));
  gcc_assert (operands[1] && operands[2]);

  if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
    {
      if (true_regnum (operands[0]) != true_regnum (operands[1]))
        return true;
      else
        return false;
    }

  /* If a = b + c, (a!=b && a!=c), must use lea form. */
  if (true_regnum (operands[0]) != true_regnum (operands[1])
      && true_regnum (operands[0]) != true_regnum (operands[2]))
    return true;
  else    
    {
      int dist_define, dist_use;
      dist_define = distance_non_agu_define (operands[1],
					     operands[2], insn);
      if (dist_define <= 0)
        return true;

      /* If this insn has both backward non-agu dependence and forward
         agu dependence, the one with short distance take effect. */
      dist_use = distance_agu_use (operands[0], insn);
      if (dist_use <= 0
	  || (dist_define + IX86_LEA_PRIORITY) < dist_use)
        return false;

      return true;
    }
}

/* Return true if destination reg of SET_INSN is shift count of
   USE_INSN.  */

bool
ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
{
  rtx set_pattern = PATTERN (set_insn);
  rtx set_dest;
  rtx shift_rtx;
  rtx use_pattern;

  /* Retrieve destination of set_insn */
  switch (GET_CODE (set_pattern))
    {
    case SET:
      set_dest = SET_DEST (set_pattern);
      break;
    case PARALLEL:
      set_pattern = XVECEXP (set_pattern, 0, 0);
      if (GET_CODE (set_pattern ) == SET)
	{
	  set_dest = SET_DEST (set_pattern);
	  break;
	}
    default:
      set_dest = NULL;
      break;
    }
  if (!set_dest || !REG_P (set_dest))
    return false;

  /* Retrieve shift count of use_insn */
  use_pattern = PATTERN (use_insn);
  switch (GET_CODE (use_pattern))
    {
    case SET:
      shift_rtx = XEXP (use_pattern, 1);
      break;
    case PARALLEL:
      set_pattern = XVECEXP (use_pattern, 0, 0);
      if (GET_CODE (set_pattern) == SET)
	{
	  shift_rtx = XEXP (set_pattern, 1);
	  break;
	}
    default:
      shift_rtx = NULL;
      break;
    }

  if (shift_rtx 
      && (GET_CODE (shift_rtx) == ASHIFT
	  || GET_CODE (shift_rtx) == LSHIFTRT
	  || GET_CODE (shift_rtx) == ASHIFTRT
	  || GET_CODE (shift_rtx) == ROTATE
	  || GET_CODE (shift_rtx) == ROTATERT))
    {
      rtx shift_count = XEXP (shift_rtx, 1);
      gcc_assert (shift_count);

      /* Return true if shift count is dest of set_insn */
      if (REG_P (shift_count)
	  && true_regnum (set_dest) == true_regnum (shift_count))
	return true;
    }

  return false;
}

/* Return TRUE or FALSE depending on whether the unary operator meets the
   appropriate constraints.  */


  switch (ix86_tune)
    {
    case PROCESSOR_PENTIUM:
    case PROCESSOR_ATOM:
    case PROCESSOR_K6:
      return 2;


  return 1;
}

/* Return true iff USE_INSN has a memory address with operands set by
   SET_INSN.  */

bool
ix86_agi_dependent (rtx set_insn, rtx use_insn)
{
  int i;
  extract_insn_cached (use_insn);
  for (i = recog_data.n_operands - 1; i >= 0; --i)
    if (MEM_P (recog_data.operand[i]))
      {
	rtx addr = XEXP (recog_data.operand[i], 0);
	return modified_in_p (addr, set_insn) != 0;
      }
  return false;

      gcc_assert (GET_CODE (addr) == SET);

      addr = SET_SRC (addr);
    }
  else
    {
      int i;
      extract_insn_cached (insn);
      for (i = recog_data.n_operands - 1; i >= 0; --i)
	if (MEM_P (recog_data.operand[i]))
	  {
	    addr = XEXP (recog_data.operand[i], 0);
	    goto found;
	  }
      return 0;
    found:;
    }

  return modified_in_p (addr, dep_insn);
}

static int

    {
    case PROCESSOR_PENTIUM:
      /* Address Generation Interlock adds a cycle of latency.  */
      if (insn_type == TYPE_LEA)
	{
	  rtx addr = PATTERN (insn);

	  if (GET_CODE (addr) == PARALLEL)
	    addr = XVECEXP (addr, 0, 0);

	  gcc_assert (GET_CODE (addr) == SET);

	  addr = SET_SRC (addr);
	  if (modified_in_p (addr, dep_insn))
	    cost += 1;
	}

      /* ??? Compares pair with jump/setcc.  */
      if (ix86_flags_dependent (insn, dep_insn, insn_type))
	cost = 0;

      /* Floating point stores require value to be ready one cycle earlier.  */
      if (insn_type == TYPE_FMOV
	  && get_attr_memory (insn) == MEMORY_STORE
	  && !ix86_agi_dependent (dep_insn, insn))
	cost += 1;
      break;


	 in parallel with previous instruction in case
	 previous instruction is not needed to compute the address.  */
      if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
	  && !ix86_agi_dependent (dep_insn, insn))
	{
	  /* Claim moves to take one cycle, as core can issue one load
	     at time and the next load can start cycle later.  */

	 in parallel with previous instruction in case
	 previous instruction is not needed to compute the address.  */
      if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
	  && !ix86_agi_dependent (dep_insn, insn))
	{
	  /* Claim moves to take one cycle, as core can issue one load
	     at time and the next load can start cycle later.  */

    case PROCESSOR_ATHLON:
    case PROCESSOR_K8:
    case PROCESSOR_AMDFAM10:
    case PROCESSOR_ATOM:
    case PROCESSOR_GENERIC32:
    case PROCESSOR_GENERIC64:
      memory = get_attr_memory (insn);

	 in parallel with previous instruction in case
	 previous instruction is not needed to compute the address.  */
      if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
	  && !ix86_agi_dependent (dep_insn, insn))
	{
	  enum attr_unit unit = get_attr_unit (insn);
	  int loadcost = 3;

Return to bug 262603

Lines 728-733 Link Here

(-)gcc/rtlanal.c (+123 lines)
728	}	728	}
729	return 0;	729	return 0;
730	}	730	}
		731
		732	static int
		733	reg_mentioned_by_mem_p_1 (const_rtx reg, const_rtx in,
		734	bool *mem_p)
		735	{
		736	const char *fmt;
		737	int i;
		738	enum rtx_code code;
		739
		740	if (in == 0)
		741	return 0;
		742
		743	if (reg == in)
		744	return 1;
		745
		746	if (GET_CODE (in) == LABEL_REF)
		747	return reg == XEXP (in, 0);
		748
		749	code = GET_CODE (in);
		750
		751	switch (code)
		752	{
		753	/* Compare registers by number. */
		754	case REG:
		755	return REG_P (reg) && REGNO (in) == REGNO (reg);
		756
		757	/* These codes have no constituent expressions
		758	and are unique. */
		759	case SCRATCH:
		760	case CC0:
		761	case PC:
		762	return 0;
		763
		764	case CONST_INT:
		765	case CONST_VECTOR:
		766	case CONST_DOUBLE:
		767	case CONST_FIXED:
		768	/* These are kept unique for a given value. */
		769	return 0;
		770
		771	default:
		772	break;
		773	}
		774
		775	if (GET_CODE (reg) == code && rtx_equal_p (reg, in))
		776	return 1;
		777
		778	fmt = GET_RTX_FORMAT (code);
		779
		780	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
		781	{
		782	if (fmt[i] == 'E')
		783	{
		784	int j;
		785	for (j = XVECLEN (in, i) - 1; j >= 0; j--)
		786	if (reg_mentioned_by_mem_p_1 (reg, XVECEXP (in, i, j), mem_p))
		787	{
		788	if (code == MEM)
		789	*mem_p = true;
		790
		791	return 1;
		792	}
		793	}
		794	else if (fmt[i] == 'e'
795	&& reg_mentioned_by_mem_p_1 (reg, XEXP (in, i), mem_p))
796	{
797	if (code == MEM)
798	*mem_p = true;
799
800	return 1;
801	}
802	}
803	return 0;
804	}
805
806	/* Similar to the function reg_mentioned_p, return true only when
807	register REG appears in a MEM container of RTX IN. */
808
809	bool
810	reg_mentioned_by_mem_p (const_rtx reg, const_rtx in)
811	{
812	bool mem = false;
813
814	reg_mentioned_by_mem_p_1 (reg, in, &mem);
815	return mem;
816	}
817
818	/* Return true if dest regsiter in set_insn is used in use_insn as
819	address calculation.
820	For example, returns true if
821	set_insn: reg_a = reg_b
822	use_insn: reg_c = (reg_a) # reg_a used in addr calculation
823	False if
824	set_insn: reg_a = reg_b
825	use_insn: (reg_c) = reg_a # reg_a is used, by not as addr. */
826
827	bool
828	reg_dep_by_addr_p (const_rtx set_insn, const_rtx use_insn)
829	{
830	rtx pattern = PATTERN (set_insn);
831	rtx set_dest = NULL;
832
833	switch (GET_CODE (pattern))
834	{
835	case SET:
836	set_dest = SET_DEST (pattern);
837	break;
838	case PARALLEL:
839	{
840	rtx pattern2 = XVECEXP (PATTERN (set_insn), 0,0);
841	if (GET_CODE (pattern2) == SET)
842	set_dest = SET_DEST (pattern2);
843	break;
844	}
845	default:
846	set_dest = NULL;
847	}
848
849	/* True if destination of set is reg and used as address. */
850	return set_dest && REG_P (set_dest)
851	&& reg_mentioned_by_mem_p (set_dest, use_insn);
852	}
853
731		854
732	/* Return 1 if in between BEG and END, exclusive of BEG and END, there is	855	/* Return 1 if in between BEG and END, exclusive of BEG and END, there is
733	no CODE_LABEL insn. */	856	no CODE_LABEL insn. */

Lines 1-5 Link Here

(-)gcc/genautomata.c (-60 / +99 lines)
1	/* Pipeline hazard description translator.	1	/* Pipeline hazard description translator.
2	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008	2	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
3	Free Software Foundation, Inc.	3	Free Software Foundation, Inc.
4		4
5	Written by Vladimir Makarov <vmakarov@redhat.com>	5	Written by Vladimir Makarov <vmakarov@redhat.com>
Lines 22-42 Link Here
22		22
23	/* References:	23	/* References:
24		24
25	1. Detecting pipeline structural hazards quickly. T. Proebsting,	25	1. The finite state automaton based pipeline hazard recognizer and
		26	instruction scheduler in GCC. V. Makarov. Proceedings of GCC
		27	summit, 2003.
		28
		29	2. Detecting pipeline structural hazards quickly. T. Proebsting,
26	C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on	30	C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on
27	Principles of Programming Languages, pages 280--286, 1994.	31	Principles of Programming Languages, pages 280--286, 1994.
28		32
29	This article is a good start point to understand usage of finite	33	This article is a good start point to understand usage of finite
30	state automata for pipeline hazard recognizers. But I'd	34	state automata for pipeline hazard recognizers. But I'd
31	recommend the 2nd article for more deep understanding.	35	recommend the 1st and 3rd article for more deep understanding.
32		36
33	2. Efficient Instruction Scheduling Using Finite State Automata:	37	3. Efficient Instruction Scheduling Using Finite State Automata:
34	V. Bala and N. Rubin, Proceedings of MICRO-28. This is the best	38	V. Bala and N. Rubin, Proceedings of MICRO-28. This is the best
35	article about usage of finite state automata for pipeline hazard	39	article about usage of finite state automata for pipeline hazard
36	recognizers.	40	recognizers.
37		41
38	The current implementation is different from the 2nd article in the	42	The current implementation is described in the 1st article and it
39	following:	43	is different from the 3rd article in the following:
40		44
41	1. New operator `\|' (alternative) is permitted in functional unit	45	1. New operator `\|' (alternative) is permitted in functional unit
42	reservation which can be treated deterministically and	46	reservation which can be treated deterministically and
Lines 463-469 Link Here
463	insn. */	467	insn. */
464	int insn_num;	468	int insn_num;
465	/* The following field value is list of bypasses in which given insn	469	/* The following field value is list of bypasses in which given insn
466	is output insn. */	470	is output insn. Bypasses with the same input insn stay one after
		471	another in the list in the same order as their occurrences in the
		472	description but the bypass without a guard stays always the last
		473	in a row of bypasses with the same input insn. */
467	struct bypass_decl *bypass_list;	474	struct bypass_decl *bypass_list;
468		475
469	/* The following fields are defined by automaton generator. */	476	/* The following fields are defined by automaton generator. */
Lines 2367-2384 Link Here
2367	}	2374	}
2368		2375
2369		2376
2370	/* The function searches for bypass with given IN_INSN_RESERV in given	2377	/* The function inserts BYPASS in the list of bypasses of the
2371	BYPASS_LIST. */	2378	corresponding output insn. The order of bypasses in the list is
2372	static struct bypass_decl *	2379	decribed in a comment for member `bypass_list' (see above). If
2373	find_bypass (struct bypass_decl *bypass_list,	2380	there is already the same bypass in the list the function reports
2374	struct insn_reserv_decl *in_insn_reserv)	2381	this and does nothing. */
		2382	static void
		2383	insert_bypass (struct bypass_decl *bypass)
2375	{	2384	{
2376	struct bypass_decl *bypass;	2385	struct bypass_decl curr, last;
2377		2386	struct insn_reserv_decl *out_insn_reserv = bypass->out_insn_reserv;
2378	for (bypass = bypass_list; bypass != NULL; bypass = bypass->next)	2387	struct insn_reserv_decl *in_insn_reserv = bypass->in_insn_reserv;
2379	if (bypass->in_insn_reserv == in_insn_reserv)	2388
2380	break;	2389	for (curr = out_insn_reserv->bypass_list, last = NULL;
2381	return bypass;	2390	curr != NULL;
		2391	last = curr, curr = curr->next)
		2392	if (curr->in_insn_reserv == in_insn_reserv)
		2393	{
		2394	if ((bypass->bypass_guard_name != NULL
		2395	&& curr->bypass_guard_name != NULL
		2396	&& ! strcmp (bypass->bypass_guard_name, curr->bypass_guard_name))
		2397	\|\| bypass->bypass_guard_name == curr->bypass_guard_name)
		2398	{
		2399	if (bypass->bypass_guard_name == NULL)
		2400	{
		2401	if (!w_flag)
		2402	error ("the same bypass `%s - %s' is already defined",
		2403	bypass->out_insn_name, bypass->in_insn_name);
		2404	else
		2405	warning (0, "the same bypass `%s - %s' is already defined",
		2406	bypass->out_insn_name, bypass->in_insn_name);
		2407	}
		2408	else if (!w_flag)
		2409	error ("the same bypass `%s - %s' (guard %s) is already defined",
		2410	bypass->out_insn_name, bypass->in_insn_name,
		2411	bypass->bypass_guard_name);
		2412	else
		2413	warning
		2414	(0, "the same bypass `%s - %s' (guard %s) is already defined",
		2415	bypass->out_insn_name, bypass->in_insn_name,
		2416	bypass->bypass_guard_name);
		2417	return;
		2418	}
		2419	if (curr->bypass_guard_name == NULL)
		2420	break;
		2421	if (curr->next == NULL \|\| curr->next->in_insn_reserv != in_insn_reserv)
		2422	{
		2423	last = curr;
		2424	break;
		2425	}
		2426
		2427	}
		2428	if (last == NULL)
		2429	{
		2430	bypass->next = out_insn_reserv->bypass_list;
		2431	out_insn_reserv->bypass_list = bypass;
		2432	}
		2433	else
		2434	{
		2435	bypass->next = last->next;
		2436	last->next = bypass;
		2437	}
2382	}	2438	}
2383		2439
2384	/* The function processes pipeline description declarations, checks	2440	/* The function processes pipeline description declarations, checks
Lines 2391-2397 Link Here
2391	decl_t decl_in_table;	2447	decl_t decl_in_table;
2392	decl_t out_insn_reserv;	2448	decl_t out_insn_reserv;
2393	decl_t in_insn_reserv;	2449	decl_t in_insn_reserv;
2394	struct bypass_decl *bypass;
2395	int automaton_presence;	2450	int automaton_presence;
2396	int i;	2451	int i;
2397		2452
Lines 2514-2549 Link Here
2514	= DECL_INSN_RESERV (out_insn_reserv);	2569	= DECL_INSN_RESERV (out_insn_reserv);
2515	DECL_BYPASS (decl)->in_insn_reserv	2570	DECL_BYPASS (decl)->in_insn_reserv
2516	= DECL_INSN_RESERV (in_insn_reserv);	2571	= DECL_INSN_RESERV (in_insn_reserv);
2517	bypass	2572	insert_bypass (DECL_BYPASS (decl));
2518	= find_bypass (DECL_INSN_RESERV (out_insn_reserv)->bypass_list,
2519	DECL_BYPASS (decl)->in_insn_reserv);
2520	if (bypass != NULL)
2521	{
2522	if (DECL_BYPASS (decl)->latency == bypass->latency)
2523	{
2524	if (!w_flag)
2525	error
2526	("the same bypass `%s - %s' is already defined",
2527	DECL_BYPASS (decl)->out_insn_name,
2528	DECL_BYPASS (decl)->in_insn_name);
2529	else
2530	warning
2531	(0, "the same bypass `%s - %s' is already defined",
2532	DECL_BYPASS (decl)->out_insn_name,
2533	DECL_BYPASS (decl)->in_insn_name);
2534	}
2535	else
2536	error ("bypass `%s - %s' is already defined",
2537	DECL_BYPASS (decl)->out_insn_name,
2538	DECL_BYPASS (decl)->in_insn_name);
2539	}
2540	else
2541	{
2542	DECL_BYPASS (decl)->next
2543	= DECL_INSN_RESERV (out_insn_reserv)->bypass_list;
2544	DECL_INSN_RESERV (out_insn_reserv)->bypass_list
2545	= DECL_BYPASS (decl);
2546	}
2547	}	2573	}
2548	}	2574	}
2549	}	2575	}
Lines 8159-8177 Link Here
8159	(advance_cycle_insn_decl)->insn_num));	8185	(advance_cycle_insn_decl)->insn_num));
8160	fprintf (output_file, " case %d:\n",	8186	fprintf (output_file, " case %d:\n",
8161	bypass->in_insn_reserv->insn_num);	8187	bypass->in_insn_reserv->insn_num);
8162	if (bypass->bypass_guard_name == NULL)	8188	for (;;)
8163	fprintf (output_file, " return %d;\n",
8164	bypass->latency);
8165	else
8166	{	8189	{
8167	fprintf (output_file,	8190	if (bypass->bypass_guard_name == NULL)
8168	" if (%s (%s, %s))\n",	8191	{
8169	bypass->bypass_guard_name, INSN_PARAMETER_NAME,	8192	gcc_assert (bypass->next == NULL
8170	INSN2_PARAMETER_NAME);	8193	\|\| (bypass->in_insn_reserv
8171	fprintf (output_file,	8194	!= bypass->next->in_insn_reserv));
8172	" return %d;\n break;\n",	8195	fprintf (output_file, " return %d;\n",
8173	bypass->latency);	8196	bypass->latency);
		8197	}
		8198	else
		8199	{
		8200	fprintf (output_file,
		8201	" if (%s (%s, %s))\n",
		8202	bypass->bypass_guard_name, INSN_PARAMETER_NAME,
		8203	INSN2_PARAMETER_NAME);
		8204	fprintf (output_file, " return %d;\n",
		8205	bypass->latency);
		8206	}
		8207	if (bypass->next == NULL
		8208	\|\| bypass->in_insn_reserv != bypass->next->in_insn_reserv)
		8209	break;
		8210	bypass = bypass->next;
8174	}	8211	}
		8212	if (bypass->bypass_guard_name != NULL)
		8213	fprintf (output_file, " break;\n");
8175	}	8214	}
8176	fputs (" }\n break;\n", output_file);	8215	fputs (" }\n break;\n", output_file);
8177	}	8216	}

Line 0 Link Here

(-)gcc/ChangeLog.atom (+134 lines)
		1	2009-02-05 Joey Ye <joey.ye@intel.com>
		2	Xuepeng Guo <xuepeng.guo@intel.com>
		3	H.J. Lu <hongjiu.lu@intel.com>
		4
		5	Atom pipeline model, tuning and insn selection.
		6	* rtlanal.c (reg_mentioned_by_mem_p_1): New function.
		7	(reg_mentioned_by_mem_p): New function.
		8	(reg_dep_by_addr_p): New function.
		9
		10	* rtl.h (reg_mentioned_by_mem_p): Declare new function.
		11	(reg_dep_by_addr_p): Likewise.
		12
		13	* config.gcc (atom): Add atom config options and target.
		14
		15	* config/i386/i386.h (TARGET_ATOM): New target macro.
		16	(X86_TUNE_OPT_AGU): New tuning flag.
		17	(TARGET_OPT_AGU): New target option.
		18	(TARGET_CPU_DEFAULT_atom): New CPU default.
		19	(PROCESSOR_ATOM): New processor.
		20
		21	* config/i386/i386-c.c (ix86_target_macros_internal): New case
		22	PROCESSOR_ATOM.
		23	(ix86_target_macros_internal): Likewise.
		24
		25	* config/i386/i386-protos.h (ix86_lea_for_add_ok): Declare new
		26	function.
		27	(ix86_dep_by_shift_count): Likewise.
		28	(ix86_agi_dependent): Likewise.
		29
		30	* config/i386/i386.c (atom_cost): New cost.
		31	(m_ATOM): New macro flag.
		32	(initial_ix86_tune_fe): Set m_ATOM.
		33	(x86_accumulate_outgoing_args): Likewise.
		34	(x86_arch_always_fancy_math_387): Likewise.
		35	(processor_target): Add Atom cost.
		36	(cpu_names): Add Atom cpu name.
		37	(override_options): Set Atom ISA.
		38	(LEA_SEARCH_THRESHOLD): New macro.
		39	(distance_non_agu_define): New function.
		40	(distance_agu_use): Likewise.
		41	(ix86_lea_for_add_ok): Likewise.
		42	(ix86_dep_by_shift_count): Likewise.
		43	(ix86_agi_dependent): Make it global.
		44	(ix86_issue_rate): New case PROCESSOR_ATOM.
		45	(ix86_adjust_cost): Likewise.
		46
		47	* config/i386/i386.md (cpu): Add new value "atom".
		48	(atom.md): Include atom.md.
		49	(use_carry, movu): New attr.
		50	(adddi3_carry_rex64): Set attr "use_carry".
		51	(addqi3_carry): Likewise.
		52	(addhi3_carry): Likewise.
		53	(addsi3_carry): Likewise.
		54	(*addsi3_carry_zext): Likewise.
		55	(subdi3_carry_rex64): Likewise.
		56	(subqi3_carry): Likewise.
		57	(subhi3_carry): Likewise.
		58	(subsi3_carry): Likewise.
		59	(x86_movdicc_0_m1_rex64): Likewise.
		60	(*x86_movdicc_0_m1_se): Likewise.
		61	(x86_movsicc_0_m1): Likewise.
		62	(*x86_movsicc_0_m1_se): Likewise.
		63	(*adddi_1_rex64): Emit add insn as much as possible.
		64	(*addsi_1): Likewise.
65	(return_internal): Set atom_unit.
66	(return_internal_long): Likewise.
67	(return_pop_internal): Likewise.
68	(*rcpsf2_sse): Set atom_sse_attr attr.
69	(*qrt<mode>2_sse): Likewise.
70	(*prefetch_sse): Likewise.
71
72	* config/i386/sse.md (cpu): Set attr "atom_sse_attr".
73	(*prefetch_sse_rex): Likewise.
74	(sse_rcpv4sf2): Likewise.
75	(sse_vmrcpv4sf2): Likewise.
76	(sse_sqrtv4sf2): Likewise.
77	(<sse>_vmsqrt<mode>2): Likewise.
78	(sse_ldmxcsr): Likewise.
79	(sse_stmxcsr): Likewise.
80	(*sse_sfence): Likewise.
81	(sse2_clflush): Likewise.
82	(*sse2_mfence): Likewise.
83	(*sse2_lfence): Likewise.
84	(avx_movup<avxmodesuffixf2c><avxmodesuffix>): Set attr "movu".
85	(<sse>_movup<ssemodesuffixf2c>): Likewise.
86	(avx_movdqu<avxmodesuffix>): Likewise.
87	(avx_lddqu<avxmodesuffix>): Likewise.
88	(sse2_movntv2di): Change attr "type" to "ssemov".
89	(sse2_movntsi): Likewise.
90	(rsqrtv8sf2): Change attr "type" to "sseadd".
91	(sse3_addsubv2df3): Set attr "atom_unit".
92	(sse3_h<plusminus_insn>v4sf3): Likewise.
93	(*sse2_pmaddwd): Likewise.
94	(*vec_extractv2di_1_rex64): Likewise.
95	(*vec_extractv2di_1_avx): Likewise.
96	(sse2_psadbw): Likewise.
97	(ssse3_phaddwv8hi3): Likewise.
98	(ssse3_phaddwv4hi3): Likewise.
99	(ssse3_phadddv4si3): Likewise.
100	(ssse3_phadddv2si3): Likewise.
101	(ssse3_phaddswv8hi3): Likewise.
102	(ssse3_phaddswv4hi3): Likewise.
103	(ssse3_phsubwv8hi3): Likewise.
104	(ssse3_phsubwv4hi3): Likewise.
105	(ssse3_phsubdv4si3): Likewise.
106	(ssse3_phsubdv2si3): Likewise.
107	(ssse3_phsubswv8hi3): Likewise.
108	(ssse3_phsubswv4hi3): Likewise.
109	(ssse3_pmaddubsw128): Likewise.
110	(sse3_pmaddubsw: Likewise.
111	(ssse3_palignrti): Likewise.
112	(ssse3_palignrdi): Likewise.
113
114	* config/i386/atom.md: New.
115
116	2009-02-05 H.J. Lu <hongjiu.lu@intel.com>
117
118	* config/i386/i386.c (ix86_agi_dependent): Remove the third
119	argument. Swap the first 2 arguments.
120	(ix86_adjust_cost): Updated.
121
122	2009-01-30 Vladimir Makarov <vmakarov@redhat.com>
123
124	* genautomata.c: Add a new year to the copyright. Add a new
125	reference.
126	(struct insn_reserv_decl): Add comments for member bypass_list.
127	(find_bypass): Remove.
128	(insert_bypass): New.
129	(process_decls): Use insert_bypass.
130	(output_internal_insn_latency_func): Output all bypasses with the
131	same input insn in one switch case.
132
133	* rtl.def (define_bypass): Describe bypass choice.
134	* doc/md.texi (define_bypass): Ditto.

Lines 1087-1093 Link Here

(-)gcc/config.gcc (-5 / +5 lines)
1087	tmake_file="${tmake_file} i386/t-linux64"	1087	tmake_file="${tmake_file} i386/t-linux64"
1088	need_64bit_hwint=yes	1088	need_64bit_hwint=yes
1089	case X"${with_cpu}" in	1089	case X"${with_cpu}" in
1090	Xgeneric\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)	1090	Xgeneric\|Xatom\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)
1091	;;	1091	;;
1092	X)	1092	X)
1093	if test x$with_cpu_64 = x; then	1093	if test x$with_cpu_64 = x; then
Lines 1096-1102 Link Here
1096	;;	1096	;;
1097	*)	1097	*)
1098	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2	1098	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1099	echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2	1099	echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1100	exit 1	1100	exit 1
1101	;;	1101	;;
1102	esac	1102	esac
Lines 1201-1207 Link Here
1201	# libgcc/configure.ac instead.	1201	# libgcc/configure.ac instead.
1202	need_64bit_hwint=yes	1202	need_64bit_hwint=yes
1203	case X"${with_cpu}" in	1203	case X"${with_cpu}" in
1204	Xgeneric\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)	1204	Xgeneric\|Xatom\|Xcore2\|Xnocona\|Xx86-64\|Xamdfam10\|Xbarcelona\|Xk8\|Xopteron\|Xathlon64\|Xathlon-fx)
1205	;;	1205	;;
1206	X)	1206	X)
1207	if test x$with_cpu_64 = x; then	1207	if test x$with_cpu_64 = x; then
Lines 1210-1216 Link Here
1210	;;	1210	;;
1211	*)	1211	*)
1212	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2	1212	echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1213	echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2	1213	echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1214	exit 1	1214	exit 1
1215	;;	1215	;;
1216	esac	1216	esac
Lines 2803-2809 Link Here
2803	esac	2803	esac
2804	# OK	2804	# OK
2805	;;	2805	;;
2806	"" \| amdfam10 \| barcelona \| k8 \| opteron \| athlon64 \| athlon-fx \| nocona \| core2 \| generic)	2806	"" \| amdfam10 \| barcelona \| k8 \| opteron \| athlon64 \| athlon-fx \| nocona \| core2 \| atom \| generic)
2807	# OK	2807	# OK
2808	;;	2808	;;
2809	*)	2809	*)

Lines 231-236 Link Here

(-)gcc/config/i386/i386.h (+5 lines)
231	#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)	231	#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
232	#define TARGET_GENERIC (TARGET_GENERIC32 \|\| TARGET_GENERIC64)	232	#define TARGET_GENERIC (TARGET_GENERIC32 \|\| TARGET_GENERIC64)
233	#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)	233	#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
		234	#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
234		235
235	/* Feature tests against the various tunings. */	236	/* Feature tests against the various tunings. */
236	enum ix86_tune_indices {	237	enum ix86_tune_indices {
Lines 295-300 Link Here
295	X86_TUNE_USE_VECTOR_FP_CONVERTS,	296	X86_TUNE_USE_VECTOR_FP_CONVERTS,
296	X86_TUNE_USE_VECTOR_CONVERTS,	297	X86_TUNE_USE_VECTOR_CONVERTS,
297	X86_TUNE_FUSE_CMP_AND_BRANCH,	298	X86_TUNE_FUSE_CMP_AND_BRANCH,
		299	X86_TUNE_OPT_AGU,
298		300
299	X86_TUNE_LAST	301	X86_TUNE_LAST
300	};	302	};
Lines 382-387 Link Here
382	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]	384	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
383	#define TARGET_FUSE_CMP_AND_BRANCH \	385	#define TARGET_FUSE_CMP_AND_BRANCH \
384	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]	386	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
		387	#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
385		388
386	/* Feature tests against the various architecture variations. */	389	/* Feature tests against the various architecture variations. */
387	enum ix86_arch_indices {	390	enum ix86_arch_indices {
Lines 564-569 Link Here
564	TARGET_CPU_DEFAULT_prescott,	567	TARGET_CPU_DEFAULT_prescott,
565	TARGET_CPU_DEFAULT_nocona,	568	TARGET_CPU_DEFAULT_nocona,
566	TARGET_CPU_DEFAULT_core2,	569	TARGET_CPU_DEFAULT_core2,
		570	TARGET_CPU_DEFAULT_atom,
567		571
568	TARGET_CPU_DEFAULT_geode,	572	TARGET_CPU_DEFAULT_geode,
569	TARGET_CPU_DEFAULT_k6,	573	TARGET_CPU_DEFAULT_k6,
Lines 2256-2261 Link Here
2256	PROCESSOR_GENERIC32,	2260	PROCESSOR_GENERIC32,
2257	PROCESSOR_GENERIC64,	2261	PROCESSOR_GENERIC64,
2258	PROCESSOR_AMDFAM10,	2262	PROCESSOR_AMDFAM10,
		2263	PROCESSOR_ATOM,
2259	PROCESSOR_max	2264	PROCESSOR_max
2260	};	2265	};
2261		2266

Lines 338-343 Link Here

(-)gcc/config/i386/sse.md (-9 / +47 lines)
338	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"	338	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
339	"vmovup<avxmodesuffixf2c>\t{%1, %0\|%0, %1}"	339	"vmovup<avxmodesuffixf2c>\t{%1, %0\|%0, %1}"
340	[(set_attr "type" "ssemov")	340	[(set_attr "type" "ssemov")
		341	(set_attr "movu" "1")
341	(set_attr "prefix" "vex")	342	(set_attr "prefix" "vex")
342	(set_attr "mode" "<MODE>")])	343	(set_attr "mode" "<MODE>")])
343		344
Lines 363-368 Link Here
363	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"	364	&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
364	"movup<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	365	"movup<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
365	[(set_attr "type" "ssemov")	366	[(set_attr "type" "ssemov")
		367	(set_attr "movu" "1")
366	(set_attr "mode" "<MODE>")])	368	(set_attr "mode" "<MODE>")])
367		369
368	(define_insn "avx_movdqu<avxmodesuffix>"	370	(define_insn "avx_movdqu<avxmodesuffix>"
Lines 373-378 Link Here
373	"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"	375	"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
374	"vmovdqu\t{%1, %0\|%0, %1}"	376	"vmovdqu\t{%1, %0\|%0, %1}"
375	[(set_attr "type" "ssemov")	377	[(set_attr "type" "ssemov")
		378	(set_attr "movu" "1")
376	(set_attr "prefix" "vex")	379	(set_attr "prefix" "vex")
377	(set_attr "mode" "<avxvecmode>")])	380	(set_attr "mode" "<avxvecmode>")])
378		381
Lines 383-388 Link Here
383	"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"	386	"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
384	"movdqu\t{%1, %0\|%0, %1}"	387	"movdqu\t{%1, %0\|%0, %1}"
385	[(set_attr "type" "ssemov")	388	[(set_attr "type" "ssemov")
		389	(set_attr "movu" "1")
386	(set_attr "prefix_data16" "1")	390	(set_attr "prefix_data16" "1")
387	(set_attr "mode" "TI")])	391	(set_attr "mode" "TI")])
388		392
Lines 424-430 Link Here
424	UNSPEC_MOVNT))]	428	UNSPEC_MOVNT))]
425	"TARGET_SSE2"	429	"TARGET_SSE2"
426	"movntdq\t{%1, %0\|%0, %1}"	430	"movntdq\t{%1, %0\|%0, %1}"
427	[(set_attr "type" "ssecvt")	431	[(set_attr "type" "ssemov")
428	(set_attr "prefix_data16" "1")	432	(set_attr "prefix_data16" "1")
429	(set_attr "mode" "TI")])	433	(set_attr "mode" "TI")])
430		434
Lines 434-440 Link Here
434	UNSPEC_MOVNT))]	438	UNSPEC_MOVNT))]
435	"TARGET_SSE2"	439	"TARGET_SSE2"
436	"movnti\t{%1, %0\|%0, %1}"	440	"movnti\t{%1, %0\|%0, %1}"
437	[(set_attr "type" "ssecvt")	441	[(set_attr "type" "ssemov")
438	(set_attr "mode" "V2DF")])	442	(set_attr "mode" "V2DF")])
439		443
440	(define_insn "avx_lddqu<avxmodesuffix>"	444	(define_insn "avx_lddqu<avxmodesuffix>"
Lines 445-450 Link Here
445	"TARGET_AVX"	449	"TARGET_AVX"
446	"vlddqu\t{%1, %0\|%0, %1}"	450	"vlddqu\t{%1, %0\|%0, %1}"
447	[(set_attr "type" "ssecvt")	451	[(set_attr "type" "ssecvt")
		452	(set_attr "movu" "1")
448	(set_attr "prefix" "vex")	453	(set_attr "prefix" "vex")
449	(set_attr "mode" "<avxvecmode>")])	454	(set_attr "mode" "<avxvecmode>")])
450		455
Lines 454-460 Link Here
454	UNSPEC_LDDQU))]	459	UNSPEC_LDDQU))]
455	"TARGET_SSE3"	460	"TARGET_SSE3"
456	"lddqu\t{%1, %0\|%0, %1}"	461	"lddqu\t{%1, %0\|%0, %1}"
457	[(set_attr "type" "ssecvt")	462	[(set_attr "type" "ssemov")
		463	(set_attr "movu" "1")
458	(set_attr "prefix_rep" "1")	464	(set_attr "prefix_rep" "1")
459	(set_attr "mode" "TI")])	465	(set_attr "mode" "TI")])
460		466
Lines 761-766 Link Here
761	"TARGET_SSE"	767	"TARGET_SSE"
762	"%vrcpps\t{%1, %0\|%0, %1}"	768	"%vrcpps\t{%1, %0\|%0, %1}"
763	[(set_attr "type" "sse")	769	[(set_attr "type" "sse")
		770	(set_attr "atom_sse_attr" "rcp")
764	(set_attr "prefix" "maybe_vex")	771	(set_attr "prefix" "maybe_vex")
765	(set_attr "mode" "V4SF")])	772	(set_attr "mode" "V4SF")])
766		773
Lines 787-792 Link Here
787	"TARGET_SSE"	794	"TARGET_SSE"
788	"rcpss\t{%1, %0\|%0, %1}"	795	"rcpss\t{%1, %0\|%0, %1}"
789	[(set_attr "type" "sse")	796	[(set_attr "type" "sse")
		797	(set_attr "atom_sse_attr" "rcp")
790	(set_attr "mode" "SF")])	798	(set_attr "mode" "SF")])
791		799
792	(define_expand "sqrtv8sf2"	800	(define_expand "sqrtv8sf2"
Lines 832-837 Link Here
832	"TARGET_SSE"	840	"TARGET_SSE"
833	"%vsqrtps\t{%1, %0\|%0, %1}"	841	"%vsqrtps\t{%1, %0\|%0, %1}"
834	[(set_attr "type" "sse")	842	[(set_attr "type" "sse")
		843	(set_attr "atom_sse_attr" "sqrt")
835	(set_attr "prefix" "maybe_vex")	844	(set_attr "prefix" "maybe_vex")
836	(set_attr "mode" "V4SF")])	845	(set_attr "mode" "V4SF")])
837		846
Lines 876-881 Link Here
876	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	885	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
877	"sqrts<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	886	"sqrts<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
878	[(set_attr "type" "sse")	887	[(set_attr "type" "sse")
		888	(set_attr "atom_sse_attr" "sqrt")
879	(set_attr "mode" "<ssescalarmode>")])	889	(set_attr "mode" "<ssescalarmode>")])
880		890
881	(define_expand "rsqrtv8sf2"	891	(define_expand "rsqrtv8sf2"
Lines 1039-1045 Link Here
1039	(const_int 1)))]	1049	(const_int 1)))]
1040	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	1050	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1041	"<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0\|%0, %2}"	1051	"<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0\|%0, %2}"
1042	[(set_attr "type" "sse")	1052	[(set_attr "type" "sseadd")
1043	(set_attr "mode" "<ssescalarmode>")])	1053	(set_attr "mode" "<ssescalarmode>")])
1044		1054
1045	;; These versions of the min/max patterns implement exactly the operations	1055	;; These versions of the min/max patterns implement exactly the operations
Lines 1175-1180 Link Here
1175	"TARGET_SSE3"	1185	"TARGET_SSE3"
1176	"addsubpd\t{%2, %0\|%0, %2}"	1186	"addsubpd\t{%2, %0\|%0, %2}"
1177	[(set_attr "type" "sseadd")	1187	[(set_attr "type" "sseadd")
		1188	(set_attr "atom_unit" "complex")
1178	(set_attr "mode" "V2DF")])	1189	(set_attr "mode" "V2DF")])
1179		1190
1180	(define_insn "avx_h<plusminus_insn>v4df3"	1191	(define_insn "avx_h<plusminus_insn>v4df3"
Lines 1298-1303 Link Here
1298	"TARGET_SSE3"	1309	"TARGET_SSE3"
1299	"h<plusminus_mnemonic>ps\t{%2, %0\|%0, %2}"	1310	"h<plusminus_mnemonic>ps\t{%2, %0\|%0, %2}"
1300	[(set_attr "type" "sseadd")	1311	[(set_attr "type" "sseadd")
		1312	(set_attr "atom_unit" "complex")
1301	(set_attr "prefix_rep" "1")	1313	(set_attr "prefix_rep" "1")
1302	(set_attr "mode" "V4SF")])	1314	(set_attr "mode" "V4SF")])
1303		1315
Lines 5066-5071 Link Here
5066	"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"	5078	"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5067	"pmaddwd\t{%2, %0\|%0, %2}"	5079	"pmaddwd\t{%2, %0\|%0, %2}"
5068	[(set_attr "type" "sseiadd")	5080	[(set_attr "type" "sseiadd")
		5081	(set_attr "atom_unit" "simul")
5069	(set_attr "prefix_data16" "1")	5082	(set_attr "prefix_data16" "1")
5070	(set_attr "mode" "TI")])	5083	(set_attr "mode" "TI")])
5071		5084
Lines 7025-7030 Link Here
7025	movq\t{%H1, %0\|%0, %H1}	7038	movq\t{%H1, %0\|%0, %H1}
7026	mov{q}\t{%H1, %0\|%0, %H1}"	7039	mov{q}\t{%H1, %0\|%0, %H1}"
7027	[(set_attr "type" "ssemov,sseishft,ssemov,imov")	7040	[(set_attr "type" "ssemov,sseishft,ssemov,imov")
		7041	(set_attr "atom_unit" ",sishuf,,*")
7028	(set_attr "memory" ",none,,*")	7042	(set_attr "memory" ",none,,*")
7029	(set_attr "mode" "V2SF,TI,TI,DI")])	7043	(set_attr "mode" "V2SF,TI,TI,DI")])
7030		7044
Lines 7057-7062 Link Here
7057	psrldq\t{$8, %0\|%0, 8}	7071	psrldq\t{$8, %0\|%0, 8}
7058	movq\t{%H1, %0\|%0, %H1}"	7072	movq\t{%H1, %0\|%0, %H1}"
7059	[(set_attr "type" "ssemov,sseishft,ssemov")	7073	[(set_attr "type" "ssemov,sseishft,ssemov")
		7074	(set_attr "atom_unit" ",sishuf,")
7060	(set_attr "memory" ",none,")	7075	(set_attr "memory" ",none,")
7061	(set_attr "mode" "V2SF,TI,TI")])	7076	(set_attr "mode" "V2SF,TI,TI")])
7062		7077
Lines 7614-7619 Link Here
7614	"TARGET_SSE2"	7629	"TARGET_SSE2"
7615	"psadbw\t{%2, %0\|%0, %2}"	7630	"psadbw\t{%2, %0\|%0, %2}"
7616	[(set_attr "type" "sseiadd")	7631	[(set_attr "type" "sseiadd")
		7632	(set_attr "atom_unit" "simul")
7617	(set_attr "prefix_data16" "1")	7633	(set_attr "prefix_data16" "1")
7618	(set_attr "mode" "TI")])	7634	(set_attr "mode" "TI")])
7619		7635
Lines 7635-7641 Link Here
7635	UNSPEC_MOVMSK))]	7651	UNSPEC_MOVMSK))]
7636	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"	7652	"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
7637	"%vmovmskp<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"	7653	"%vmovmskp<ssemodesuffixf2c>\t{%1, %0\|%0, %1}"
7638	[(set_attr "type" "ssecvt")	7654	[(set_attr "type" "ssemov")
7639	(set_attr "prefix" "maybe_vex")	7655	(set_attr "prefix" "maybe_vex")
7640	(set_attr "mode" "<MODE>")])	7656	(set_attr "mode" "<MODE>")])
7641		7657
Lines 7645-7651 Link Here
7645	UNSPEC_MOVMSK))]	7661	UNSPEC_MOVMSK))]
7646	"TARGET_SSE2"	7662	"TARGET_SSE2"
7647	"%vpmovmskb\t{%1, %0\|%0, %1}"	7663	"%vpmovmskb\t{%1, %0\|%0, %1}"
7648	[(set_attr "type" "ssecvt")	7664	[(set_attr "type" "ssemov")
7649	(set_attr "prefix_data16" "1")	7665	(set_attr "prefix_data16" "1")
7650	(set_attr "prefix" "maybe_vex")	7666	(set_attr "prefix" "maybe_vex")
7651	(set_attr "mode" "SI")])	7667	(set_attr "mode" "SI")])
Lines 7668-7674 Link Here
7668	"TARGET_SSE2 && !TARGET_64BIT"	7684	"TARGET_SSE2 && !TARGET_64BIT"
7669	;; @@@ check ordering of operands in intel/nonintel syntax	7685	;; @@@ check ordering of operands in intel/nonintel syntax
7670	"%vmaskmovdqu\t{%2, %1\|%1, %2}"	7686	"%vmaskmovdqu\t{%2, %1\|%1, %2}"
7671	[(set_attr "type" "ssecvt")	7687	[(set_attr "type" "ssemov")
7672	(set_attr "prefix_data16" "1")	7688	(set_attr "prefix_data16" "1")
7673	(set_attr "prefix" "maybe_vex")	7689	(set_attr "prefix" "maybe_vex")
7674	(set_attr "mode" "TI")])	7690	(set_attr "mode" "TI")])
Lines 7682-7688 Link Here
7682	"TARGET_SSE2 && TARGET_64BIT"	7698	"TARGET_SSE2 && TARGET_64BIT"
7683	;; @@@ check ordering of operands in intel/nonintel syntax	7699	;; @@@ check ordering of operands in intel/nonintel syntax
7684	"%vmaskmovdqu\t{%2, %1\|%1, %2}"	7700	"%vmaskmovdqu\t{%2, %1\|%1, %2}"
7685	[(set_attr "type" "ssecvt")	7701	[(set_attr "type" "ssemov")
7686	(set_attr "prefix_data16" "1")	7702	(set_attr "prefix_data16" "1")
7687	(set_attr "prefix" "maybe_vex")	7703	(set_attr "prefix" "maybe_vex")
7688	(set_attr "mode" "TI")])	7704	(set_attr "mode" "TI")])
Lines 7693-7698 Link Here
7693	"TARGET_SSE"	7709	"TARGET_SSE"
7694	"%vldmxcsr\t%0"	7710	"%vldmxcsr\t%0"
7695	[(set_attr "type" "sse")	7711	[(set_attr "type" "sse")
		7712	(set_attr "atom_sse_attr" "mxcsr")
7696	(set_attr "prefix" "maybe_vex")	7713	(set_attr "prefix" "maybe_vex")
7697	(set_attr "memory" "load")])	7714	(set_attr "memory" "load")])
7698		7715
Lines 7702-7707 Link Here
7702	"TARGET_SSE"	7719	"TARGET_SSE"
7703	"%vstmxcsr\t%0"	7720	"%vstmxcsr\t%0"
7704	[(set_attr "type" "sse")	7721	[(set_attr "type" "sse")
		7722	(set_attr "atom_sse_attr" "mxcsr")
7705	(set_attr "prefix" "maybe_vex")	7723	(set_attr "prefix" "maybe_vex")
7706	(set_attr "memory" "store")])	7724	(set_attr "memory" "store")])
7707		7725
Lines 7720-7725 Link Here
7720	"TARGET_SSE \|\| TARGET_3DNOW_A"	7738	"TARGET_SSE \|\| TARGET_3DNOW_A"
7721	"sfence"	7739	"sfence"
7722	[(set_attr "type" "sse")	7740	[(set_attr "type" "sse")
		7741	(set_attr "atom_sse_attr" "fence")
7723	(set_attr "memory" "unknown")])	7742	(set_attr "memory" "unknown")])
7724		7743
7725	(define_insn "sse2_clflush"	7744	(define_insn "sse2_clflush"
Lines 7728-7733 Link Here
7728	"TARGET_SSE2"	7747	"TARGET_SSE2"
7729	"clflush\t%a0"	7748	"clflush\t%a0"
7730	[(set_attr "type" "sse")	7749	[(set_attr "type" "sse")
		7750	(set_attr "atom_sse_attr" "fence")
7731	(set_attr "memory" "unknown")])	7751	(set_attr "memory" "unknown")])
7732		7752
7733	(define_expand "sse2_mfence"	7753	(define_expand "sse2_mfence"
Lines 7745-7750 Link Here
7745	"TARGET_64BIT \|\| TARGET_SSE2"	7765	"TARGET_64BIT \|\| TARGET_SSE2"
7746	"mfence"	7766	"mfence"
7747	[(set_attr "type" "sse")	7767	[(set_attr "type" "sse")
		7768	(set_attr "atom_sse_attr" "fence")
7748	(set_attr "memory" "unknown")])	7769	(set_attr "memory" "unknown")])
7749		7770
7750	(define_expand "sse2_lfence"	7771	(define_expand "sse2_lfence"
Lines 7762-7767 Link Here
7762	"TARGET_SSE2"	7783	"TARGET_SSE2"
7763	"lfence"	7784	"lfence"
7764	[(set_attr "type" "sse")	7785	[(set_attr "type" "sse")
		7786	(set_attr "atom_sse_attr" "lfence")
7765	(set_attr "memory" "unknown")])	7787	(set_attr "memory" "unknown")])
7766		7788
7767	(define_insn "sse3_mwait"	7789	(define_insn "sse3_mwait"
Lines 7885-7890 Link Here
7885	"TARGET_SSSE3"	7907	"TARGET_SSSE3"
7886	"phaddw\t{%2, %0\|%0, %2}"	7908	"phaddw\t{%2, %0\|%0, %2}"
7887	[(set_attr "type" "sseiadd")	7909	[(set_attr "type" "sseiadd")
		7910	(set_attr "atom_unit" "complex")
7888	(set_attr "prefix_data16" "1")	7911	(set_attr "prefix_data16" "1")
7889	(set_attr "prefix_extra" "1")	7912	(set_attr "prefix_extra" "1")
7890	(set_attr "mode" "TI")])	7913	(set_attr "mode" "TI")])
Lines 7913-7918 Link Here
7913	"TARGET_SSSE3"	7936	"TARGET_SSSE3"
7914	"phaddw\t{%2, %0\|%0, %2}"	7937	"phaddw\t{%2, %0\|%0, %2}"
7915	[(set_attr "type" "sseiadd")	7938	[(set_attr "type" "sseiadd")
		7939	(set_attr "atom_unit" "complex")
7916	(set_attr "prefix_extra" "1")	7940	(set_attr "prefix_extra" "1")
7917	(set_attr "mode" "DI")])	7941	(set_attr "mode" "DI")])
7918		7942
Lines 7967-7972 Link Here
7967	"TARGET_SSSE3"	7991	"TARGET_SSSE3"
7968	"phaddd\t{%2, %0\|%0, %2}"	7992	"phaddd\t{%2, %0\|%0, %2}"
7969	[(set_attr "type" "sseiadd")	7993	[(set_attr "type" "sseiadd")
		7994	(set_attr "atom_unit" "complex")
7970	(set_attr "prefix_data16" "1")	7995	(set_attr "prefix_data16" "1")
7971	(set_attr "prefix_extra" "1")	7996	(set_attr "prefix_extra" "1")
7972	(set_attr "mode" "TI")])	7997	(set_attr "mode" "TI")])
Lines 7987-7992 Link Here
7987	"TARGET_SSSE3"	8012	"TARGET_SSSE3"
7988	"phaddd\t{%2, %0\|%0, %2}"	8013	"phaddd\t{%2, %0\|%0, %2}"
7989	[(set_attr "type" "sseiadd")	8014	[(set_attr "type" "sseiadd")
		8015	(set_attr "atom_unit" "complex")
7990	(set_attr "prefix_extra" "1")	8016	(set_attr "prefix_extra" "1")
7991	(set_attr "mode" "DI")])	8017	(set_attr "mode" "DI")])
7992		8018
Lines 8073-8078 Link Here
8073	"TARGET_SSSE3"	8099	"TARGET_SSSE3"
8074	"phaddsw\t{%2, %0\|%0, %2}"	8100	"phaddsw\t{%2, %0\|%0, %2}"
8075	[(set_attr "type" "sseiadd")	8101	[(set_attr "type" "sseiadd")
		8102	(set_attr "atom_unit" "complex")
8076	(set_attr "prefix_data16" "1")	8103	(set_attr "prefix_data16" "1")
8077	(set_attr "prefix_extra" "1")	8104	(set_attr "prefix_extra" "1")
8078	(set_attr "mode" "TI")])	8105	(set_attr "mode" "TI")])
Lines 8101-8106 Link Here
8101	"TARGET_SSSE3"	8128	"TARGET_SSSE3"
8102	"phaddsw\t{%2, %0\|%0, %2}"	8129	"phaddsw\t{%2, %0\|%0, %2}"
8103	[(set_attr "type" "sseiadd")	8130	[(set_attr "type" "sseiadd")
		8131	(set_attr "atom_unit" "complex")
8104	(set_attr "prefix_extra" "1")	8132	(set_attr "prefix_extra" "1")
8105	(set_attr "mode" "DI")])	8133	(set_attr "mode" "DI")])
8106		8134
Lines 8187-8192 Link Here
8187	"TARGET_SSSE3"	8215	"TARGET_SSSE3"
8188	"phsubw\t{%2, %0\|%0, %2}"	8216	"phsubw\t{%2, %0\|%0, %2}"
8189	[(set_attr "type" "sseiadd")	8217	[(set_attr "type" "sseiadd")
		8218	(set_attr "atom_unit" "complex")
8190	(set_attr "prefix_data16" "1")	8219	(set_attr "prefix_data16" "1")
8191	(set_attr "prefix_extra" "1")	8220	(set_attr "prefix_extra" "1")
8192	(set_attr "mode" "TI")])	8221	(set_attr "mode" "TI")])
Lines 8215-8220 Link Here
8215	"TARGET_SSSE3"	8244	"TARGET_SSSE3"
8216	"phsubw\t{%2, %0\|%0, %2}"	8245	"phsubw\t{%2, %0\|%0, %2}"
8217	[(set_attr "type" "sseiadd")	8246	[(set_attr "type" "sseiadd")
		8247	(set_attr "atom_unit" "complex")
8218	(set_attr "prefix_extra" "1")	8248	(set_attr "prefix_extra" "1")
8219	(set_attr "mode" "DI")])	8249	(set_attr "mode" "DI")])
8220		8250
Lines 8269-8274 Link Here
8269	"TARGET_SSSE3"	8299	"TARGET_SSSE3"
8270	"phsubd\t{%2, %0\|%0, %2}"	8300	"phsubd\t{%2, %0\|%0, %2}"
8271	[(set_attr "type" "sseiadd")	8301	[(set_attr "type" "sseiadd")
		8302	(set_attr "atom_unit" "complex")
8272	(set_attr "prefix_data16" "1")	8303	(set_attr "prefix_data16" "1")
8273	(set_attr "prefix_extra" "1")	8304	(set_attr "prefix_extra" "1")
8274	(set_attr "mode" "TI")])	8305	(set_attr "mode" "TI")])
Lines 8289-8294 Link Here
8289	"TARGET_SSSE3"	8320	"TARGET_SSSE3"
8290	"phsubd\t{%2, %0\|%0, %2}"	8321	"phsubd\t{%2, %0\|%0, %2}"
8291	[(set_attr "type" "sseiadd")	8322	[(set_attr "type" "sseiadd")
		8323	(set_attr "atom_unit" "complex")
8292	(set_attr "prefix_extra" "1")	8324	(set_attr "prefix_extra" "1")
8293	(set_attr "mode" "DI")])	8325	(set_attr "mode" "DI")])
8294		8326
Lines 8375-8380 Link Here
8375	"TARGET_SSSE3"	8407	"TARGET_SSSE3"
8376	"phsubsw\t{%2, %0\|%0, %2}"	8408	"phsubsw\t{%2, %0\|%0, %2}"
8377	[(set_attr "type" "sseiadd")	8409	[(set_attr "type" "sseiadd")
		8410	(set_attr "atom_unit" "complex")
8378	(set_attr "prefix_data16" "1")	8411	(set_attr "prefix_data16" "1")
8379	(set_attr "prefix_extra" "1")	8412	(set_attr "prefix_extra" "1")
8380	(set_attr "mode" "TI")])	8413	(set_attr "mode" "TI")])
Lines 8403-8408 Link Here
8403	"TARGET_SSSE3"	8436	"TARGET_SSSE3"
8404	"phsubsw\t{%2, %0\|%0, %2}"	8437	"phsubsw\t{%2, %0\|%0, %2}"
8405	[(set_attr "type" "sseiadd")	8438	[(set_attr "type" "sseiadd")
		8439	(set_attr "atom_unit" "complex")
8406	(set_attr "prefix_extra" "1")	8440	(set_attr "prefix_extra" "1")
8407	(set_attr "mode" "DI")])	8441	(set_attr "mode" "DI")])
8408		8442
Lines 8509-8514 Link Here
8509	"TARGET_SSSE3"	8543	"TARGET_SSSE3"
8510	"pmaddubsw\t{%2, %0\|%0, %2}"	8544	"pmaddubsw\t{%2, %0\|%0, %2}"
8511	[(set_attr "type" "sseiadd")	8545	[(set_attr "type" "sseiadd")
		8546	(set_attr "atom_unit" "simul")
8512	(set_attr "prefix_data16" "1")	8547	(set_attr "prefix_data16" "1")
8513	(set_attr "prefix_extra" "1")	8548	(set_attr "prefix_extra" "1")
8514	(set_attr "mode" "TI")])	8549	(set_attr "mode" "TI")])
Lines 8547-8552 Link Here
8547	"TARGET_SSSE3"	8582	"TARGET_SSSE3"
8548	"pmaddubsw\t{%2, %0\|%0, %2}"	8583	"pmaddubsw\t{%2, %0\|%0, %2}"
8549	[(set_attr "type" "sseiadd")	8584	[(set_attr "type" "sseiadd")
		8585	(set_attr "atom_unit" "simul")
8550	(set_attr "prefix_extra" "1")	8586	(set_attr "prefix_extra" "1")
8551	(set_attr "mode" "DI")])	8587	(set_attr "mode" "DI")])
8552		8588
Lines 8754-8759 Link Here
8754	return "palignr\t{%3, %2, %0\|%0, %2, %3}";	8790	return "palignr\t{%3, %2, %0\|%0, %2, %3}";
8755	}	8791	}
8756	[(set_attr "type" "sseishft")	8792	[(set_attr "type" "sseishft")
		8793	(set_attr "atom_unit" "sishuf")
8757	(set_attr "prefix_data16" "1")	8794	(set_attr "prefix_data16" "1")
8758	(set_attr "prefix_extra" "1")	8795	(set_attr "prefix_extra" "1")
8759	(set_attr "mode" "TI")])	8796	(set_attr "mode" "TI")])
Lines 8770-8775 Link Here
8770	return "palignr\t{%3, %2, %0\|%0, %2, %3}";	8807	return "palignr\t{%3, %2, %0\|%0, %2, %3}";
8771	}	8808	}
8772	[(set_attr "type" "sseishft")	8809	[(set_attr "type" "sseishft")
		8810	(set_attr "atom_unit" "sishuf")
8773	(set_attr "prefix_extra" "1")	8811	(set_attr "prefix_extra" "1")
8774	(set_attr "mode" "DI")])	8812	(set_attr "mode" "DI")])
8775		8813
Lines 8956-8962 Link Here
8956	UNSPEC_MOVNTDQA))]	8994	UNSPEC_MOVNTDQA))]
8957	"TARGET_SSE4_1"	8995	"TARGET_SSE4_1"
8958	"%vmovntdqa\t{%1, %0\|%0, %1}"	8996	"%vmovntdqa\t{%1, %0\|%0, %1}"
8959	[(set_attr "type" "ssecvt")	8997	[(set_attr "type" "ssemov")
8960	(set_attr "prefix_extra" "1")	8998	(set_attr "prefix_extra" "1")
8961	(set_attr "prefix" "maybe_vex")	8999	(set_attr "prefix" "maybe_vex")
8962	(set_attr "mode" "TI")])	9000	(set_attr "mode" "TI")])