View | Details | Raw Unified
Collapse All | Expand All

(-) radeon_accel.c (-12 / +7 lines)
 Lines 203-211    Link Here 
	host_path_cntl = INREG(HOST_PATH_CNTL);
	host_path_cntl = INREG(HOST_PATH_CNTL);
	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
	if (rinfo->family == CHIP_FAMILY_R300 ||
	if (IS_R300_VARIANT(rinfo)) {
	    rinfo->family == CHIP_FAMILY_R350 ||
	    rinfo->family == CHIP_FAMILY_RV350) {
		u32 tmp;
		u32 tmp;
		OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
		OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
 Lines 241-249    Link Here 
	INREG(HOST_PATH_CNTL);
	INREG(HOST_PATH_CNTL);
	OUTREG(HOST_PATH_CNTL, host_path_cntl);
	OUTREG(HOST_PATH_CNTL, host_path_cntl);
	if (rinfo->family != CHIP_FAMILY_R300 ||
	if (IS_R300_VARIANT(rinfo))
	    rinfo->family != CHIP_FAMILY_R350 ||
	    rinfo->family != CHIP_FAMILY_RV350)
		OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
		OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 Lines 254-269    Link Here 
{
{
	unsigned long temp;
	unsigned long temp;
	/* disable 3D engine */
	OUTREG(RB3D_CNTL, 0);
	radeonfb_engine_reset(rinfo);
	radeonfb_engine_reset(rinfo);
	radeon_fifo_wait (1);
	radeon_fifo_wait (1);
	if ((rinfo->family != CHIP_FAMILY_R300) &&
	if (IS_R300_VARIANT(rinfo)) {
	    (rinfo->family != CHIP_FAMILY_R350) &&
		temp = INREG(RB2D_DSTCACHE_MODE);
	    (rinfo->family != CHIP_FAMILY_RV350))
		OUTREG(RB2D_DSTCACHE_MODE, temp | (1<<17)); /* FIXME */
	} else {
		OUTREG(RB2D_DSTCACHE_MODE, 0);
		OUTREG(RB2D_DSTCACHE_MODE, 0);
	}
	radeon_fifo_wait (3);
	radeon_fifo_wait (3);
	/* We re-read MC_FB_LOCATION from card as it can have been
	/* We re-read MC_FB_LOCATION from card as it can have been